Zig-Zag Redistribution Layer Profile for Stress-Resistant Packaging
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Solution Overview
Problem
Conventional planar redistribution layers (RDLs) in semiconductor packaging are susceptible to delamination, cracking, and stress damage due to thermal and structural mismatches, limiting their effectiveness and reliability.
Innovation Solution
Implementing a non-planar RDL trace configuration with a 'zig-zag' or 'folding' pattern that includes peaks and valleys, formed using a gradient grayscale mask or multi-exposure process, to enhance stress buffering and adhesion with underlying/overlying passivation layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a planar RDL configuration is used, then the manufacturing process is simple, but the RDL is susceptible to delamination, cracking, and stress damage
Solution Approach 1:
The RDL trace is configured with a non-planar, zig-zag profile containing multiple peaks and valleys instead of a flat surface. This curvature allows the RDL to absorb thermal expansion stress and mechanical deformation through elastic deformation of the zig-zag structure, preventing delamination and cracking while maintaining manufacturing feasibility through standard deposition processes
Solution Approach 2:
The invention changes the geometric parameters of the RDL from a two-dimensional planar configuration to a three-dimensional non-planar configuration with controlled peak and valley heights. This parameter change enables the RDL to accommodate thermal stress and mechanical strain, improving reliability without significantly complicating the manufacturing process
2Ease of manufacture
If wire bonds are used for electrical coupling, then the packaging process is conventional and simple, but the I/O density is limited to the outer perimeter
Solution Approach 1:
The RDL redistributes electrical connections from the two-dimensional outer perimeter (wire bond approach) to a three-dimensional non-planar structure that utilizes vertical height variations. This allows I/O connections to be distributed across the entire top surface area of the semiconductor device, dramatically increasing I/O density while maintaining conventional packaging processes
3Reliability
If the RDL trace has a non-planar configuration with peaks and valleys, then stress buffering and adhesion are improved, but the manufacturing precision requirements increase
Solution Approach 1:
The invention defines specific parameter ranges for the non-planar RDL configuration, including peak height, valley depth, and slope angles, that balance stress buffering performance with manufacturing feasibility. These controlled parameter variations enable improved adhesion and stress resistance while maintaining compatibility with standard semiconductor manufacturing processes
Data Source
AI summary
A semiconductor device package includes a semiconductor device and an electrically conductive pad disposed in contact with a surface of the semiconductor device. The semiconductor device package further includes a redistribution layer (RDL) formed over the electrically conductive pad and the surface of the semiconductor device, and an electrical connector disposed over and electrically coupled to the RDL. The RDL includes a first passivation layer disposed over a surface of the semiconductor device and the electrically conductive pad, and further includes an RDL trace. The RDL trace includes a first portion in contact with the electrically conductive pad, a second portion in contact with one of the electrical connector or an underlying metallization layer in contact with the electrical connector, and a third portion having a non-planar and undulating configuration relative to the surface of the semiconductor device.