Zigzag Scan Line Pixel Array for Parasitic Capacitance Reduction
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Solution Overview
Problem
Conventional pixel arrays suffer from uneven display brightness due to significant differences in gate-drain parasitic capacitance caused by misalignment during manufacturing, leading to insufficient color performance and aperture ratio, which results in poor display quality.
Innovation Solution
A pixel array design with zigzag scan lines and sub-pixels connected to the same data line on both sides, where the first sub-pixel's gate electrode is connected to the (n+1)th scan line and the second sub-pixel's gate electrode is connected to the nth scan line, minimizing parasitic capacitance variations and increasing the aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If gate electrodes and drain electrodes are manufactured through different photo mask processes with precise alignment requirements, then manufacturing complexity increases, but misalignment occurs causing significant gate-drain parasitic capacitance differences and uneven display brightness
Solution Approach 1:
The pixel array is divided into first pixels and second pixels with different electrode configurations. First pixels have gate electrodes connected to first scan lines and drain electrodes connected to first data lines, while second pixels have gate electrodes connected to second scan lines and drain electrodes connected to second data lines. This segmentation allows independent optimization of each pixel type and reduces the impact of misalignment on overall display quality.
Solution Approach 2:
Different regions of the pixel array are assigned different electrode layouts and connection configurations. The first pixels and second pixels have distinct gate electrode and drain electrode arrangements tailored to their specific locations and functions, allowing each region to be optimized for its particular requirements while accommodating manufacturing variations.
2Device complexity
If conventional pixel array layout is used with scan lines between adjacent pixels, then device complexity is reduced, but aperture ratio decreases and display brightness becomes insufficient
Solution Approach 1:
The pixel array layout transitions from a conventional two-dimensional arrangement to a three-dimensional structure with stacked electrodes. The source electrodes and drain electrodes are positioned at different vertical levels, allowing light to pass through from the front surface while maintaining electrical connections through vertical pathways. This dimensional change increases the aperture ratio and improves display brightness without significantly increasing planar complexity.
3Ease of manufacture
If irregularly arranged pixels with scan lines extending linearly are used, then manufacturing simplicity is maintained, but color performance becomes insufficient and aperture ratio decreases
Solution Approach 1:
The pixel array employs asymmetric electrode configurations where first pixels and second pixels have non-identical gate electrode and drain electrode arrangements. This asymmetry allows for optimized color performance in different regions while maintaining manufacturing simplicity through the use of standardized photo mask processes. The asymmetric design enables better control over light emission characteristics and color reproduction.
Data Source
AI summary
A pixel array includes scan lines extended along a row direction in a zigzag manner, data lines extended along a column direction, and pixels connected the scan lines and the data lines. Each pixel arranged in nth row includes a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first transistor and a first pixel electrode. A first gate electrode and a first drain electrode of the first transistor are respectively connected to the (n+1)th scan line and the first pixel electrode. A second sub-pixel includes a second transistor and a second pixel electrode. A second gate electrode and a second drain electrode of the second transistor are respectively connected to the nth scan line and the second sub-pixel electrode. A first source electrode of the first transistor and a second source electrode of the second transistor are connected to the same data line.