Zigzag Slit Structures for 3D NAND Wafer Warpage Control
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Solution Overview
Problem
The existing 3D memory device fabrication techniques face challenges in achieving balanced wafer flatness and efficient gate line deposition due to unbalanced wafer bow and warpage, and the complexity of slit structure etching patterns, which affects memory density and fabrication costs.
Innovation Solution
The implementation of zigzag slit structures that extend vertically through the memory stack and laterally in a zigzag pattern, allowing for simultaneous etching of channel holes and slit openings, reducing wafer bow and warpage, and enabling balanced loading during fabrication, while maintaining the pitch of parallel slit structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional straight slit structures are used for dividing memory regions, then the fabrication process becomes complex with unbalanced wafer loading, but the memory density can be maintained
Solution Approach 1:
The patent applies curvature by transitioning from straight slit structures to zigzag slit structures. The zigzag pattern introduces controlled curvature and angular variations in the slit path, which redistributes the etching load more evenly across the wafer surface during fabrication, thereby reducing unbalanced wafer bow and warpage while maintaining effective memory region division.
Solution Approach 2:
The zigzag slit structure introduces asymmetry in the otherwise symmetric straight slit design. By creating alternating angular deviations in the slit pattern, the design asymmetrically distributes mechanical and thermal stresses during fabrication, leading to more uniform wafer flatness and reduced warpage across different wafer regions.
2Manufacturing precision
If unbalanced wafer bow and warpage occur during fabrication, then memory density can be maintained, but gate line deposition becomes inefficient and fabrication costs increase
Solution Approach 1:
The zigzag pattern's curved geometry redistributes the mechanical load during wafer processing, creating a more uniform stress distribution that maintains wafer flatness. This curvature-based design prevents localized warpage that would otherwise cause deposition defects and rework, thereby improving both precision and productivity.
Solution Approach 2:
The patent changes the geometric parameters of the slit structure from straight lines to zigzag patterns with specific angles and dimensions. This parameter modification alters the stress distribution characteristics during fabrication, leading to improved wafer flatness uniformity and subsequent deposition efficiency.
3Productivity
If straight slit structures are used, then the fabrication process is simpler, but wafer bow and warpage become unbalanced affecting memory density
Solution Approach 1:
The zigzag slit structure's curved geometry acts as a stress-distributing mechanism during wafer fabrication. The alternating angles and curved paths of the slits prevent concentration of mechanical and thermal stresses in specific regions, thereby maintaining stable wafer flatness throughout the fabrication process and preventing warpage-induced memory density variations.
Solution Approach 2:
By introducing asymmetric zigzag patterns instead of symmetric straight lines, the design creates varied stress pathways that prevent localized warpage. This asymmetric geometry ensures more uniform stress distribution across the wafer, stabilizing wafer flatness and maintaining consistent memory density across different fabrication batches.
Data Source
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AI summary
3D memory devices (100,200,300) having zigzag slit structures (324,402,546) and methods for forming the same are disclosed. A 3D memory device (100,200,300) includes a substrate (302,502), a memory stack (310,538) including interleaved conductive layers (306,536) and dielectric layers (308,508) above the substrate (302,502), an array of NAND memory strings (102,304,404,518) each extending vertically through the memory stack (310,538), and a plurality of slit structures (324,402,546) laterally dividing the array of NAND memory strings (102,304,404,518) into a plurality of memory regions. Each of the plurality of slit structures (324,402,546) extends vertically through the memory stack (310,538) and extends laterally in a first zigzag pattern in a plan view.