Vertical Channel Memory Array With Zigzag Word-Line Layout
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Solution Overview
Problem
Current semiconductor memory devices face challenges in reducing the area of each unit device while maintaining efficient operation, particularly with the increasing complexity of device integration.
Innovation Solution
The semiconductor memory device incorporates a vertical channel transistor structure with word lines and channel layers arranged in a zigzag pattern, allowing for efficient electrical connections and reduced device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a vertical channel transistor structure is used, then the device area is reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent transitions from a planar transistor structure to a vertical channel structure, moving the current flow path from the horizontal plane to the vertical dimension. This dimensional change allows multiple transistors to be stacked vertically, significantly reducing the footprint area while maintaining the necessary electrical pathways through carefully designed bit line connections at different vertical levels.
Solution Approach 2:
The patent implements a stacked configuration where channel layers, gate insulating layers, and bit lines are nested vertically one above another. Each bit line is positioned at a specific vertical level to connect to corresponding channel layers, creating a compact nested structure that reduces horizontal area occupation while maintaining functional independence of each transistor unit.
2Ease of operation
If word lines are arranged in a zigzag pattern, then electrical connection efficiency is improved, but structural complexity increases
Solution Approach 1:
The patent employs a zigzag pattern for word line arrangement, replacing straight linear paths with angular curved segments. This curved configuration allows bit lines to efficiently connect to multiple channel layers at different vertical positions without requiring complex three-dimensional routing, improving electrical connection efficiency while keeping the structural pattern relatively simple and manufacturable.
3Productivity
If device integration is increased, then productivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the semiconductor device into multiple discrete vertical stacks, each containing channel layers, gate insulating layers, and bit lines at specific vertical positions. This segmentation allows each unit to be independently formed and controlled during manufacturing, enabling higher overall device integration while maintaining manageable precision requirements for each individual stack through standardized fabrication processes.
Data Source
AI summary
A semiconductor memory device includes: a plurality of word lines extending in a first direction; a plurality of channel layers alternately arranged with the word lines, wherein the channel layers extend in a second direction; and a plurality of bit lines located on the word lines and the channel layers, and extending in a third direction. The bit lines are electrically connected to the channel layers. The plurality of word lines include: a plurality of selected word lines to which a positive voltage is applied; and a plurality of non-selected word lines to which a negative voltage is applied. The plurality of channel layers include: a selected channel layer that is turned on; and a non-selected channel layer that is turned off.