Hardware Accelerator for Scalar Dot Product in zk-SNARK

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Solution Overview

Problem

Current hardware accelerators for the zk-SNARK protocol, while achieving faster computation through parallel processing, do not optimize the computation of the scalar dot product efficiently, leading to suboptimal performance in proof generation and verification.

Innovation Solution

A hardware accelerator that implements the Multi-Scalar Multiplication algorithm using a pipelined architecture with accumulators and elliptic curve adders, splitting scalar values into chunks and using buckets to store cumulative additions, allowing for parallel processing and efficient computation of scalar dot products.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If parallel processing is used to accelerate computation, then computation speed is improved, but computation time is not sufficiently reduced for scalar dot product operations

Engineering Contradiction:
Improvecomputation speedVSAvoidcomputation time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The scalar value is divided into multiple chunks, and the dot product computation is segmented into multiple iterations. Each iteration processes one chunk and updates the accumulator accordingly. This segmentation allows the computation to be broken down into manageable parallelizable units while maintaining correctness through iterative accumulation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The accumulators are pre-configured with bucket structures and memory allocations before the main computation begins. The scalar chunks are prepared and staged for processing. This preliminary setup enables the computation to proceed efficiently without runtime configuration overhead, reducing total computation time.

Inventive Principle:
Principle #10Preliminary action

2Quantity of substance

If scalar values are split into chunks and processed iteratively, then memory efficiency is improved, but device complexity increases

Engineering Contradiction:
Improvememory usageVSAvoidhardware structure
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The accumulator structure is designed to be universal, handling multiple scalar chunks and elliptic curve points through the same bucket and memory infrastructure. The same adder and memory units are reused across iterations rather than being replicated, reducing device complexity while maintaining the ability to process segmented scalars efficiently.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The bucket structure acts as an intermediary between the scalar chunks and the final result. Each bucket temporarily holds partial computation results before being accumulated into the final sum. This intermediary structure simplifies memory management and enables efficient parallel updates without requiring complex direct addressing schemes.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If multiple accumulators and buckets are used for parallel computation, then processing speed is improved, but device complexity increases

Engineering Contradiction:
Improveprocessing throughputVSAvoidnumber of components
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Multiple accumulators are merged into a unified bucket structure where all accumulators share common memory resources and addition logic. Rather than implementing separate complete addition chains for each accumulator, the design merges the addition operations to share hardware resources, reducing the number of adders needed while maintaining parallel processing capability.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The system dynamically allocates and updates bucket contents based on the current iteration and scalar chunk being processed. The accumulator states are dynamically updated through the bucket interface, allowing flexible parallel processing without requiring a fixed static hardware configuration for each possible computation path.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20240080197A1Hardware accelerator for computing a scalar dot product
Publication Date: 2024.03.07 INGONYAMA LTD
  • US20240080197A1 patent drawing
  • US20240080197A1 patent drawing
  • US20240080197A1 patent drawing

AI summary

A hardware accelerator computes a scalar dot product given by Σi=0N−1diPi where di is a scalar of length b bits and Pi is an element in a group. The hardware accelerator includes a plurality A of accumulators addressed by corresponding contiguous partitions of the scalar di, each partition being of length c such thatA=⌈bc⌉and each accumulator containing a plurality B of buckets where B=2c. The value of Pi is entered into each empty accumulator bucket whose value corresponds to the weight of the respective partition associated with the corresponding accumulator or is added to a non-zero value that is already in the bucket, the sum replacing the previous value. An accumulator sums the values in the respective buckets of each accumulator so as to derive A sums, and sums the A computed sums to derive the scalar dot product.