Zmax-mask Occlusion Culling Reduces GPU Memory Traffic
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Solution Overview
Problem
Current depth prepass methods in graphics processing units (GPUs) are inefficient as they require multiple passes and significant memory traffic, especially when dealing with complex scenes and highly tessellated models, due to the need for per-pixel depth computations and feedback loops.
Innovation Solution
The implementation of Zmax-mask occlusion culling, which uses two zmax-values per tile and a zmax-mask to perform accurate hierarchical depth representation without per-pixel depth testing, allowing for efficient occlusion culling within the depth unit and reducing memory traffic by enabling depth writes only in the second pass with a LESS_EQUAL test.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If per-pixel depth computations are performed in the first pass, then depth buffer accuracy is improved, but memory traffic and computational overhead increase significantly
Solution Approach 1:
The patent divides the depth buffer into hierarchical levels (HiZ buffer at tile level and fine depth buffer at pixel level). During the first pass, only HiZ buffer updates are performed without computing per-pixel depths. This segmentation allows the system to maintain depth accuracy where needed while avoiding unnecessary computations in occluded regions, thereby reducing memory traffic and computational overhead.
Solution Approach 2:
The patent performs preliminary occlusion culling using the HiZ buffer before rendering the second pass. By pre-computing tile-level depth bounds (zmin and zmax) during the first pass and using them to cull occluded triangles in the second pass, the system avoids performing per-pixel depth computations for hidden surfaces, thus reducing overall computational overhead and memory traffic.
2Manufacturing precision
If multiple passes are used for rendering, then rendering quality is improved, but rendering time increases
Solution Approach 1:
The patent performs preliminary occlusion culling using the HiZ buffer before rendering the second pass. By pre-computing tile-level depth bounds during the first pass and using them to cull occluded triangles in the second pass, the system avoids performing per-pixel depth computations for hidden surfaces, thus reducing overall computational overhead and memory traffic.
Solution Approach 2:
The patent applies partial depth computation by only updating HiZ buffer values (zmin and zmax) during the first pass without computing complete per-pixel depths. This partial action is sufficient for occlusion culling purposes and allows the system to maintain rendering quality in the second pass while significantly reducing the computational workload compared to full per-pixel depth computation in both passes.
3Measurement precision
If per-pixel depth testing is performed, then occlusion culling accuracy is improved, but device complexity and computational overhead increase
Solution Approach 1:
The patent divides the depth buffer into hierarchical levels (HiZ buffer at tile level and fine depth buffer at pixel level). During the first pass, only HiZ buffer updates are performed without computing per-pixel depths. This segmentation allows the system to maintain depth accuracy where needed while avoiding unnecessary computations in occluded regions, thereby reducing memory traffic and computational overhead.
Solution Approach 2:
The patent introduces the HiZ buffer as an intermediary data structure between the scene geometry and the final pixel rendering. The HiZ buffer stores tile-level depth bounds (zmin and zmax) that serve as a coarse approximation of the depth buffer, enabling fast occlusion culling decisions without requiring detailed per-pixel depth information. This intermediary layer simplifies the computational complexity while maintaining sufficient accuracy for culling purposes.
Data Source
AI summary
An apparatus, method, and machine-readable medium for performing masked occlusion culling. For example, one embodiment of an apparatus comprises: incremental scene rendering circuitry/logic to incrementally render a first portion of a scene in a first buffer and a second portion of a scene in a second buffer; buffer merging circuitry/logic to merge the first portion of the scene and the second portion of the scene to generate merged scene data; and masked occlusion culling (MOC) circuitry/logic, responsive to a mask value in an occlusion query (OQ) mask buffer, to perform depth testing and occlusion culling operations on the merged scene data.