ZNS Storage Parallel Writes via Zone Cache

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Solution Overview

Problem

Existing ZNS storage devices are limited by their requirement for in-order writes, which results in unsatisfactory write performance and increased computational resource consumption when dealing with large data storage needs.

Innovation Solution

A storage device with a ZONE switcher, ZONE cache, and ZONE persistence controller that allows out-of-order writes by caching data in a ZONE cache and writing it in parallel to multiple ZONEs in the NAND chip array, independent of the application's write order.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If in-order write is enforced in ZNS storage devices, then data consistency is maintained, but write performance deteriorates due to sequential processing requirements

Engineering Contradiction:
Improvedata consistencyVSAvoidwrite performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The storage device divides the storage space into multiple independent ZONES, each capable of being managed separately. The controller segments write operations by identifying different ZONES within the same LBA range and routing them to appropriate physical blocks, allowing parallel processing of writes to different zones while maintaining in-order writes within each zone.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The controller acts as an intermediary between the host and the storage medium. It receives write commands from the host, identifies the target ZONE, and intelligently maps logical block addresses to physical blocks that can be written in parallel. This mediator function allows the system to maintain the in-order write constraint while achieving parallel write performance through sophisticated address mapping.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If synchronous IO mode is used to ensure in-order write, then data consistency is maintained, but write performance deteriorates due to blocking operations

Engineering Contradiction:
Improvedata consistencyVSAvoidwrite latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system dynamically adjusts the write operation mode based on the target ZONE. When multiple ZONES are identified as targets for write operations, the controller dynamically switches to parallel write mode for those zones. This dynamic adaptation allows the system to maintain data consistency for zones requiring in-order writes while achieving high-performance parallel writes for zones that can tolerate out-of-order operations.

Inventive Principle:
Principle #15Dynamics

3Productivity

If data is distributed across multiple ZONES to increase write performance, then parallel write capability is improved, but computational resource consumption increases

Engineering Contradiction:
Improvewrite performanceVSAvoidcomputational resource consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The storage device performs self-service by automatically identifying and managing multiple ZONES within the same LBA range without requiring host intervention. The controller independently determines which ZONES can be written in parallel, manages the address mapping, and coordinates the parallel write operations. This self-service capability reduces the computational burden on the host system while achieving high write performance through parallel operations.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12293095B2Storage device and data access method thereof
Publication Date: 2025.05.06 SAMSUNG ELECTRONICS CO LTD
  • US12293095B2 patent drawing
  • US12293095B2 patent drawing
  • US12293095B2 patent drawing

AI summary

A storage device includes: a NAND chip array having a plurality of NAND chips; a ZONE switcher configured to control output of write data to a ZONE cache when a ZONE write command is received; the ZONE cache configured to cache the write data in a cache space corresponding to a ZONE among a plurality of zones; and a ZONE persistence controller configured to control storing, in parallel, the write data in at least two of the plurality of ZONEs cached in the ZONE cache in NAND chips of the NAND chip array corresponding to the plurality of ZONEs.