ZOGaN Light-Emitting Structure With Uniform Mesa Etching
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Solution Overview
Problem
GaN-based light emitting devices face issues with low internal quantum efficiency due to lattice mismatch and hole-electron imbalance, leading to strain and efficiency droop, and current etching technologies are inadequate for zinc-oxide based semiconductors, resulting in undercuts and poor etching uniformity.
Innovation Solution
A method for manufacturing a ZOGaN light emitting device using a multilayer structure of GaN-based nitride and ZnO-based oxide semiconductors, employing a novel etching process that allows for precise etching of each material separately, including dry etching with (BCl3, Cl2, Ar) gases and wet etching with diluted chemical solutions, to form a mesa structure with a transparent p-electrode layer for improved hole injection and surface protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching technology is used on zinc-oxide based semiconductors, then the etching process can be performed, but undercuts are formed and etching uniformity is poor
Solution Approach 1:
The patent applies parameter changes by modifying etching conditions including using a two-step etching process (dry etching followed by wet etching), controlling etching time and temperature, and adjusting chemical solution concentration to achieve uniform etching without undercuts on zinc-oxide based semiconductors
Solution Approach 2:
The patent introduces an intermediary approach by using a combination of dry and wet etching methods, where each method compensates for the limitations of the other, to achieve precise and uniform etching results on zinc-oxide based semiconductor materials
2Reliability
If AlGaN EBL layer is added to block electron overflowing, then electron leakage is reduced, but electrons accumulate at the EBL-QW boundary creating strong electric field and strain
Solution Approach 1:
The patent applies local quality by creating a compositional gradient in the AlGaN EBL layer, where the aluminum composition varies spatially to provide different local properties: higher aluminum content near the QW to block electrons while lower aluminum content at the boundary to reduce strain accumulation
Solution Approach 2:
The patent changes the aluminum composition parameter across the EBL layer thickness, transitioning from higher to lower aluminum content, which simultaneously maintains electron blocking capability while reducing the strong electric field and strain at the boundary region
3Reliability
If more holes are supplied from p-type layer to active layer, then internal quantum efficiency is improved, but the complexity of achieving sufficient hole injection increases
Solution Approach 1:
The patent introduces a p-type zinc-oxide based semiconductor layer as an intermediary between the p-type GaN layer and the active layer. This intermediary layer facilitates hole injection into the active layer by providing a favorable energy band alignment and reducing the hole injection barrier, thereby improving internal quantum efficiency without significantly increasing device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the internal quantum efficiency of light emitting devices by addressing strain and etching challenges, enabling high production yield and precise pattern alignment for next-generation displays with improved luminous efficiency and reduced manufacturing costs.
Implementation Method 1
employing a novel etching process that allows for precise etching of each material separately, including dry etching with (BCl3, Cl2, Ar) gases and wet etching with diluted chemical solutions
Data Source
AI summary
A device for facilitating emitting light is disclosed. Accordingly, the device may include at least one substrate, at least one first layer configured to be placed on the at least one substrate. Further, the at least one first layer may be an n-type nitride based semiconductor layer. At least one second layer configured to be placed on the at least one first layer. Further, the at least one second layer may be a nitride based semiconductor. At least one third layer configured to be placed on the at least one second layer. Further, the at least one third layer may be a p-type semiconductor layer. At least one fourth layer configured to be placed on the at least one third layer. Further, the at least one fourth layer may include at least one transparent electrode.