Zone-Based Optimization Framework for MCMM Timing
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Solution Overview
Problem
Conventional circuit optimization techniques face runtime bottlenecks and poor Quality of Results (QoR) due to exponential complexity in timing updates and inadequate handling of multi-mode multi-corner (MCMM) scenarios, often failing to converge on an optimal solution.
Innovation Solution
A zone-based optimization framework that selects optimizing transformations for logic gates without degrading timing metrics in local and broader circuit contexts, rejecting transformations that worsen metrics in any MCMM scenario, and propagating timing information efficiently within defined zones to reduce computational expense.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional techniques perform full timing update of the entire circuit whenever a logic gate is changed, then timing accuracy is maintained, but computational complexity becomes exponential and runtime becomes excessive
Solution Approach 1:
The patent divides the circuit into zones around each logic gate being optimized. Only timing updates are performed within these localized zones rather than across the entire circuit, reducing computational complexity from exponential to manageable levels while maintaining sufficient timing accuracy for the optimization task.
Solution Approach 2:
The patent applies different timing update strategies to different regions of the circuit. Full timing accuracy is maintained locally around the logic gate being optimized, while distant regions receive approximate or no timing updates, achieving a balance between accuracy and computational efficiency.
2Loss of time
If conventional techniques impose a time limit on the optimization process, then runtime is controlled and termination is guaranteed, but Quality of Results (QoR) deteriorates
Solution Approach 1:
The optimization process is segmented into zone-based iterations where only relevant circuit regions are updated each time. This allows the optimizer to make meaningful progress within time limits without requiring exhaustive full-circuit timing updates, maintaining QoR while controlling runtime.
Solution Approach 2:
The patent performs partial timing updates only in necessary zones rather than complete circuit updates. This partial action approach achieves sufficient optimization quality within practical time limits by focusing computational effort where it matters most for the current optimization step.
3Ease of operation
If conventional techniques optimize each MCMM scenario independently, then each scenario can be processed separately, but convergence fails and overall optimization efficiency decreases
Solution Approach 1:
The patent merges the optimization processes across multiple MCMM scenarios by maintaining a unified zone-based timing update framework. Transformations are evaluated and applied considering their impact across all scenarios simultaneously, enabling convergence while still allowing independent scenario characteristics to be preserved in the evaluation criteria.
Data Source
AI summary
Some embodiments of the present invention provide techniques and systems for efficiently optimizing a circuit design for one or more multi-mode multi-corner (MCMM) scenarios. A system can select an optimizing transformation for a logic gate, which if applied to the logic gate, does not degrade a timing metric in a local context of the logic gate. Next, the system can determine whether applying the optimizing transformation to the logic gate degrades the timing metric in a zone around the logic gate. If so, the system can reject the optimizing transformation. Otherwise, the system can determine whether applying the optimizing transformation to the logic gate degrades the timing metric in the circuit design. If so, the system can reject the optimizing transformation. Otherwise, the system can accept the optimizing transformation.