Zone Memory Block Failure Protection via Parity Matching

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Solution Overview

Problem

Conventional memory sub-systems face challenges in efficiently managing block failures during programming of multi-level cell (MLC), triple-level cell (TLC), or quad-level cell (QLC) blocks, leading to high overprovisioning of SLC cache blocks and reduced competitiveness.

Innovation Solution

The implementation of block failure protection in a memory sub-system that supports zones involves matching non-parity zones filling up at similar rates, generating parity for a stripe of data across these zones, and storing the parity in a parity zone, thereby reducing the need for SLC cache blocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional memory sub-systems use SLC cache blocks for block failure protection during programming of MLC/TLC/QLC blocks, then reliability is improved, but device complexity and overprovisioning increase

Engineering Contradiction:
Improveblock failure protectionVSAvoidoverprovisioning of SLC cache blocks
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The memory sub-system is divided into zones with different protection levels. Non-parity zones store data without full redundancy, while parity zones provide selective protection. This segmentation allows the system to implement failure protection only where needed during programming operations, rather than uniformly across all blocks, thereby reducing overall overprovisioning while maintaining reliability for critical operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different zones are assigned different quality levels of protection based on their specific needs. Parity zones receive enhanced failure protection mechanisms, while non-parity zones use standard protection. This local differentiation allows the system to optimize reliability for zones most susceptible to programming failures without unnecessarily protecting zones that have lower risk profiles, thus reducing device complexity and overprovisioning.

Inventive Principle:
Principle #3Local quality

2Reliability

If SLC cache blocks are used for failure protection, then reliability during programming is improved, but productivity decreases due to reduced usable capacity

Engineering Contradiction:
Improvefailure protection during programmingVSAvoidusable capacity
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By segmenting the memory into parity and non-parity zones, the system provides failure protection only for the parity zone portion of the capacity. This allows a larger proportion of the total memory to be usable compared to a uniform protection scheme, thereby improving productivity while maintaining reliability where it matters most during programming operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system applies failure protection partially - only to parity zones during programming operations - rather than excessively protecting all zones. This partial application of protection mechanisms maintains sufficient reliability for critical programming operations while preserving more usable capacity, thus improving productivity without sacrificing essential reliability.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20250138944A1Block failure protection for zone memory system
Publication Date: 2025.05.01 MICRON TECHNOLOGY INC
  • US20250138944A1 patent drawing
  • US20250138944A1 patent drawing
  • US20250138944A1 patent drawing

AI summary

Various embodiments provide block failure protection for a memory sub-system that supports zones, such a memory sub-system that uses a RAIN (redundant array of independent NAND-type flash memory devices) technique for data error-correction. For some embodiments, non-parity zones of a memory sub-system that are filling up at a similar rate are matched together, a parity is generated for stored data from across the matching zones, and the generated parity is stored in a parity zone of the memory device.