Zone Memory Read-Verify Recovery During SLC-QLC Migration

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Solution Overview

Problem

Conventional zone memory sub-systems face challenges in handling block read-verify failures during data migration and refresh operations, leading to data loss or corruption, especially in non-cache blocks like QLC blocks, which affect data integrity and system reliability.

Innovation Solution

The memory sub-system employs a zone-based architecture with SLC cache blocks and QLC non-cache blocks, incorporating mechanisms to handle read-verify failures by moving affected zones to a read-only state, reallocating new QLC blocksets, and performing error checks, ensuring data integrity and reliability through processes like SLC to QLC migration and error handling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If read-verify failure handling is implemented in zone memory sub-systems, then data integrity is improved, but system complexity increases

Engineering Contradiction:
Improvedata integrityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system divides the memory device into zones, each with independent state management. When a read-verify failure occurs in one zone, only that zone is affected and handled independently, while other zones continue to operate normally. This segmentation isolates failures and simplifies the overall error handling mechanism.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system introduces an intermediary error handling mechanism that detects read-verify failures, determines affected zones, and coordinates recovery operations. This intermediary layer manages the complexity of failure detection and recovery without exposing the host system to detailed error handling complexities.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If read-verify failure handling mechanisms are added, then data integrity is improved, but processing time increases

Engineering Contradiction:
Improvedata integrityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs read-verify operations during the normal data migration process from cache blocks to non-cache blocks, rather than separately afterward. This preliminary verification integrates error detection into the existing workflow, avoiding additional time penalties.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

When a read-verify failure is detected, the system quickly identifies the affected zone and skips unnecessary verification operations for other zones. The error handling process rushes through essential steps (marking zone as read-only, reallocating blocks) without performing exhaustive checks, thereby minimizing time loss.

Inventive Principle:
Principle #21Skipping (Rushing through)

3Reliability

If zone-based architecture with error handling is implemented, then system reliability is improved, but device complexity increases

Engineering Contradiction:
Improvesystem reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The memory device is segmented into multiple zones with independent state machines. Each zone maintains its own read-only status and error state, allowing localized error handling without affecting the entire device. This segmentation reduces the propagation of errors and simplifies the overall system state management.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically adjusts zone states based on error conditions. When a read-verify failure occurs, the affected zone transitions to a read-only state, and the system dynamically reallocates blocks within that zone. This dynamic state management adapts the system behavior to current conditions without requiring complex static error handling structures.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20260037140A1Handling read-verify failure in zone memory system
Publication Date: 2026.02.05 MICRON TECHNOLOGY INC
  • US20260037140A1 patent drawing
  • US20260037140A1 patent drawing
  • US20260037140A1 patent drawing

AI summary

Various embodiments provide handling block read-verify failure in a memory sub-system that supports zones. In particular, some embodiments described herein handle block read-verify failure during migration (e.g., copyback) of data from one or more cache blocks to one or more non-cache blocks of a zone on a memory device on a memory sub-system, during non-cache block (e.g., QLC non-cache block) refresh, or both.