Zoned Nonvolatile Memory Allocation for Faster Garbage Collection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing storage devices face challenges in improving operating speed and managing storage space efficiently, particularly in nonvolatile memory devices, which affect the performance of host devices such as computers and smartphones.

Innovation Solution

A storage device with a nonvolatile memory device and a controller that allocates zones based on a zone map table, performs garbage collection as a background operation, and manages logical addresses sequentially, utilizing multiple memory chips and blocks with erase units to optimize data allocation and retrieval.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If traditional storage space management is used without zone allocation, then the storage device structure is simpler, but the operating speed and data access efficiency deteriorate

Engineering Contradiction:
Improveoperating speedVSAvoidstorage space management complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The storage space is divided into multiple zones, each zone containing multiple erase units. This segmentation allows parallel processing of different zones during garbage collection and data access operations, improving operating speed while maintaining manageable complexity through structured organization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The zone map table is pre-configured with zone allocations and erase unit mappings before data operations begin. This preliminary organization enables faster data access and garbage collection by eliminating the need for dynamic space management during operations, thus improving speed without proportionally increasing complexity.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If garbage collection is performed synchronously with host requests, then resource utilization is lower, but the responsiveness to host requests is better

Engineering Contradiction:
Improveresource utilizationVSAvoidhost request waiting time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

Garbage collection is performed periodically as background operations at predetermined intervals rather than synchronously with each host request. This periodic execution improves resource utilization by keeping garbage collection circuits active and processing data continuously, while the asynchronous nature prevents blocking of host requests, thus reducing perceived waiting time.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The garbage collection process operates continuously in the background without interrupting host data operations. Multiple garbage collection circuits process different zones simultaneously, ensuring continuous useful action is performed on storage resources while maintaining responsiveness to host requests.

Inventive Principle:
Principle #20Continuity of useful action

3Productivity

If multiple garbage collection circuits are used for parallel processing, then the garbage collection speed is improved, but the device complexity increases

Engineering Contradiction:
Improvegarbage collection speedVSAvoidcontroller circuit complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The garbage collection function is divided into multiple independent circuits, each responsible for processing specific zones. This segmentation enables parallel processing across zones, improving garbage collection speed while keeping each individual circuit relatively simple and manageable.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple garbage collection circuits are merged into a unified controller architecture that shares common resources such as the zone map table and memory interfaces. This merging approach achieves parallel processing capability while avoiding proportional increases in overall device complexity through resource sharing.

Inventive Principle:
Principle #5Merging (Combining)

4Speed

If erase units are selectively allocated to zones based on zone map table, then the data access efficiency is improved, but the management complexity increases

Engineering Contradiction:
Improvedata access efficiencyVSAvoidzone management complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The zone map table is pre-configured with optimal mappings between zones and erase units based on expected data access patterns. This preliminary action establishes efficient data access paths before operations begin, improving data access efficiency while avoiding the need for complex dynamic decision-making during operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The zone map table serves as an intermediary data structure that simplifies the mapping between logical zones and physical erase units. This intermediary layer abstracts the complexity of selective allocation, providing efficient data access through structured lookup while keeping the management logic centralized and manageable.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12504899B2Storage device including nonvolatile memory device and operating method of storage device
Publication Date: 2025.12.23 SAMSUNG ELECTRONICS CO LTD
  • US12504899B2 patent drawing
  • US12504899B2 patent drawing
  • US12504899B2 patent drawing

AI summary

A storage device, including: a nonvolatile memory device including a plurality of memory cells; and a controller configured to: allocate a plurality of zones to a storage space of the nonvolatile memory device based on a request received from an external host device, select two or more erase units to be allocated to each of the plurality of zones based on a zone map table, fixedly and sequentially manage logical addresses of data written in the plurality of zones, wherein the nonvolatile memory device includes a plurality of memory chips, wherein each memory chip of the plurality of memory chips includes a plurality of memory blocks, wherein each memory block of the plurality of memory blocks includes at least two erase units, and wherein the controller is further configured to select at least one erase unit from the each memory block to be allocated to a zone.