Zoned Memory Cell Storage With Journal Updates for Write Wear

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Solution Overview

Problem

Existing storage devices face challenges in optimizing space utilization and managing data writes efficiently, particularly in high-speed data processing systems, leading to potential inefficiencies and reduced lifespan of memory cells.

Innovation Solution

Implementing a storage device with memory cells divided into two types (e.g., SLC, MLC, TLC, QLC) and a memory controller that manages data writes and updates, limiting writes to certain cells and using a journal area for overwritten data, along with optional compression/decompression to optimize space utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If memory cells are used to store large amounts of data at high speed, then data processing speed and storage capacity are improved, but space utilization and memory cell lifespan deteriorate due to excessive write operations

Engineering Contradiction:
Improvedata processing speedVSAvoidmemory cell lifespan
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The memory device is divided into two distinct groups: first group memory cells with higher endurance that handle frequent write operations, and second group memory cells with lower endurance that store stable data. This segmentation allows each group to be optimized for its specific function, improving overall system reliability while maintaining high data processing speed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different quality characteristics are assigned to different parts of the memory device. The first group memory cells are designed with higher write endurance (local quality for frequent updates), while the second group memory cells are designed for stable storage (local quality for data retention). This local quality differentiation resolves the contradiction by matching cell characteristics to operational requirements.

Inventive Principle:
Principle #3Local quality

2Quantity of substance

If compression and decompression are implemented to increase memory usage efficiency, then space utilization is improved, but device complexity increases

Engineering Contradiction:
Improvespace utilizationVSAvoiddevice complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The host device performs compression and decompression operations using its own processing resources rather than requiring dedicated compression hardware in the storage device. This self-service approach improves space utilization while avoiding the addition of complex compression/decompression circuitry to the storage device, thus maintaining simplicity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12366964B2Storage device operated by zone and data processing system including the same
Publication Date: 2025.07.22 SAMSUNG ELECTRONICS CO LTD
  • US12366964B2 patent drawing
  • US12366964B2 patent drawing
  • US12366964B2 patent drawing

AI summary

A storage device operated by zone and data processing system including the same are provided. A storage device comprises a memory device including a plurality of memory blocks including a plurality of memory cells connected to a plurality of gate lines, and a memory controller controlling the memory device, wherein memory cells of a first group among the plurality of memory cells include cells of a first type, memory cells other than the memory cells of the first group among the plurality of memory cells are defined as a second group, and the memory cells of the second group include cells of a second type different from the first type, the memory controller is configured to transmit size information of the memory cells of the first group so that the host programs data into the memory cells of the first group, and store an update of the data programmed in the memory cells of the first group with respect to the memory cells of the second group, and the host does not perform a plurality of write requests to the same address with respect to the memory cells of the first group more than twice.