Zoned Write Mapping for Non-Sequential Storage Commands

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Solution Overview

Problem

Memory systems operating with zoned storage protocols face challenges in processing non-sequential write commands, leading to increased write latency and command rejections, which complicates high-traffic operations.

Innovation Solution

Implementing a memory system configured with a write counter and bitmap for each zone to manage non-sequential write commands, allowing data to be written to available physical block addresses while rejecting data to previously written logical block addresses, thus maintaining zone integrity and improving performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If zoned storage protocols enforce sequential write commands, then zone integrity is maintained, but write latency increases and command rejections occur

Engineering Contradiction:
Improvezone integrityVSAvoidwrite latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The memory device is divided into multiple independent zones, each with its own write counter and state machine. This segmentation allows parallel processing of write commands across different zones, reducing overall latency while maintaining sequential integrity within each individual zone. The controller can independently manage writes to zone 0, zone 1, zone 2, etc., simultaneously.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A write pointer is introduced as an intermediary mechanism between the host controller and the physical memory zones. The write pointer tracks the current write position within each zone and enables the state machine to determine whether incoming write commands are sequential or random, allowing the system to accept random writes when the zone is in the appropriate state while maintaining zone integrity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If zoned storage protocols reject non-sequential write commands, then zone structure is preserved, but productivity decreases due to command rejections

Engineering Contradiction:
Improvezone structureVSAvoidwrite throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The zone state machine dynamically transitions between states (empty, open, closed, full) based on the current write pattern and zone conditions. When a zone is in the 'open' state, it accepts sequential writes; when transitioning to 'closed', it can accept random writes by updating the write pointer. This dynamic adaptation allows the system to maximize productivity by accepting valid random writes while maintaining zone structure through proper state management.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the operational parameters of zone acceptance based on the current state. The write counter threshold and state machine conditions are adjusted dynamically - when the write counter indicates available space and the state permits, random write commands are accepted and the write pointer is updated accordingly. This parameter change enables the system to differentiate between acceptable and unacceptable random writes, improving throughput without compromising zone integrity.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20260003510A1Zoned random write operations
Publication Date: 2026.01.01 MICRON TECHNOLOGY INC
  • US20260003510A1 patent drawing
  • US20260003510A1 patent drawing
  • US20260003510A1 patent drawing

AI summary

Methods, systems, and devices for zoned random write operations are described. A memory system may receive a set of write commands associated with respective logical block addresses (LBAs) that may be in a sequential order, where the respective LBAs may be associated with a zone. The memory system may write first data to a first physical block address (PBA), where the first data may be associated with a first LBA of the respective LBAs. The memory system may determine whether a second LBA associated with second data is sequential relative to a write pointer associated with the zone. The memory system may write the second data to a second PBA that may be sequential to the first PBA in response to determining that the second logical block address is non-sequential relative to the write pointer and on a value of a bitmap corresponding to the second LBA.