Z-PAT Outlier Detection Using Wafer Defect Signatures
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional Z-PAT methodologies in semiconductor manufacturing result in excessive yield loss and overkill due to their inability to identify the underlying cause of reliability failures, particularly latent reliability defects (LRD), leading to reactive adjustments rather than proactive prevention.
Innovation Solution
A system and method for Z-direction Part Average Testing (Z-PAT) that incorporates defect-guided statistical outlier detection using characterization data, spatial signature analysis, and machine learning to identify Z-PAT defect signatures, enabling precise identification of potential reliability failures and reducing overkill by providing insights into causal mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional statistical outlier detection methods are used, then the detection process is simple, but the detection precision is insufficient to distinguish process variations from device defects
Solution Approach 1:
The system performs preliminary actions by conducting design rule checks, logic synthesis, and gate-level simulations before the outlier detection process. These preliminary steps prepare the circuit design data in advance, organizing defect information and simulation results so that the subsequent statistical outlier detection can focus specifically on comparing measured data against pre-computed expected behavior, thereby improving detection precision without adding complexity to the core detection algorithm.
Solution Approach 2:
The system introduces an intermediary layer of z-pattern templates that represent expected circuit behavior under various defect conditions. These templates act as mediators between the raw measured data and the defect detection logic. By comparing measured z-patterns against a library of pre-computed templates representing different defect types, the system achieves high detection precision while keeping the actual detection process relatively simple, as the complex defect modeling is encapsulated in the templates rather than the detection algorithm itself.
2Measurement precision
If comprehensive defect analysis is performed to improve detection accuracy, then the detection precision improves, but the processing time increases
Solution Approach 1:
The system performs comprehensive defect analysis in advance during the template generation phase. Z-pattern templates are pre-computed for various defect conditions using detailed circuit simulations and defect modeling. This preliminary action captures complex defect behaviors beforehand, so that during actual production testing, the system only needs to compare measured data against these pre-analyzed templates, achieving high detection accuracy with minimal processing time.
Solution Approach 2:
The system uses periodic action by implementing a two-stage process: an offline phase where comprehensive defect analysis and template generation are performed periodically or as needed, and an online phase where rapid comparison against templates is performed for each device. This separation allows computationally intensive defect analysis to be done when processing time is less critical, while production testing benefits from fast template-based comparison.
3Reliability
If detailed circuit simulation and defect modeling are used, then the reliability of defect identification improves, but the computational resources and complexity increase
Solution Approach 1:
The system creates simplified copies of circuit behavior in the form of z-pattern templates that capture essential defect characteristics without requiring full circuit simulations during detection. These templates are copied representations of expected behavior under various defect conditions, allowing the system to achieve high defect identification reliability through comparison against multiple template copies rather than performing complex simulations for each device tested.
Solution Approach 2:
The system segments the complex defect analysis task into separate, manageable components: circuit simulation to generate ideal z-patterns, defect modeling to create defective z-patterns, and template generation to compile these into a lookup library. This segmentation allows each component to be optimized independently and enables parallel processing, reducing overall system complexity while maintaining high reliability through comprehensive coverage of different defect scenarios.
Data Source
Figure 1
Figure 2
Figure 3A
AI summary
A system and method for Z-PAT defect-guided statistical outlier detection of semiconductor reliability failures includes receiving electrical test bin data with semiconductor die data for a plurality of wafers in a lot generated by a statistical outlier detection subsystem configured to perform Z-direction Part Average Testing (Z-PAT) on test data generated by an electrical test subsystem after fabrication of the plurality of wafers in the lot, receiving characterization data for the plurality of wafers in the lot generated by a semiconductor fab characterization subsystem during the fabrication of the plurality of wafers in the lot, determining a statistical correlation between the electrical test bin data and the characterization data at a same x, y position on each of the plurality of wafers in the lot, and locating defect data signatures on the plurality of wafers in the lot based on the statistical correlation.