ZQ Calibration Circuit With Charge Injection for Multi-Die Memory
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Solution Overview
Problem
Semiconductor memory devices face challenges in reducing signal transmission time and minimizing impedance mismatching, leading to increased external noise and signal reflection, which are not adequately addressed by existing ZQ calibration methods, especially in multi-die packages where increased loading capacitance prolongs calibration execution time.
Innovation Solution
A memory device with a ZQ calibration circuit that includes a driver connected to an external ZQ resistor in series, a charge injection circuit with an AC coupling capacitor, and a comparator to adjust resistance values, facilitating faster ZQ calibration by injecting charges in the direction of voltage level changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If signal swing width is reduced to minimize transmission time, then transmission time is reduced, but external noise influence and signal reflection increase
Solution Approach 1:
The patent changes the impedance parameter of the memory device by adjusting the on-die termination resistance through ZQ calibration. The calibration circuit modifies the resistance value to match the impedance of the memory controller, thereby reducing signal reflection and noise while maintaining reduced signal swing width for fast transmission.
2Reliability
If ZQ calibration is performed to adjust resistance values, then impedance matching is improved, but calibration execution time increases due to loading capacitance in multi-die packages
Solution Approach 1:
The patent performs preliminary charge injection into the ZQ calibration node before the actual resistance adjustment process. This pre-charging action reduces the time required for the voltage to reach stable levels during calibration, thereby accelerating the overall calibration execution time without compromising impedance matching accuracy.
Solution Approach 2:
The calibration circuit uses periodic toggling of the ZQ calibration node between different voltage levels to rapidly sample and determine the optimal resistance value. This periodic switching approach enables faster convergence of the calibration process compared to traditional sequential adjustment methods.
3Reliability
If on-die termination resistance is adjusted to match memory controller resistance, then signal integrity is improved, but calibration complexity increases
Solution Approach 1:
The calibration circuit automatically determines the optimal resistance value by comparing voltage levels at the ZQ calibration node with reference voltages. The circuit self-adjusts the on-die termination resistance without requiring external intervention or complex control logic, thereby maintaining signal integrity while limiting complexity growth.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution reduces ZQ calibration execution time and improves signal integrity in multi-die packages, enhancing overall memory device performance.
Implementation Method 1
a charge injection circuit including a buffer and an alternating current (AC) coupling capacitor
Data Source
AI summary
Provided is a memory device including a plurality of memories and a ZQ resistor, wherein a first memory from among the plurality of memories includes a ZQ pin connected to the above ZQ resistor, and a ZQ calibration circuit configured to perform a ZQ calibration operation, the ZQ calibration circuit includes a driver, and a charge injection circuit, which includes a buffer and an AC coupling capacitor, is connected to the ZQ pin, and receives a charge injection signal, in response to a voltage level of a ZQ node being higher than a level of a reference voltage, the charge injection signal transitions from logic high to logic low, and, in response to the voltage level of the ZQ node being lower than the level of the reference voltage, the charge injection signal transitions from logic low to logic high.