Shared ZQ Resistor Arbitration Using Unique Chip Timing Patterns
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in efficiently managing ZQ resistor access for multiple chips, leading to prolonged calibration times due to the exponential increase in required delay variations as the number of chips increases, particularly in low-power consumption and multi-chip packages.
Innovation Solution
A time-based arbitration scheme with unique ZQ timing patterns for each chip, where the arbiter circuit uses a combination of pull-up and pull-down driver circuits and a comparator to determine access to the shared ZQ resistor, allowing multiple chips to calibrate simultaneously without extending calibration time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a voltage based arbitration scheme is used to determine ZQ calibration request priority, then the arbitration can be implemented with simple circuitry, but chip packages with multiple-chips and low-power consumption types cannot effectively differentiate between multiple states
Solution Approach 1:
The patent changes the arbitration parameter from voltage level (voltage based arbitration) to time delay (time based arbitration). Each chip is programmed with a unique time delay value, allowing multiple chips to be differentiated by their timing characteristics rather than voltage levels. This enables effective state differentiation in low-power devices where voltage based schemes fail.
2Adaptability or versatility
If a time based arbitration scheme with unique time delay for each chip is used, then any number of chips can use the ZQ resistor, but the required time increases exponentially according to the number of chips
Solution Approach 1:
The patent merges multiple arbitration functions into a single arbitration circuit that handles all chips simultaneously. The arbiter circuit compares timing patterns from multiple chips in parallel and grants access based on the earliest valid pattern, rather than sequentially processing each chip. This reduces the exponential time increase to a linear or logarithmic relationship with the number of chips.
Solution Approach 2:
The patent introduces dynamic timing patterns where each chip has a programmable unique time delay that can be configured optimally. The arbitration system dynamically identifies and responds to the earliest timing pattern, allowing flexible adaptation to different chip configurations and minimizing total calibration time.
3Reliability
If multiple chips request ZQ resistor access simultaneously, then comprehensive impedance calibration can be achieved, but sequential access increases total calibration time
Solution Approach 1:
The patent applies preliminary action by programming each chip with its unique time delay value before the arbitration process begins. This pre-configured timing information allows the arbitration circuit to quickly determine access priority without extensive negotiation or sequencing during the actual calibration process, reducing total calibration time while maintaining comprehensive coverage of all chips.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient ZQ calibration for semiconductor memory devices with multiple chips by reducing the time required for arbitration, ensuring high-speed memory access and maintaining low power consumption.
Implementation Method 1
using an arbiter circuit that compares ZQ pad voltage with a reference voltage to determine access priority
Data Source
AI summary
Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor and a calibration circuit. The calibration circuit determines whether the resistor is available based, at least in part, on timing information that is unique to a corresponding chip of the plurality of chip. The timing information of each chip of the plurality of chips has a fixed duration of time common to the plurality of chips.