ZrHfMO Dielectric Layer for High Capacitance DRAM
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Solution Overview
Problem
In highly integrated semiconductor memory devices, achieving a cell capacitance of 20 fF/cell or more is challenging due to the difficulty in ensuring adequate capacitance with existing dielectric layers like ZrO2/Al2O3/ZrO2, especially in below 40 nm-process DRAMs, where increasing the capacitor height above 1.7 μm is necessary.
Innovation Solution
A dielectric layer is formed by mixing zirconium, hafnium, and a IV group element, such as silicon or cerium, using an atomic layer deposition method to create a ZrHfMO layer with a nano-lamination structure, which enhances the dielectric constant and leakage current restraint, allowing for adequate cell capacitance without increasing capacitor height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the height of a capacitor is increased to above 1.7 μm to obtain adequate cell capacitance, then the cell capacitance increases to 20 fF/cell or more, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent changes the dielectric material parameters by introducing a multi-layer structure with different dielectric constants. The first dielectric layer has a dielectric constant of 2.1-2.5, the second layer has 3.5-4.5, and the third layer has 5.5-6.5, allowing adequate capacitance without increasing capacitor height
Solution Approach 2:
The patent uses a composite dielectric structure comprising three different dielectric layers with progressively higher dielectric constants. This composite approach achieves the required capacitance density without increasing the physical height of the capacitor, resolving the contradiction between capacitance quantity and device complexity
2Quantity of substance
If a dielectric layer such as ZrO2/Al2O3/ZrO2 is used to maintain capacitance, then the dielectric properties are stable, but it is difficult to ensure 20 fF/cell in below 40 nm-process DRAMs without increasing capacitor height
Solution Approach 1:
The patent systematically changes the dielectric constant parameter across three layers, with the first layer at 2.1-2.5, second at 3.5-4.5, and third at 5.5-6.5. This gradient approach achieves higher capacitance density without increasing capacitor height, solving the problem for below 40 nm-process DRAMs
Solution Approach 2:
Instead of increasing capacitance in the vertical dimension (height), the patent transitions to solving the problem in the material composition dimension by using layers with different dielectric constants, achieving 20 fF/cell without increasing capacitor height
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ZrHfMO layer achieves a dielectric constant of 50 to 60 and an equivalent oxide thickness of about 5 Å, facilitating the attainment of desired cell capacitance while reducing the need for increased capacitor height, thus addressing the capacitance challenge in advanced DRAMs.
Implementation Method 1
forming a dielectric layer in which zirconium, hafnium, and a IV group element are mixed using an atomic layer deposition method
Data Source
AI summary
A semiconductor device includes a dielectric layer in which zirconium, hafnium, and a IV group element are mixed. A method for fabricating a capacitor includes forming a bottom electrode, forming the dielectric layer and forming a top electrode over the dielectric layer.