ZrxAlyOz Dielectric Layer Fabrication for DRAM Capacitors
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Solution Overview
Problem
In highly integrated semiconductor devices like DRAM, capacitors face challenges in achieving sufficient capacitance and low leakage current due to limitations in existing dielectric materials and structures, especially at sub-70 nm level interconnection technology.
Innovation Solution
A method for fabricating a capacitor using a ZrxAlyOz dielectric layer formed by atomic layer deposition, comprising zirconium, aluminum, and oxygen in specific mole fractions, combined with a metal-insulator-metal (MIM) structure, to increase capacitance and reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a MIM capacitor structure with Ru electrode and thin oxide (Tox ≈ 12 Å) is used, then capacitance is increased, but leakage current increases to about 1 fA per cell
Solution Approach 1:
The patent uses a composite dielectric structure consisting of a first dielectric layer (high-K material like HfO2 or Ta2O5) and a second dielectric layer (low-K material like SiO2 or Al2O3). This composite structure combines the high capacitance benefit of high-K materials with the low leakage current advantage of low-K materials, resolving the contradiction between increased capacitance and reduced leakage current.
2Quantity of substance
If capacitor area is increased with 3D electrode structure to increase capacitance, then capacitance is improved, but device complexity increases
Solution Approach 1:
The patent changes the dielectric parameter by introducing a multi-layer dielectric structure with different K values. Instead of increasing area or complexity, the solution modifies the dielectric properties through layer composition and thickness control, achieving higher capacitance with simpler planar electrodes.
3Quantity of substance
If equivalent oxide thickness is decreased to about 12 Å or less, then capacitance is increased, but leakage current increases making implementation difficult in 512M or higher capacity DRAM
Solution Approach 1:
The patent employs a composite dielectric system where a thin high-K dielectric layer provides the necessary capacitance density, while an additional low-K dielectric layer suppresses leakage current. This composite approach enables Tox equivalent thickness of 12 Å or less while maintaining reliability for 512M and higher capacity DRAM devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach achieves the required capacitance of 25 fF per cell and leakage current of 0.5 fA per cell or less, with improved thermal stability and breakdown voltage, enabling mass production of sub-70 nm DRAM capacitors.
Implementation Method 1
forming a ZrxAlyOz dielectric layer on the bottom electrode using an atomic layer deposition (ALD) method
Data Source
AI summary
A method for fabricating a capacitor in a semiconductor device includes: forming a bottom electrode; forming a ZrxAlyOz dielectric layer on the bottom electrode using an atomic layer deposition (ALD) method, wherein the ZrxAlyOz dielectric layer comprises a zirconium (Zr) component, an aluminum (Al) component and an oxygen (O) component mixed in predetermined mole fractions of x, y and z, respectively; and forming a top electrode on the ZrxAlyOz dielectric layer.