ZUC Module Secondary Critical Path Optimization
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Solution Overview
Problem
Conventional hardware implementations of the ZUC module in 5G modems face significant propagation delays, particularly in secondary critical paths, which limit the throughput and performance of 3GPP confidentiality and integrity algorithms, despite optimizations to primary critical paths.
Innovation Solution
The proposed solution involves a method and system that reduce propagation delay by using conjunction and exclusive disjunction operations to process sliding key strings and modular addition units with split adders, along with all-byte substitution boxes and linear transformation units, to optimize the non-linear function part of the ZUC module, thereby improving critical paths R1 to R1 and R1 to T.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional hardware implementation of ZUC module is used, then the primary critical path is optimized, but secondary critical paths cause propagation delays that limit throughput
Solution Approach 1:
The nonlinear function F is segmented into multiple independent computational stages: conjunction operations stage, exclusive disjunction operations stage, and modular addition stage. Each stage processes different portions of the sliding key strings in parallel, breaking the monolithic critical path into shorter segments that can be executed concurrently, thereby reducing overall propagation delay in secondary critical paths
Solution Approach 2:
The hardware implementation uses dynamic clocking strategies where different stages of the nonlinear function are clocked at different rates based on their computational complexity and criticality. The conjunction and exclusive disjunction stages operate in synchronized cycles while the modular addition stage uses pipelined operations, creating a dynamic timing structure that optimizes throughput without sacrificing correctness
2Loss of time
If pipelined implementation is used to optimize primary critical path, then primary path delay is reduced, but secondary critical paths (R1 to R1 and R1 to T) still limit throughput
Solution Approach 1:
The conjunction operations and exclusive disjunction operations are performed in advance during the same clock cycle before the modular addition operation. This preliminary computation of intermediate results (T-string components) allows the final modular addition to proceed independently without waiting for sequential computation, effectively preempting the secondary critical path delay
Solution Approach 2:
Intermediate registers are introduced between the conjunction/exclusive disjunction stages and the modular addition stage to buffer and synchronize data flow. These intermediary storage elements decouple the timing constraints of different computational stages, allowing secondary critical paths to be optimized independently from the primary critical path
Data Source
AI summary
Embodiments of present disclosure relates to and systems to reduce propagation delays in hardware implementation of 3GPP confidentiality or standardized algorithm 128-EEA3 and 3GPP integrity algorithm 128-EIA3 using ZUC module. The reduction of the propagation delays is achieved by improving or optimizing secondary critical paths, which are subsequent to primary critical path, related to the 3GPP confidentiality or standardized algorithm 128-EEA3 and the 3GPP integrity algorithm 128-EIA3. Non-conventional modifications in the hardware implementation are proposed for the improvement or optimization.