3D Multilayer Semiconductor Design for Enhanced IC Performance
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Summary
Problems
Existing 3D integrated circuits face challenges with wire performance degradation due to scaling, which affects IC performance, functionality, and power consumption, and current 3D memory structures using poly-silicon channels suffer from higher cell-to-cell performance variations and lower drive than monocrystalline channels.
Innovation solutions
The development of multilayer semiconductor devices with monocrystalline channels, utilizing epitaxial growth of SiGe and single crystal silicon layers, and oxide-to-oxide bonding to form self-aligned transistors, allowing for efficient connection and control of memory cells across multiple levels with shared lithography steps.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If poly-silicon channels are used in 3D memory structures, then manufacturing is simplified, but cell-to-cell performance variations increase and drive capability decreases
Why choose this principle:
The patent changes the material parameter from poly-silicon to monocrystalline silicon for the channel region. This fundamental material parameter change resolves the contradiction by providing both manufacturing feasibility through epitaxial growth and superior electrical performance with reduced cell-to-cell variation and enhanced drive capability compared to poly-silicon channels
Principle concept:
If component sizes are scaled down, then transistor performance and density improve, but wire performance degrades
Why choose this principle:
The patent transitions from 2D planar scaling to 3D vertical stacking architecture. By stacking multiple transistor layers vertically, the invention achieves higher transistor density without further lateral scaling, thereby avoiding the wire performance degradation that occurs with continued miniaturization of interconnect dimensions
Application Domain
Data Source
AI summary:
The development of multilayer semiconductor devices with monocrystalline channels, utilizing epitaxial growth of SiGe and single crystal silicon layers, and oxide-to-oxide bonding to form self-aligned transistors, allowing for efficient connection and control of memory cells across multiple levels with shared lithography steps.
Abstract
Methods of making a 3D multilayer semiconductor device, including: providing a first substrate including a first level, the first level including a first single crystal silicon layer (SCSL); providing a second substrate including a second level, the second level including a second SCSL; performing an epitaxial growth of a SiGe layer on top of the second SCSL; performing an epitaxial growth of a third SCSL on top of the SiGe layer, the third SCSL has an average thickness of less than 2,000 nm; forming second transistors each including a single crystal channel, where forming the second transistors includes growth of a second SiGe layer on top of the third SCSL; forming many metal layers interconnecting the second transistors; and then performing a bonding of the second level onto the first level, where performing the bonding includes making oxide-to-oxide bond zones; and performing removal of a majority of the second SCSL.