Backside Via Design for Reliable Semiconductor Connections
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Summary
Problems
The challenge of forming reliable semiconductor devices at smaller sizes is exacerbated by the complexity of fabrication processes as feature sizes continue to decrease, making it difficult to achieve reliable connections and maintain device integrity.
Innovation solutions
A method is introduced to form epitaxial source/drain structures and backside vias in semiconductor devices, utilizing advanced etching and deposition techniques to create precise connections between semiconductor layers and vias, enabling reliable electrical connections despite reduced feature sizes.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process difficulty and device reliability worsen
Why choose this principle:
The patent introduces backside vias that extend through the substrate from the front surface to the back surface, adding a vertical dimension to the interconnection architecture. This allows electrical connections to be established through the substrate thickness, enabling continued scaling of planar features while maintaining connectivity reliability through the third dimension.
Principle concept:
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process difficulty and device reliability worsen
Why choose this principle:
The patent divides the interconnection path into multiple segments: front-side contacts, epitaxial source/drain structures, backside vias extending through the substrate, and back-side contacts. This segmentation allows each component to be optimized independently for its specific function while maintaining overall system reliability despite reduced feature sizes.
Application Domain
Data Source
AI summary:
A method is introduced to form epitaxial source/drain structures and backside vias in semiconductor devices, utilizing advanced etching and deposition techniques to create precise connections between semiconductor layers and vias, enabling reliable electrical connections despite reduced feature sizes.
Abstract
A method includes forming a semiconductor strip and semiconductor layers vertically stacked over a front side of the semiconductor strip; forming a gate structure over the semiconductor layers; etching the semiconductor strip to form recesses in the semiconductor strip and on opposite sides of the gate structure; forming epitaxial layers in the recesses, respectively; forming isolation layers over the epitaxial layers, respectively; forming epitaxial source/drain structures over the isolation layers, respectively; performing an etching process from a backside of the semiconductor strip to form a via opening extending through the semiconductor strip, one of the epitaxial layer, and one of the isolation layer, wherein one of the epitaxial source/drain structures is exposed through the via opening; and forming a backside via in the via opening.