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Home»TRIZ Case»Carrier-Based Warpage Control for 3DIC Stacking

Carrier-Based Warpage Control for 3DIC Stacking

May 22, 20263 Mins Read
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Carrier-Based Warpage Control for 3DIC Stacking

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Summary

Problems

Conventional Package-on-Package (PoP) device fabrication processes fail to adequately prevent warping, especially when stacking relatively thin integrated circuit dies, due to material coefficient of thermal expansion mismatches.

Innovation solutions

A method involving the use of a carrier with a low coefficient of thermal expansion, such as glass or silicon, to temporarily mount substrates and dies, followed by pressure annealing, underfill material application, and molding to inhibit warping, while allowing for horizontal offset stacking and subsequent removal of the carrier.

TRIZ Analysis

Specific contradictions:

warping control
vs
process complexity

General conflict description:

Manufacturing precision
vs
Device complexity
TRIZ inspiration library
24 Intermediary (Mediator)
Try to solve problems with it

Principle concept:

If conventional fabrication processes are used to stack packages, then the manufacturing process is simple, but the packages warp due to thermal expansion mismatches

Why choose this principle:

A carrier substrate is introduced as an intermediary component during the stacking process. This carrier has a low coefficient of thermal expansion that acts as a stable reference plane, preventing warping of the stacked packages. The carrier is temporarily used during assembly and then removed, serving as a mediator that enables precise stacking without introducing permanent structural changes to the final product.

TRIZ inspiration library
35 Parameter changes
Try to solve problems with it

Principle concept:

If conventional fabrication processes are used to stack packages, then the manufacturing process is simple, but the packages warp due to thermal expansion mismatches

Why choose this principle:

The process utilizes controlled temperature changes during pressure annealing to reduce warpage. By heating the stacked packages on the carrier to elevated temperatures and then cooling them under pressure, the thermal expansion differences between materials are minimized, allowing the packages to conform to the carrier's flat surface and reducing warpage.

Application Domain

3dic stacking warpage control thermal expansion

Data Source

Patent US20190267255A1 Carrier warpage control for three dimensional integrated circuit (3DIC) stacking
Publication Date: 29 Aug 2019 TRIZ 电器元件
FIG 01
US20190267255A1-D00001
FIG 02
US20190267255A1-D00002
FIG 03
US20190267255A1-D00003
Login to view Image

AI summary:

A method involving the use of a carrier with a low coefficient of thermal expansion, such as glass or silicon, to temporarily mount substrates and dies, followed by pressure annealing, underfill material application, and molding to inhibit warping, while allowing for horizontal offset stacking and subsequent removal of the carrier.

Abstract

An embodiment method of forming a package-on-package (PoP) device includes temporarily mounting a substrate on a carrier, stacking a first die on the substrate, at least one of the die and the substrate having a coefficient of thermal expansion mismatch relative to the carrier, and stacking a second die on the first die. The substrate may be formed from one of an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, and a laminate substrate.

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    3dic stacking thermal expansion warpage control
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    Table of Contents
    • Carrier-Based Warpage Control for 3DIC Stacking
      • Summary
      • TRIZ Analysis
      • Data Source
      • Accelerate from idea to impact
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