Efficient Heat Dissipation in Chip Packaging with Vertical Conduction
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Summary
Problems
Existing chip packaging methods face limitations in heat dissipation capability due to limited exposure and flexibility of heat conduction elements, which are often far away from the bottom plate and have restricted layout, leading to inefficient heat dissipation.
Innovation solutions
The method involves forming multiple vertical heat conduction elements on a wafer or chip units, cutting them into individual units, and disposing them on a base material with through-holes, allowing the elements to directly connect or pass through, enhancing heat transfer paths to the base material.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If wirings are used for heat conduction in prior art, then electromagnetic protection is provided, but heat dissipation capability is limited due to wirings being far from the bottom plate and having small exposed areas
Why choose this principle:
The patent transitions from planar heat conduction (wirings on the surface) to vertical heat conduction by introducing heat conduction posts that extend downward through the package material to the bottom plate, utilizing the vertical dimension to reduce heat transfer distance and improve dissipation efficiency
Principle concept:
If wirings are used for heat conduction in prior art, then electromagnetic protection is provided, but heat dissipation capability is limited due to wirings being far from the bottom plate and having small exposed areas
Why choose this principle:
The patent introduces heat conduction posts as intermediary elements between the chip unit and the bottom plate, providing a dedicated thermal pathway that mediates heat transfer and overcomes the limitation of using wirings that are both too far from the bottom plate and too small in exposed area
Application Domain
Data Source
AI summary:
The method involves forming multiple vertical heat conduction elements on a wafer or chip units, cutting them into individual units, and disposing them on a base material with through-holes, allowing the elements to directly connect or pass through, enhancing heat transfer paths to the base material.
Abstract
A chip packaging method includes: providing a wafer, on which multiple bumps are formed; cutting the wafer into multiple chip units, wherein multiple vertical heat conduction elements are formed on the wafer or the chip units; disposing the chip units on a base material; and providing a package material to encapsulate lateral sides and a bottom surface of each of the chip units, to form a chip package unit, wherein the bottom surface of the chip unit faces the base material; wherein, in the chip package unit, the bumps on the chip units abut against the base material, and wherein the vertical heat conduction elements directly connect to the base material, or the base material includes multiple through-holes and the vertical heat conduction elements pass through the multiple through-holes in the base material.