Compact Semiconductor Packaging with Embedded Die Design
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Summary
Problems
Conventional semiconductor packaging technologies face challenges in creating lightweight, thin, short, and small semiconductor packages that meet the growing demands of electronic devices such as smartphones and smart pads, as they struggle to efficiently integrate semiconductor dies between substrates while ensuring electrical connectivity and thermal management.
Innovation solutions
A semiconductor device design that embeds a semiconductor die between an extended substrate and a bottom substrate, using conductive bumps and an adhering member for electrical and thermal connectivity, with the option of encapsulating the die and bumps in a mold member, allowing for various coupling methods like ball-to-ball, ball-to-post, post-to-ball, and post-to-post configurations.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If conventional semiconductor packaging is used, then electrical connectivity and thermal management are achieved, but the package size and weight are too large for modern electronic devices
Why choose this principle:
The semiconductor die is embedded within a cavity formed in the first substrate, creating a nested structure where the die is housed inside the substrate volume rather than being mounted on the surface. This nesting approach reduces the overall package footprint while maintaining all necessary electrical and thermal connection pathways.
Principle concept:
If conventional semiconductor packaging is used, then electrical connectivity and thermal management are achieved, but the package size and weight are too large for modern electronic devices
Why choose this principle:
The invention transitions from traditional surface-mount packaging to a three-dimensional embedded structure. By creating cavities within the substrate and embedding dies within these cavities, the design utilizes vertical space more efficiently, reducing the horizontal footprint and enabling smaller package dimensions.
Application Domain
Data Source
AI summary:
A semiconductor device design that embeds a semiconductor die between an extended substrate and a bottom substrate, using conductive bumps and an adhering member for electrical and thermal connectivity, with the option of encapsulating the die and bumps in a mold member, allowing for various coupling methods like ball-to-ball, ball-to-post, post-to-ball, and post-to-post configurations.
Abstract
A method of manufacturing a semiconductor device having a semiconductor die within an extended substrate and a bottom substrate may include bonding a bottom surface of a semiconductor die to a top surface of a bottom substrate, forming an adhering member to a top surface of the semiconductor die, bonding an extended substrate to the semiconductor die and to the top surface of the bottom substrate utilizing the adhering member and a conductive bump on a bottom surface of the extended substrate and a conductive bump on the bottom substrate. The semiconductor die and the conductive bumps may be encapsulated utilizing a mold member. The conductive bump on the bottom surface of the extended substrate may be electrically connected to a terminal on the top surface of the extended substrate. The adhering member may include a laminate film, a non-conductive film adhesive, or a thermal hardening liquid adhesive.