Optimized Display Driver IC Design for Reduced Chip Size
Here’s PatSnap Eureka !
Summary
Problems
Conventional LCD source driver ICs have a large chip size due to the size of high voltage transistors, which is exacerbated by the thickness of the gate oxide layer, leading to increased power consumption and reduced portability in high-definition displays.
Innovation solutions
A display driver semiconductor device manufacturing method that involves forming trench isolating regions, high and low voltage well regions, and specific gate insulating layers using chemical vapor deposition (CVD) and thermal oxide techniques to reduce the size of high voltage transistors, thereby minimizing the overall chip size.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If the thickness of the gate oxide layer is increased to satisfy breakdown voltage requirements for high voltage transistors, then the electrical performance is improved, but the transistor size and overall chip size increase
Why choose this principle:
The patent applies different gate oxide thicknesses to different transistor types on the same chip. High voltage transistors receive thicker gate oxide (e.g., 50-100nm) to satisfy breakdown voltage requirements, while low voltage transistors receive thinner gate oxide (e.g., 10-30nm) to minimize area. This local differentiation resolves the contradiction by optimizing each transistor type for its specific voltage requirements rather than using a uniform thickness across all transistors.
Principle concept:
If the thickness of the gate oxide layer is increased to satisfy breakdown voltage requirements for high voltage transistors, then the electrical performance is improved, but the transistor size and overall chip size increase
Why choose this principle:
The manufacturing process segments the gate oxide formation into multiple distinct oxidation steps. First, a thin gate oxide is formed across the entire substrate, then additional thick gate oxide is selectively grown only in high voltage transistor regions through controlled oxidation processes. This segmentation allows the chip to simultaneously have both thin oxide regions (for small low voltage transistors) and thick oxide regions (for high voltage transistors requiring higher breakdown voltage).
Application Domain
Data Source
AI summary:
A display driver semiconductor device manufacturing method that involves forming trench isolating regions, high and low voltage well regions, and specific gate insulating layers using chemical vapor deposition (CVD) and thermal oxide techniques to reduce the size of high voltage transistors, thereby minimizing the overall chip size.
Abstract
A display driver semiconductor device includes a high voltage well region being formed on a substrate, a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device is formed on the high voltage well region and includes a first gate insulating layer. The second semiconductor device is formed adjacent to the first semiconductor device and includes a second gate insulating layer. The third semiconductor device is formed adjacent to the second semiconductor device and includes a third gate insulating layer. The first insulating layer may be formed using a chemical vapor deposition (CVD) process and the second insulating layer is formed using a thermal oxide process.