Disturb-Resistant Non-Volatile Memory Design for High Density
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Summary
Problems
Current semiconductor devices, particularly non-volatile memory devices, face challenges such as short channel effects, sub-threshold slope non-scaling, and increased power dissipation as they approach sizes less than 100 nm, and existing alternative memory devices like Fe-RAM, MRAM, and PCRAM have limitations in CMOS compatibility, size, and reliability.
Innovation solutions
A method and structure for forming a disturb-resistant non-volatile memory device using an amorphous silicon switching material, integrated with CMOS-compatible fabrication techniques, which includes forming a substrate with dielectric and wiring materials, patterning and etching to create orthogonal wiring structures, and using a dielectric material to isolate switching regions and prevent parasitic leakage.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If transistor size is scaled down to less than 100 nm to increase memory density, then memory capacity is improved, but short channel effects and power dissipation increase
Why choose this principle:
The patent replaces the conventional FET-based mechanical/electrical switching system with a resistive switching device that uses material property changes (resistive state transitions) to achieve switching functionality. This substitution eliminates short channel effects that plague scaled FETs while maintaining high-density storage capability.
Principle concept:
If transistor size is scaled down to less than 100 nm to increase memory density, then memory capacity is improved, but short channel effects and power dissipation increase
Why choose this principle:
The invention changes the fundamental switching parameter from charge-based (in FETs) to resistance-based (in resistive switching devices). By utilizing materials that can transition between high and low resistance states, the device achieves reliable switching at nanoscale dimensions without suffering from short channel effects.
Application Domain
Data Source
AI summary:
A method and structure for forming a disturb-resistant non-volatile memory device using an amorphous silicon switching material, integrated with CMOS-compatible fabrication techniques, which includes forming a substrate with dielectric and wiring materials, patterning and etching to create orthogonal wiring structures, and using a dielectric material to isolate switching regions and prevent parasitic leakage.
Abstract
A method of forming a disturb-resistant non volatile memory device. The method includes providing a semiconductor substrate having a surface region and forming a first dielectric material overlying the surface region. A first wiring material overlies the first dielectric material, a doped polysilicon material overlies the first wiring material, and an amorphous silicon switching material overlies the said polysilicon material. The switching material is subjected to a first patterning and etching process to separating a first strip of switching material from a second strip of switching spatially oriented in a first direction. The first strip of switching material, the second strip of switching material, the contact material, and the first wiring material are subjected to a second patterning and etching process to form at least a first switching element from the first strip of switching material and at least a second switching element from the second strip of switching material, and a first wiring structure comprising at least the first wiring material and the contact material. The first wiring structure being is in a second direction at an angle to the first direction.