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Home»TRIZ Case»Dynamic Cooling for Semiconductor Wafer Alignment

Dynamic Cooling for Semiconductor Wafer Alignment

May 22, 20263 Mins Read
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Dynamic Cooling for Semiconductor Wafer Alignment

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Summary

Problems

Existing semiconductor wafer cooling techniques use a fixed cooling time, which can lead to inconsistent wafer heating across exposure stages, causing photomask misalignment and degraded overlay performance due to thermal expansion and contraction.

Innovation solutions

A learning cooling device that determines a cooling time for a semiconductor wafer based on the pattern mask area, ensuring synchronization between wafer exposure time and cooling time to reduce photomask misalignment.

TRIZ Analysis

Specific contradictions:

cooling process speed
vs
photomask alignment accuracy

General conflict description:

Productivity
vs
Manufacturing precision
TRIZ inspiration library
15 Dynamics
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Principle concept:

If a fixed cooling time is used for all wafers, then the cooling process is simple and fast, but the wafer temperature becomes inconsistent across different exposure stages, causing photomask misalignment

Why choose this principle:

The cooling time is changed from a fixed static value to a dynamic value that varies according to the pattern mask area. The cooling device adjusts the cooling time based on the specific exposure conditions of each wafer, making the cooling process adaptive rather than rigid. This resolves the contradiction by allowing the system to be both efficient (fast cooling) and precise (aligned photomasks) simultaneously.

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35 Parameter changes
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Principle concept:

If a fixed cooling time is used for all wafers, then the cooling process is simple and fast, but the wafer temperature becomes inconsistent across different exposure stages, causing photomask misalignment

Why choose this principle:

The cooling time parameter is changed based on the pattern mask area parameter. By establishing a relationship between these two parameters, the system optimizes the cooling process for different exposure conditions. Larger pattern mask areas receive different cooling times compared to smaller areas, ensuring consistent wafer temperature and photomask alignment across all exposure stages.

Application Domain

semiconductor cooling photomask alignment dynamic process control

Data Source

Patent US12282318B2 Semiconductor wafer cooling
Publication Date: 22 Apr 2025 TRIZ 电器元件
FIG 01
US12282318-D00001
FIG 02
US12282318-D00002
FIG 03
US12282318-D00003
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AI summary:

A learning cooling device that determines a cooling time for a semiconductor wafer based on the pattern mask area, ensuring synchronization between wafer exposure time and cooling time to reduce photomask misalignment.

Abstract

A cooling controller receives, from one or more sensors, wafer information associated with a wafer. The cooling controller determines a pattern mask area for the wafer based on the wafer information. The cooling controller determines a cooling time for the wafer based on the pattern mask area. The cooling controller causes a cooling plate to cool the wafer for a time duration equal to the cooling time. Determining the cooling time for a wafer based on a pattern mask area provides stable and consistent wafer temperatures for wafers having different mask and layout properties, which reduces mask overlay variation and increases wafer yield.

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    dynamic process control photomask alignment semiconductor cooling
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    Table of Contents
    • Dynamic Cooling for Semiconductor Wafer Alignment
      • Summary
      • TRIZ Analysis
      • Data Source
      • Accelerate from idea to impact
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