Enhanced High-Frequency LDMOS Design with Reduced Capacitance
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Summary
Problems
Conventional LDMOS devices with field plate structures face challenges in high-frequency applications due to increased parasitic feedback capacitance, which degrades high-frequency performance and results in power loss, necessitating a reduction in gate-to-drain capacitance without compromising breakdown voltage and on-resistance.
Innovation solutions
The implementation of a gate structure divided into multiple segments with adjustable spacing, using standard CMOS fabrication technology, to reduce parasitic capacitance by minimizing the overlap area between the gate and drain/drift regions, thereby enhancing high-frequency performance.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If a field plate structure is used to increase breakdown voltage and reduce on-resistance, then power performance is improved, but parasitic feedback capacitance (Miller capacitance) increases, degrading high-frequency performance
Why choose this principle:
The gate structure is divided into multiple gate segments separated by insulating layers, which reduces the continuous overlap area between gate and drain, thereby reducing parasitic feedback capacitance while maintaining the field plate's voltage enhancement function
Principle concept:
If a field plate structure is used to increase breakdown voltage and reduce on-resistance, then power performance is improved, but parasitic feedback capacitance (Miller capacitance) increases, degrading high-frequency performance
Why choose this principle:
The gate structure uses different configurations in different regions: a first gate segment over the body region and second gate segments over the drift region, allowing localized optimization of electric field distribution and capacitance reduction
Application Domain
Data Source
AI summary:
The implementation of a gate structure divided into multiple segments with adjustable spacing, using standard CMOS fabrication technology, to reduce parasitic capacitance by minimizing the overlap area between the gate and drain/drift regions, thereby enhancing high-frequency performance.
Abstract
A high-frequency LDMOS device includes a semiconductor substrate of a first conductivity type, a doped drift region of a second conductivity type formed on the substrate, and a body region of the first conductivity type formed in the doped drift region. Source and drain regions of the second conductivity type are formed proximate an upper surface of the body region and doped drift region, respectively, and spaced laterally from one another. A first insulating layer is formed on the body and doped drift regions. A gate structure including multiple gate segments is formed on the first insulating layer. Each of the gate segments is spaced laterally from one another by a second insulating layer disposed between adjacent gate segments. A spacing between adjacent gate segments is controlled as a function of a thickness of the second insulating layer, a thickness of the first and second insulating layers being independently controlled.