Reducing Defects in Miniaturized Semiconductor Memory Devices
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Summary
Problems
Miniaturization of semiconductor memory devices often results in defects in the semiconductor layer, leading to electrical deviations in device characteristics and reduced manufacturing yield, necessitating a structure that minimizes defects to improve reliability.
Innovation solutions
The semiconductor memory device incorporates a conductive layer, first and second electrode layers, semiconductor channel bodies, and insulating layers with recessed portions, where the second semiconductor channel body has a recessed portion on its lateral surface and the second electrode layer has a recessed portion facing the channel body, along with a specific manufacturing process involving thermal oxidation and deposition techniques to enhance channel body strength and reduce crystal defects.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If the structure is miniaturized to increase memory density, then the memory device capacity is improved, but defects are likely to be generated in the semiconductor layer resulting in reduced manufacturing yield
Why choose this principle:
The patent applies preliminary action by forming a stress relief structure (recessed portion with different stress characteristics) in advance within the semiconductor layer before subsequent processing steps. This pre-formed structure prevents stress accumulation and crystal defect generation during miniaturization, thereby maintaining manufacturing yield while enabling higher memory density.
Principle concept:
If the structure is miniaturized to increase memory density, then the memory device capacity is improved, but electrical deviations are induced in device characteristics such as threshold voltage
Why choose this principle:
The stress relief structure is formed in advance to prevent stress-induced crystal defects that cause electrical deviations. By addressing the stress issue before device fabrication is complete, the patent ensures consistent electrical characteristics including threshold voltage across miniaturized memory cells.
Application Domain
Data Source
AI summary:
The semiconductor memory device incorporates a conductive layer, first and second electrode layers, semiconductor channel bodies, and insulating layers with recessed portions, where the second semiconductor channel body has a recessed portion on its lateral surface and the second electrode layer has a recessed portion facing the channel body, along with a specific manufacturing process involving thermal oxidation and deposition techniques to enhance channel body strength and reduce crystal defects.
Abstract
A semiconductor memory device includes a conductive layer; a first electrode layer provided above the conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a first semiconductor channel body extending through the first electrode layer in a first direction from the conductive layer to the first electrode layer; a second semiconductor channel body provided between the conductive layer and the first semiconductor channel body, the second semiconductor channel body extending through the second electrode layer; and an insulating layer provided between the second semiconductor channel body and the second electrode layer. The second semiconductor channel body includes a first recessed portion in a lateral surface facing the second electrode layer, and the second electrode layer includes a second recessed portion in a surface facing the second semiconductor channel body.