Improved Power Delivery for Multi-Chip Packages with PVRs
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Summary
Problems
The complexity of manufacturing multi-chip packages leads to issues such as poor structural configuration and delamination, resulting in high yield loss and increased costs, due to the large number of manufacturing steps and small scale of these packages.
Innovation solutions
The implementation of multi-chip package structures that include Integrated Passive Device (IPD) capacitors and in-Package Voltage Regulators (PVR) with on-die inductors to improve power delivery and electrical performance, such as embedding IPD capacitors beneath the substrate for noise decoupling and using PVRs with buck converters to power dies, which reduces losses and enhances performance.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If multi-chip packages are manufactured with increased integration and miniaturization, then functionality and circuitry density are improved, but manufacturing complexity increases leading to poor structural configuration and delamination
Why choose this principle:
The patent divides the multi-chip package into modular units with standardized interconnection interfaces. Each chip module can be independently manufactured and tested before final assembly, reducing the complexity of manufacturing the entire package as a single complex structure.
Principle concept:
If multi-chip packages are manufactured with increased integration and miniaturization, then functionality and circuitry density are improved, but manufacturing complexity increases leading to poor structural configuration and delamination
Why choose this principle:
The patent implements a hierarchical packaging structure where chips are mounted on substrates, which are then assembled into multi-chip modules, which in turn are integrated into the final package. This nested arrangement allows systematic management of complexity at each level.
Application Domain
Data Source
AI summary:
The implementation of multi-chip package structures that include Integrated Passive Device (IPD) capacitors and in-Package Voltage Regulators (PVR) with on-die inductors to improve power delivery and electrical performance, such as embedding IPD capacitors beneath the substrate for noise decoupling and using PVRs with buck converters to power dies, which reduces losses and enhances performance.
Abstract
A semiconductor structure includes a first substrate. A first die and a second die are disposed over the first substrate and are adjacent to one another. A plurality of first conductive bumps are disposed between the first substrate and the first die and between the first substrate and the second die. A second substrate is disposed below the first substrate. A plurality of second conductive bumps is disposed between the first substrate and the second substrate. An in-package voltage regulator (PVR) chip is disposed over the second substrate. A molding material is disposed over the first substrate and surrounds the first die, the second die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip.