Power Factor Correction Circuit for Safer and Efficient Capacitor Design
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Summary
Problems
Traditional Totem-Pole power factor correction circuits experience significant losses in the rectifier bridge and have large filter circuits, which can lead to excessive voltage on the bus capacitor during no-load or light-load conditions, potentially causing capacitor explosion.
Innovation solutions
A power factor correction circuit design that includes bridge arms with switches and inductors connected in parallel, with capacitors and switching units configured to maintain equal capacitance values or turn off under no-load/light-load conditions, preventing voltage peaks and reducing filter circuit volume.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If film capacitor is used to reduce filter circuit volume, then the volume of the filter circuit is reduced, but the bus capacitor voltage becomes much higher than normal under no-load or light-load conditions, which may result in capacitor explosion
Why choose this principle:
The patent applies dynamic control by turning off switching units under no-load or light-load conditions. This dynamic operation mode prevents the bus capacitor voltage from rising to dangerous levels while maintaining the compact filter circuit design using film capacitors.
Principle concept:
If film capacitor is used to reduce filter circuit volume, then the volume of the filter circuit is reduced, but the bus capacitor voltage becomes much higher than normal under no-load or light-load conditions, which may result in capacitor explosion
Why choose this principle:
The patent changes the operational parameters of the switching units based on load conditions. By adjusting the switching state according to load levels, the system maintains safe bus capacitor voltage while achieving reduced filter circuit volume with film capacitors.
Application Domain
Data Source
AI summary:
A power factor correction circuit design that includes bridge arms with switches and inductors connected in parallel, with capacitors and switching units configured to maintain equal capacitance values or turn off under no-load/light-load conditions, preventing voltage peaks and reducing filter circuit volume.
Abstract
The present invention discloses a power factor correction circuit. The power factor correction circuit includes: a first bridge arm having a first switch and a second switch; a second bridge arm having a third switch and a fourth switch; a first inductor and a second inductor; a first capacitor and/or a second capacitor connected with a common point between the second inductor and the first inductor; and a third capacitor and/or a fourth capacitor, the third capacitor connected in parallel to the third switch based on an arrangement of the second capacitor and having a capacitance value same as that of the second capacitor, the fourth capacitor connected in parallel to the fourth switch based on an arrangement of the first capacitor and having a capacitance value same as that of the first capacitor.