Precision Comparator Design with Observable DAC References
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Summary
Problems
Existing comparator circuits face issues with unobservable VREFH, gain errors due to capacitor mismatch, slower DAC transitions, lower input impedance, and periodic blind zones due to dedicated auto-zero phases, which affect precision and speed in high-bandwidth applications.
Innovation solutions
The proposed solution involves a comparator circuit with a matching capacitor and sampling capacitor configuration, using switching devices to manage phases for auto-zero and DAC operations, allowing for incremental offset voltage nullification and observable DAC references, eliminating blind zones and reducing capacitor mismatch errors.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If a dedicated auto-zero phase is used to nullify offset voltage, then offset voltage is contained, but periodic blind zones are created affecting productivity
Why choose this principle:
The patent combines the auto-zero function with the normal comparison operation by using the same capacitor network for both purposes. The switching mechanism allows the capacitors to serve dual functions: storing offset voltage during comparison phases and performing auto-zero during dedicated phases, eliminating the need for separate blind zones.
Principle concept:
If a dedicated auto-zero phase is used to nullify offset voltage, then offset voltage is contained, but periodic blind zones are created affecting productivity
Why choose this principle:
The patent employs dynamic switching of capacitor connections through control signals that change the circuit topology in real-time. The capacitors are dynamically reconfigured between comparison mode and auto-zero mode, allowing continuous operation without periodic blind zones while maintaining offset voltage containment.
Application Domain
Data Source
AI summary:
The proposed solution involves a comparator circuit with a matching capacitor and sampling capacitor configuration, using switching devices to manage phases for auto-zero and DAC operations, allowing for incremental offset voltage nullification and observable DAC references, eliminating blind zones and reducing capacitor mismatch errors.
Abstract
A comparator circuit includes a matching capacitor in series with a first switching device and a second switching device. The first and second switching devices are in parallel between the matching capacitor and a reference voltage. The comparator circuit further includes a sampling capacitor in series with a third switching device and a fourth switching device. The third switching device is in series between the sampling capacitor and a DAC, and the fourth switching device is in series between the sampling capacitor an input voltage. The comparator circuit further includes a comparator having an inverting input terminal and a non-inverting input terminal. The inverting input terminal is capacitively coupled to the matching capacitor and the non-inverting input terminal is capacitively coupled to the sampling capacitor. The comparator circuit further includes a fifth switching device and a sixth switching device in series between the matching capacitor and the sampling capacitor.