Reducing Wafer Bow in Semiconductor Multilayer Structures
Here’s PatSnap Eureka !
Summary
Problems
Existing methods for producing semiconductor-on-insulator (SOI) wafers with high resistivity substrates face challenges such as high costs, time-consuming processes, and non-uniform thickness, particularly for layers thinner than a few microns. Additionally, these substrates are prone to the formation of high conductivity charge inversion or accumulation layers at the buried oxide/handle interface, leading to parasitic power losses and device nonlinearity when used in RF applications.
Innovation solutions
A multilayer structure is developed comprising a high resistivity single crystal semiconductor handle substrate, a textured semiconductor oxide, nitride, or oxynitride layer, a polycrystalline silicon charge trapping layer, a dielectric layer, and a single crystal semiconductor device layer. The charge trapping layer is formed near the oxide interface to trap charges and maintain the high resistivity of the substrate, even in the near surface region.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If a polycrystalline silicon layer is formed on a silicon substrate, then the film can serve as a charge trapping layer or active device layer, but the film stress causes wafer bowing that complicates subsequent processing
Why choose this principle:
A textured intermediate layer is introduced between the silicon substrate and the polycrystalline silicon film. This intermediate layer acts as a stress buffer that absorbs and distributes the tensile stress generated by the polycrystalline silicon film, preventing wafer bowing while maintaining the functional properties of the charge trapping layer.
Principle concept:
If a polycrystalline silicon layer is formed on a silicon substrate, then the film can serve as a charge trapping layer or active device layer, but the film stress causes wafer bowing that complicates subsequent processing
Why choose this principle:
The intermediate layer is designed with specific physical and chemical parameters including a thickness of 50-200 nm, specific surface area of 0.5-2.0 m²/g, and porosity of 30-70%. These parameter optimizations enable the layer to effectively manage film stress while maintaining processability.
Application Domain
Data Source
AI summary:
A multilayer structure is developed comprising a high resistivity single crystal semiconductor handle substrate, a textured semiconductor oxide, nitride, or oxynitride layer, a polycrystalline silicon charge trapping layer, a dielectric layer, and a single crystal semiconductor device layer. The charge trapping layer is formed near the oxide interface to trap charges and maintain the high resistivity of the substrate, even in the near surface region.
Abstract
A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, a textured oxide, nitride, or oxynitride layer, a polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer. The multilayer structure is prepared in a manner that reduces wafer bow.