Self-Aligned Source Design for Split-Gate Memory Cells
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Summary
Problems
Existing split gate non-volatile flash memory cells face challenges in scaling down memory cell size due to misalignment issues between control gate lines and source lines, leading to leakage and difficulty in reducing the critical CG-to-SL spacing, which affects the size and efficiency of the memory cell array.
Innovation solutions
The formation of memory cells with conductive floating gates and control gates, aligned with insulation spacers, and the use of silicon carbon in trenches, allowing for a self-aligned source region implant that minimizes the CG-to-SL spacing and eliminates the need for optical proximity correction, enabling better control over source line dimensions and reduced memory cell size.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If conventional ion implantation between floating gates is used to form source regions, then source regions can be formed, but misalignment between control gate lines and source lines occurs leading to leakage and inability to reduce CG-to-SL spacing
Why choose this principle:
The method performs preliminary actions by first forming control gates, then forming spacers along their sidewalls, and finally using these spacers as masks to define source line positions. This preliminary establishment of reference structures ensures that subsequent source region formation is automatically aligned with control gates, eliminating misalignment issues and preventing leakage between adjacent floating gates.
Principle concept:
If conventional ion implantation between floating gates is used to form source regions, then source regions can be formed, but misalignment between control gate lines and source lines occurs leading to leakage and inability to reduce CG-to-SL spacing
Why choose this principle:
The control gate structures and their associated spacers serve as self-aligning masks for defining source line positions. The spacers automatically form at precise locations relative to the control gates, and the subsequent etching and implantation processes use these spacers as self-generated masks, eliminating the need for separate alignment operations and ensuring precise CG-to-SL spacing control.
Application Domain
Data Source
AI summary:
The formation of memory cells with conductive floating gates and control gates, aligned with insulation spacers, and the use of silicon carbon in trenches, allowing for a self-aligned source region implant that minimizes the CG-to-SL spacing and eliminates the need for optical proximity correction, enabling better control over source line dimensions and reduced memory cell size.
Abstract
A memory device having a pair of conductive floating gates with inner sidewalls facing each other, and disposed over and insulated from a substrate of first conductivity type. A pair of spaced apart conductive control gates each disposed over and insulated from one of the floating gates, and each including inner sidewalls facing each other. A pair of first spacers of insulation material extending along control gate inner sidewalls and over the floating gates. The floating gate inner sidewalls are aligned with side surfaces of the first spacers. A pair of second spacers of insulation material each extend along one of the first spacers and along one of the floating gate inner sidewalls. A trench formed into the substrate having sidewalls aligned with side surfaces of the second spacers. Silicon carbon disposed in the trench. Material implanted into the silicon carbon forming a first region having a second conductivity type.