SiC JFET Gate Design for Reduced Junction Current
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Summary
Problems
In semiconductor devices, particularly SiC-based JFETs, challenges include precise control of gate region areas, increased junction current due to heavily doped PN junctions, high-energy ion implantation requirements for edge termination, and elevated gate resistance due to electrode wiring constraints.
Innovation solutions
A multi-epitaxial method involving repeated processes of epitaxial growth, ion implantation, and activation annealing is employed to form gate regions with precise gate-to-gate spacing, reducing junction current and gate resistance by using a multi-layered epitaxial structure and optimized ion implantation energies.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If ion implantation is performed to form gate regions in SiC-based JFETs, then the gate regions can be formed, but high-energy ion implantation is required for edge termination which increases process complexity and difficulty
Why choose this principle:
The gate region formation process is segmented into multiple ion implantation steps with different energies. First, high-energy ion implantation (1.5-2.0 MeV) is used to form the deep termination region, followed by lower-energy ion implantation (0.1-0.5 MeV) to form the main gate region. This segmentation allows each step to be optimized for its specific purpose, reducing overall process difficulty while maintaining device reliability.
Principle concept:
If ion implantation is performed to form gate regions in SiC-based JFETs, then the gate regions can be formed, but high-energy ion implantation is required for edge termination which increases process complexity and difficulty
Why choose this principle:
The termination region is formed first through high-energy ion implantation before forming the main gate region. This preliminary action creates a foundation that prevents premature breakdown and allows subsequent lower-energy implantation to form the gate region without requiring equally high energies, thereby simplifying the overall process.
Application Domain
Data Source
AI summary:
A multi-epitaxial method involving repeated processes of epitaxial growth, ion implantation, and activation annealing is employed to form gate regions with precise gate-to-gate spacing, reducing junction current and gate resistance by using a multi-layered epitaxial structure and optimized ion implantation energies.
Abstract
In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.