Reducing On-Voltage in SiC Semiconductor Devices with Trench Gate Structures
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Summary
Problems
Silicon carbide (SiC) semiconductor devices with trench gate structures face increased on-voltage due to basal plane dislocation expansion to stacking faults during reverse conduction, as holes reach and expand basal plane dislocations, affecting element operation.
Innovation solutions
The SiC semiconductor device incorporates defect portions in the JFET portion to trap carriers, preventing them from reaching basal plane dislocations and thus suppressing the expansion to stacking faults, which includes a substrate with a specific impurity concentration gradient and trench gate structure, allowing the parasitic diode to function as a freewheeling diode without a separate component.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If a trench gate structure is formed in a SiC semiconductor device, then the switching performance is improved, but the on-voltage increases due to basal plane dislocation expansion to stacking faults during reverse conduction
Why choose this principle:
An n-type intermediate layer is introduced between the p-type base layer and the n- drift layer. This intermediate layer acts as a mediator that prevents holes generated during reverse conduction from reaching and expanding basal plane dislocations, thereby suppressing the formation of stacking faults while maintaining the trench gate structure's switching performance
Principle concept:
If a trench gate structure is formed in a SiC semiconductor device, then the switching performance is improved, but the on-voltage increases due to basal plane dislocation expansion to stacking faults during reverse conduction
Why choose this principle:
The n-type intermediate layer is formed in advance during the epitaxial growth process, before the device operates. This preliminary structural preparation ensures that when reverse conduction occurs, holes are blocked from reaching vulnerable dislocation sites, preventing the harmful expansion to stacking faults
Application Domain
Data Source
AI summary:
The SiC semiconductor device incorporates defect portions in the JFET portion to trap carriers, preventing them from reaching basal plane dislocations and thus suppressing the expansion to stacking faults, which includes a substrate with a specific impurity concentration gradient and trench gate structure, allowing the parasitic diode to function as a freewheeling diode without a separate component.
Abstract
A SiC semiconductor device includes a substrate of a first conductivity type, a buffer layer of the first conductivity type on the substrate, a low-concentration layer on the buffer layer, a first deep layer and a JFET portion on the low-concentration layer, a current diffusion layer of the first conductivity type disposed on the JFET portion and having an impurity concentration higher than the low-concentration layer, a second deep layer of a second conductivity type disposed on the first deep layer, a base layer of the second conductivity type disposed on the current diffusion layer and the second deep layer, an impurity region of the first conductivity type disposed in a surface layer portion of the base layer, and a trench gate structure penetrating the impurity region and the base layer and reach the current diffusion layer. The JFET portion is formed with defect portions.