Silicon Carbide Substrate Design for Enhanced Reliability
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Summary
Problems
The existing manufacturing methods for silicon carbide stacked substrates face issues such as increased resistance due to basal plane dislocations (BPDs) in epitaxial layers, which are not effectively suppressed, leading to higher substrate resistance and reduced reliability, especially when current flows through regions with BPDs, and the conversion efficiency of BPDs to harmless threading edge dislocations (TEDs) is insufficient.
Innovation solutions
A silicon carbide stacked substrate structure is developed with specific impurity concentration gradients, including a semiconductor layer with a lower impurity concentration than the SiC substrate and a buffer layer with a higher concentration than the drift layer, to enhance the conversion efficiency of BPDs to TEDs at the interface, thereby reducing substrate resistance and improving reliability.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If silicon carbide substrates are sintered at high temperature (2000°C or above) to achieve high strength and low defect density, then substrate quality improves, but production cost increases and production time extends
Why choose this principle:
The patent changes the sintering temperature parameter from conventional high temperature (2000°C or above) to a lower temperature range (1800-2000°C) by introducing aluminum oxide as a sintering aid, thereby reducing energy consumption and production time while maintaining substrate quality
Principle concept:
If silicon carbide substrates are sintered at high temperature (2000°C or above) to achieve high strength and low defect density, then substrate quality improves, but production cost increases and production time extends
Why choose this principle:
Aluminum oxide is introduced as an intermediary substance (sintering aid) that facilitates the sintering process at lower temperatures by promoting grain boundary formation and reducing sintering resistance, enabling quality substrate production without requiring extreme temperatures
Application Domain
Data Source
AI summary:
A silicon carbide stacked substrate structure is developed with specific impurity concentration gradients, including a semiconductor layer with a lower impurity concentration than the SiC substrate and a buffer layer with a higher concentration than the drift layer, to enhance the conversion efficiency of BPDs to TEDs at the interface, thereby reducing substrate resistance and improving reliability.
Abstract
In a silicon carbide stacked substrate, the efficiency of converting the basal plane dislocation (BPD) which is a fault to deteriorate the current-carrying reliability into a threading edge dislocation (TED) which is a harmless fault is improved, thereby improving the reliability of the silicon carbide stacked substrate. As means therefor, in a silicon carbide stacked substrate including a SiC substrate and a buffer layer and a drift layer which are epitaxial layers sequentially formed on the SiC substrate, a semiconductor layer having an impurity concentration lower than those of the SiC substrate and the buffer layer and higher than that of the drift layer is formed between the SiC substrate and the buffer layer so as to be in contact with an upper surface of the SiC substrate.