Wafer Flatness Control with Backside Compensation Structures
Here’s PatSnap Eureka !
Summary
Problems
Existing wafer flatness control methods, such as uniform backside deposition, are ineffective for semiconductor devices like 3D memory devices that introduce unbalanced variations in different directions, leading to curvature differences in the wafer plane, which can affect device yield.
Innovation solutions
A compensation structure with a specifically-designed pattern is formed on the backside of the wafer based on a model of wafer flatness differences in different directions, using simulation and measurement data to optimize layout, thickness, and material properties to balance wafer flatness.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If uniform backside deposition is used to control wafer flatness, then the manufacturing process is simple, but it is ineffective for devices introducing unbalanced variations in different directions
Why choose this principle:
The patent applies local quality by creating a non-uniform compensation structure with spatially varying thickness and material properties on the wafer backside. The compensation structure has different characteristics in different regions to counteract the unbalanced mechanical stress variations introduced by 3D memory device structures, thereby achieving precise flatness control that uniform deposition cannot provide.
Principle concept:
If uniform backside deposition is used to control wafer flatness, then the manufacturing process is simple, but it is ineffective for devices introducing unbalanced variations in different directions
Why choose this principle:
The patent employs asymmetry by designing a compensation structure that is intentionally non-uniform and asymmetric in its distribution, thickness, and material composition. This asymmetric structure is specifically tailored to counterbalance the asymmetric stress patterns generated by 3D memory device architectures, enabling effective flatness control for devices with directional variations.
Application Domain
Data Source
AI summary:
A compensation structure with a specifically-designed pattern is formed on the backside of the wafer based on a model of wafer flatness differences in different directions, using simulation and measurement data to optimize layout, thickness, and material properties to balance wafer flatness.
Abstract
Embodiments of semiconductor structures for wafer flatness control and methods for using and forming the same are disclosed. In an example, a model indicative of a flatness difference of a wafer between a first direction and a second direction is obtained. The flatness difference is associated with one of a plurality of fabrication stages of a plurality of semiconductor devices on a front side of the wafer. A compensation pattern is determined for reducing the flatness difference based on the model. At the one of the plurality of the fabrication stages, a compensation structure is formed on a backside opposite to the front side of the wafer based on the compensation pattern to reduce the flatness difference.