Voltage control and regulation circuit with low cost fast response to voltage sags

Abstract

The application discloses a low-cost voltage control and regulation circuit for fast response to voltage dip, and in particular solves the problems of excessive influence of on-chip response to voltage dip on system performance and poor flexibility, and belongs to the technical field of basic electronic circuits.The circuit comprises a voltage monitoring unit, a current prediction unit, a voltage loop controller, a current loop controller, a clock gating circuit and a performance-aware voltage controller, and through a full-closed loop and double-loop architecture, the voltage is adjusted in real time, and the performance cost during the adjustment is greatly reduced; the voltage loop controller and the current loop controller are jointly used, different control parameters are used to respectively fit frequency adjustment amounts corresponding to the voltage and the current, and a flexible double-closed loop control strategy is realized; the clock gating circuit is used to process the frequency adjustment amount, and the working frequency of a controlled object is quickly controlled through clock enabling; and the performance-aware voltage controller and the clock gating circuit are jointly used, so that the purpose of simply and efficiently resisting voltage dip is realized.

Description

Technical Field

[0001] This invention belongs to the field of basic electronic circuit technology, and in particular relates to an on-chip, low-cost, fast-response voltage control and regulation circuit for voltage sags. Background Technology

[0002] The rapid development of integrated circuits has required processors to handle more complex and varied tasks, and drastic load changes pose challenges to the stability of power supply networks. Load changes directly lead to changes in supply current, resulting in voltage sags. This means insufficient timing margin or even failure to meet minimum requirements, leading to calculation errors. Voltage sags can generally be divided into three stages, with the first-order voltage sag being the most difficult to monitor. Its frequency and amplitude depend on the package inductor and on-chip capacitor, ranging from tens to hundreds of megahertz in frequency and tens to hundreds of millivolts in amplitude. When a voltage sag occurs, various methods such as LDOs and DC-DC converters are needed to restore the voltage and prevent system errors.

[0003] Conventional voltage sag control and regulation systems often require multiple cycles for frequency recovery to avoid introducing new voltage sags. However, the entire process requires a recovery time of several microseconds, which means that loads experiencing frequent voltage sags can severely impact chip performance. Designing different frequency recovery strategies based on the degree of voltage sag would incur additional hardware costs, increasing design complexity and reducing system flexibility. Therefore, a low-cost, fast-responding voltage control and regulation circuit is needed to quickly address voltage sag phenomena with minimal performance overhead. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of the aforementioned background technology and the main design challenges by providing a low-cost, fast-response voltage control and regulation circuit for voltage sags. Through a fully closed-loop, dual-loop circuit architecture, the invention achieves the objective of fast response to voltage sags based on the frequency adjustment corresponding to voltage and current, thus solving the problems of excessive impact on system performance and poor flexibility of on-chip voltage sag response schemes.

[0005] To achieve the above-mentioned objectives, the present invention employs the following technical solution:

[0006] A low-cost, fast-response voltage control and regulation circuit operates on a controlled object consisting of a chip circuit and an external power supply chip that powers it. The voltage control and regulation circuit includes: a voltage monitoring unit, a current prediction unit, a voltage loop controller, a current loop controller, a clock gating circuit, and a performance-aware voltage controller. The voltage monitoring unit monitors and generates the current clock cycle voltage code value of the controlled object, with a 1-2 cycle delay in the output code value. The current prediction unit monitors the current clock cycle current code value and predicts the current code value for the controlled object in future clock cycles. The voltage loop controller generates a frequency control quantity controlled by the input voltage based on the current clock cycle voltage code value and the current clock cycle current code value. The current loop controller generates a frequency control quantity controlled by the input current based on the future clock cycle current code value. The clock gating circuit receives the frequency control quantities controlled by the input voltage and the frequency control quantities controlled by the input current, and generates a clock enable signal and a global clock signal. The global clock signal is used to adaptively adjust the clock frequency of the chip circuit. The performance-aware voltage controller receives the clock enable signal output by the clock gating circuit and generates a voltage regulation command to adaptively adjust the output voltage of the external power supply chip.

[0007] As a further optimization of the voltage control and regulation circuit for low-cost, fast response to voltage drops, the voltage loop controller processes the current clock cycle voltage code value and current clock cycle current code value as follows to generate a frequency control quantity controlled by the input voltage: The current clock cycle voltage code value is low-pass filtered to obtain the current voltage value; the current voltage value is subtracted from the static voltage value to obtain the delayed voltage drop S1; the current voltage drop F1 is predicted based on the delayed voltage drop S1 and the current clock cycle current code value; and the frequency control quantity Vcf controlled by the input voltage is calculated based on the delayed voltage drop S1, the current voltage drop F1, the target voltage drop T1, and the proportional coefficient a1 and differential coefficient b1 of the voltage loop controller. .

[0008] As a further optimization of the voltage control and regulation circuit for low-cost, fast response to voltage sags, the current loop controller processes the future clock cycle current code value as follows to generate a frequency control quantity controlled by the input current: The current code value of the current cycle is obtained based on the future clock cycle current code value; the current code value of the future clock cycle and the current clock cycle current code value are averaged and filtered to obtain the filtered predicted current value F2; the current clock cycle current code value is exponentially weighted and filtered to obtain the filtered current current value S2; and the frequency control quantity Icf controlled by the input current is calculated by combining the filtered predicted current value F2, the filtered current current value S2, the target current value T2, and the proportional coefficient a2 and differential coefficient b2 of the current loop controller. .

[0009] As a further optimization of the voltage control and regulation circuit for low-cost, fast response to voltage sags, a clock-gated circuit includes: an adder, a modulator, and a gated clock unit; one input of the adder receives a frequency control quantity controlled by the input voltage, and the other input of the adder receives a frequency control quantity controlled by the input current, and the adder outputs a total frequency control quantity; the input of the modulator is connected to the output of the adder, and the modulator outputs a clock enable signal; the input of the gated clock unit is connected to the output of the modulator, and the gated clock unit outputs a global clock signal.

[0010] As a further optimization of voltage control and regulation circuits that provide low-cost, fast response to voltage drops, a performance-aware voltage controller includes: a periodic timer, a clock gating monitor, and voltage judgment logic. The periodic timer periodically outputs a full-count pulse according to configuration parameters. The clock gating monitor receives the clock enable signal and the full-count pulse, records the number of times the clock enable signal is invalid within a monitoring cycle, and periodically resets the count of invalid clock enable signals under the action of the full-count pulse. The voltage judgment logic receives the count of invalid clock enable signals output by the clock gating monitor, compares the voltage rise threshold with the count of invalid clock enable signals when the full-count pulse is valid, and outputs a voltage rise command. When the full-count pulse is valid, it compares the voltage fallback threshold with the count of invalid clock enable signals and outputs a voltage fall command.

[0011] As a further optimization of the voltage control and regulation circuit that provides a low-cost, fast response to voltage drops, the current prediction unit trains and filters the switching weights of key system signals using machine learning algorithms, multiplies and accumulates the switching monitoring results of key system signals, and outputs the predicted current code value for future clock cycles.

[0012] As a further optimization of the voltage control and regulation circuit that provides a low-cost, fast response to voltage drops, a fourth-order low-pass filter implemented through a four-stage pipeline is used to perform low-pass filtering on the voltage code value of the current clock cycle.

[0013] As a further optimization of the voltage control and regulation circuit that provides a low-cost, fast response to voltage drops, the current code value for the current clock cycle is obtained through a first-level register based on the current code value for the future clock cycle.

[0014] As a further optimization of the voltage control and regulation circuit that provides a low-cost, fast response to voltage drops, the modulator is a Δ-Σ modulator.

[0015] The low-cost, fast-response voltage control and regulation circuit proposed in this invention has the following advantages compared to existing voltage sag control and regulation schemes:

[0016] (1) The voltage is adjusted in real time using a fully closed-loop, dual-loop architecture. The voltage and current information are used together to achieve the effect of prediction, which greatly reduces the performance cost during the adjustment period.

[0017] (2) By using a voltage loop controller and a current loop controller in combination, different control parameters are used to fit the frequency adjustment corresponding to the voltage and current, thus realizing a flexible dual closed-loop control strategy.

[0018] (3) By processing the frequency control that integrates voltage monitoring, current monitoring and prediction through the clock gating circuit, a global clock signal is obtained to achieve rapid control of the controlled object. By combining the performance-aware voltage controller and the clock gating circuit, frequent adjustments are avoided through gating counting, and the clock enable signal is converted into the adjustment of the voltage of the controlled object, thus achieving the invention objective of simple and efficient countermeasure against voltage drop. Attached Figure Description

[0019] Figure 1 This is a block diagram of the low-cost, fast-response voltage sag controller and its regulating circuit of the present invention.

[0020] Figure 2 This is a block diagram of the voltage loop controller of the present invention.

[0021] Figure 3 This is a block diagram of the low-pass filter in the voltage loop controller of the present invention.

[0022] Figure 4 This is a block diagram of the current loop controller of the present invention.

[0023] Figure 5 This is a block diagram of the clock gating circuit of the present invention.

[0024] Figure 6 This is a block diagram of the performance-sensing voltage controller of the present invention.

[0025] Figure 7 The waveforms of various signals during the circuit control and voltage regulation process proposed in this invention are shown. Detailed Implementation

[0026] To better understand the purpose, structure, and function of this invention, the prediction circuit for zero-response period voltage sag monitoring of this invention will be described in further detail below with reference to the accompanying drawings.

[0027] like Figure 1As shown, a low-cost, fast-response controller and regulation circuit for a controlled object, operating on a voltage drop, includes a voltage monitoring unit, a current prediction unit, a voltage loop controller, a current loop controller, a clock gating circuit, and a performance-aware voltage controller. The overall circuit architecture is a fully closed-loop architecture. The controlled object, voltage monitoring unit, voltage loop controller, clock gating circuit, and performance-aware voltage controller form one loop, and the controlled object, current prediction unit, current loop controller, clock gating circuit, and performance-aware voltage controller form another loop. The controlled object consists of a chip circuit and an off-chip power supply chip that powers it.

[0028] In this embodiment, the voltage control and regulation circuit proposed in this invention is illustrated by taking a controlled object consisting of a SoC circuit and an off-chip power supply chip that supplies power to it as an example.

[0029] The voltage monitoring unit monitors and generates the current clock cycle voltage code value of the controlled object, with a 1-2 cycle delay in the output code value. The current prediction unit monitors the current clock cycle current code value and predicts the future clock cycle current code value of the controlled object. The voltage loop controller generates a frequency control quantity controlled by the input voltage based on the current clock cycle voltage code value and the current clock cycle current code value. The current loop controller generates a frequency control quantity controlled by the input current based on the future clock cycle current code value. The clock gating circuit receives the frequency control quantities controlled by the input voltage and the frequency control quantities controlled by the input current and generates a fast-response clock enable signal and a global clock signal. The global clock signal is used to adaptively adjust the clock frequency of the SoC circuit. The performance-aware voltage controller receives the clock enable signal output by the clock gating circuit and generates a voltage regulation command to adaptively adjust the output voltage of the external power supply chip.

[0030] The voltage monitoring unit is a circuit module that monitors the voltage of the object under test. The current prediction unit uses a machine learning algorithm to train and select the flip weights of key system signals. After multiplying and accumulating the monitoring results of the flip weights of key system signals, it outputs the predicted current code value for the future clock cycle, thus achieving the effect of predicting the current of the controlled object. At the same time, it can also output the monitoring result of the current code value for the current clock cycle.

[0031] like Figure 2As shown, the voltage loop controller first sets the target voltage drop, proportional term coefficient, and derivative term coefficient as needed, denoted as T1, a1, and b1 respectively. After receiving the voltage code value of the current clock cycle output by the voltage monitoring unit, it filters out high-frequency noise through a low-pass filter to ensure system stability and outputs the corresponding current voltage value. The actual delayed voltage drop S1 is obtained by subtracting the current voltage value from the static voltage value. The delayed voltage drop S1 is then passed through the voltage prediction unit to obtain the current voltage drop F1 without delay. The delayed voltage drop S1, combined with the current voltage drop F1, the target voltage drop T1, the proportional term coefficient a1, and the derivative term coefficient b1, is used to calculate the frequency control quantity Vcf controlled by the input voltage.

[0032] The acquisition of frequency control quantities controlled by input voltage includes the following steps:

[0033] Step 101: Read the voltage code value of the current clock cycle output by the voltage monitoring unit. If the voltage code value of the current clock cycle output changes, proceed to step 102; otherwise, proceed to step 101.

[0034] Step 102: The voltage code value of the current clock cycle output by the voltage monitoring unit is passed through a low-pass filter and then subtracted from the static voltage value to complete the data preprocessing, and the delayed voltage drop is obtained. The data of the delayed voltage drop is recorded as S1. The delayed voltage drop is the code value obtained after the current voltage drop code value is passed through the register. Proceed to step 103.

[0035] Step 103: The delayed voltage drop data S1 and the current clock cycle current code value are used to obtain the current voltage drop through the voltage prediction unit. The current voltage drop data is recorded as F1, and then proceed to step 104.

[0036] Step 104: Calculate the frequency control quantity controlled by the input voltage. .

[0037] like Figure 3 As shown, the low-pass filter in the voltage loop controller is implemented as a fourth-order low-pass filter using a four-stage pipeline. By adjusting the input, output, and the position of the filter coefficient weighting, the critical path length is reduced to a single-stage multiplication and addition. By adjusting the filter coefficients, the filter timing is brought to 2GHz.

[0038] like Figure 4As shown, the current loop controller first sets the target current value, proportional coefficient, and derivative coefficient as needed, denoted as T2, a2, and b2 respectively. After receiving the future clock cycle current code value output by the current prediction unit, it obtains the current code value of the current clock cycle through a first-level register. The two are then filtered by an averaging filter to remove high-frequency noise to ensure system stability and output the corresponding filtered predicted current value F2. In addition, the current clock cycle current code value is passed through an exponential weighting filter to obtain the filtered current current value S2. The filtered predicted current value F2, combined with the filtered current current value S2, the target current value T2, the proportional coefficient a2, and the derivative coefficient b2, is used to calculate the frequency control quantity Icf controlled by the input current.

[0039] The acquisition of frequency control quantities controlled by input current includes the following steps:

[0040] Step 201: Read the future clock cycle current code value output by the current prediction unit. If the output future clock cycle current code value changes, proceed to step 202; otherwise, proceed to step 201.

[0041] Step 202: After passing the future clock cycle current code value output by the current prediction unit through the first-level register, obtain the current code value of the current clock cycle, and proceed to step 203;

[0042] Step 203: Pass the current code value of the future clock cycle and the current code value of the current cycle through an average filter to obtain the filtered predicted current value. Record the data of the filtered predicted current value as F2, and proceed to step 204.

[0043] Step 204: Pass the current code value of the current clock cycle through an exponentially weighted average filter to obtain the filtered current value. Record the filtered current value as S2 and proceed to step 205.

[0044] Step 205: Calculate the frequency control quantity controlled by the input current. .

[0045] like Figure 5As shown, the clock gating circuit combines the frequency control quantity controlled by the input voltage and the frequency control quantity controlled by the input current to generate a clock gating signal. When the frequency control quantity is too large, the clock gating signal is invalidated. To implement this clock gating adjustment circuit, the frequency control quantity controlled by the input voltage and the frequency control quantity controlled by the input current are first added to obtain the total frequency control quantity. This total frequency control quantity is then passed through a Δ-Σ modulator to obtain the clock gating signal, which is also the clock enable signal. The gated clock signal is then output through the clock gating unit, becoming the global clock signal for the controlled object. The Δ-Σ modulator includes a difference stage, an integration stage, and a binarization stage. The difference stage calculates the output error based on the feedback signal, the integration stage integrates the error, and the result is a single-bit signal output through a binarizer. Through continuous feedback adjustment, the integral error value is controlled within a certain range, achieving the effect of the output signal following the input signal. This clock gating circuit can complete the adjustment within one cycle, offering the advantage of fast response.

[0046] like Figure 6 As shown, the performance-aware voltage controller receives the clock enable signal generated by the clock gating circuit, calculates the clock gating ratio to sense the performance degradation caused by gating adjustment, and uses this as a basis to guide the external power supply chip to adjust the supply voltage. First, the periodic timer periodically outputs a full-count pulse according to the configuration parameters; then, the clock gating monitor uses the full-count pulse signal to periodically reset to zero, and records the number of times the clock enable signal from the clock gating circuit is invalid within a monitoring cycle, outputting the accumulated value; finally, the voltage judgment logic compares the voltage rise threshold and voltage fall threshold with the accumulated value of the number of invalid clock enable signals when the full-count pulse is valid, and outputs a voltage rise command and a voltage fall command. The external power supply chip adjusts the output voltage according to these two signals, thus performing performance-aware voltage regulation.

[0047] like Figure 7As shown, a current excitation is applied at 10ns to induce a voltage change. Because the current loop controller uses predicted dynamic current information, it can generate a frequency control quantity controlled by the input current before the voltage drops. Subsequently, since the predicted dynamic current is always a step current amplitude, the frequency control quantity controlled by the input current remains at a high level. At 10ns, the voltage loop controller senses a rapid voltage drop based on data from the voltage monitoring unit and outputs a large frequency control quantity controlled by the input voltage. Subsequently, as the voltage stabilizes, the frequency control quantity controlled by the input voltage gradually decreases. The clock gating circuit determines whether to perform clock gating based on both the frequency control quantities controlled by the input current and the frequency control quantities controlled by the input voltage. At 10ns, because both the frequency control quantities controlled by the input voltage and the frequency control quantities controlled by the input current are relatively large, the clock enable signal is pulled low. Then, at 12ns, the gated clock signal no longer outputs a rising edge, so the dynamic current returns to zero. The clock enable signal only becomes effective again when the voltage recovers to a higher level. After multiple adjustments, the voltage gradually stabilizes, and the gated clock signal returns to its normal frequency.

[0048] It is understood that the present invention has been described through some embodiments, and those skilled in the art can make various changes or equivalent substitutions to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A low-cost, fast-response voltage control and regulation circuit for voltage sags, operating on a controlled object consisting of a chip circuit and an external power supply chip supplying power to it, characterized in that... The voltage control and regulation circuit includes: The voltage monitoring unit is used to monitor and generate the current clock cycle voltage code value of the controlled object, and the output code value has a delay of 1-2 cycles; The current prediction unit is used to monitor the current code value in the current clock cycle and predict the current code value of the controlled object in the future clock cycles. A voltage loop controller is used to generate a frequency control quantity controlled by the input voltage based on the voltage code value and the current code value of the current clock cycle. A current loop controller is used to generate frequency control quantities controlled by the input current based on the current code value of future clock cycles. A clock gating circuit is used to receive frequency control quantities controlled by input voltage and frequency control quantities controlled by input current, and to generate a clock enable signal and a global clock signal, wherein the global clock signal is used to adaptively adjust the clock frequency of the chip circuit; and, A performance-aware voltage controller receives the clock enable signal from the clock gating circuit and generates a voltage regulation command to adaptively adjust the output voltage of the external power supply chip.

2. The low-cost, fast-response voltage control and regulation circuit for voltage sags according to claim 1, characterized in that, The voltage loop controller processes the current clock cycle voltage code value and current clock cycle current code value as follows to generate a frequency control quantity controlled by the input voltage: The current clock cycle voltage code value is low-pass filtered to obtain the current voltage value; the current voltage value is subtracted from the static voltage value to obtain the delayed voltage drop S1; the current voltage drop F1 is predicted based on the delayed voltage drop S1 and the current clock cycle current code value; and the frequency control quantity Vcf controlled by the input voltage is calculated based on the delayed voltage drop S1, the current voltage drop F1, the target voltage drop T1, and the proportional coefficient a1 and differential coefficient b1 of the voltage loop controller. .

3. The low-cost, fast-response voltage control and regulation circuit for rapid voltage sags according to claim 1, characterized in that, The current loop controller processes the future clock cycle current code value to generate a frequency control quantity controlled by the input current as follows: Based on the future clock cycle current code value, obtain the current code value of the current cycle; perform an average filter on both the future and current clock cycle current code values ​​to obtain a filtered predicted current value F2; perform an exponentially weighted filter on the current clock cycle current code value to obtain a filtered current value S2; and combine the filtered predicted current value F2, the filtered current value S2, the target current value T2, and the proportional coefficient a2 and differential coefficient b2 of the current loop controller to calculate the frequency control quantity Icf controlled by the input current. .

4. The low-cost, fast-response voltage control and regulation circuit for voltage sags according to claim 1, characterized in that, The clock gate circuit includes: An adder receives a frequency control quantity controlled by the input voltage at one input terminal and a frequency control quantity controlled by the input current at the other input terminal, and outputs a total frequency control quantity. A modulator, whose input is connected to the output of the adder, outputs a clock enable signal; and, The gated clock unit has its input connected to the output of the modulator and outputs a global clock signal.

5. The low-cost, fast-response voltage control and regulation circuit for rapid voltage sags according to claim 1, characterized in that, The performance-aware voltage controller includes: A periodic timer is used to periodically output a count-full pulse according to configuration parameters; A clock gating monitor receives a clock enable signal and a full-count pulse. Within one monitoring cycle, it records the number of times the clock enable signal is invalid, and periodically resets the count of invalid clock enable signals to zero under the action of the full-count pulse. The voltage judgment logic receives the count value of the number of invalid clock enable signals output by the clock gating monitor. When the count is full and the pulse is valid, it compares the voltage rise threshold with the count value of the number of invalid clock enable signals and outputs a voltage rise command. When the count is full and the pulse is valid, it compares the voltage fallback threshold with the count value of the number of invalid clock enable signals and outputs a voltage fall command.

6. The low-cost, fast-response voltage control and regulation circuit for voltage sags according to claim 1, characterized in that, The current prediction unit trains and filters the flip weights of key system signals using machine learning algorithms, then multiplies and accumulates the flip monitoring results of key system signals to output the prediction result of the current code value for future clock cycles.

7. The low-cost, fast-response voltage control and regulation circuit for rapid voltage sags according to claim 2, characterized in that, A fourth-order low-pass filter, implemented through a four-stage pipeline, is used to perform low-pass filtering on the voltage code value of the current clock cycle.

8. The low-cost, fast-response voltage control and regulation circuit for rapid voltage sags according to claim 3, characterized in that, The current code value for the current clock cycle is obtained by using the first-level register based on the current code value for the future clock cycle.

9. The low-cost, fast-response voltage control and regulation circuit for voltage sags according to claim 4, characterized in that, The modulator is a Δ-Σ modulator.

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