Display device and electronic apparatus

Abstract

The invention provides a display device and electronic equipment, the display device is provided with a display light-transmitting area and a transition display area, the transition display area is located on the periphery of the display light-transmitting area, and the display device comprises a plurality of light-emitting devices arranged in the display light-transmitting area; the plurality of pixel driving circuits are arranged in the transition display area, each pixel driving circuit comprises a driving transistor, and the driving transistor comprises a grid electrode; the grid electrode lead wire is located above the driving transistor, and the grid electrode lead wire is electrically connected with the grid electrode of the driving transistor; the at least one transparent conducting layer is located above the plurality of pixel driving circuits, the at least one transparent conducting layer comprises a plurality of transparent wires, and the plurality of transparent wires are electrically connected with the plurality of light-emitting devices and part of the pixel driving circuits; and the shielding layer is positioned between the plurality of gate leads and the at least one transparent conductive layer, and is arranged corresponding to the plurality of gate leads.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display device and an electronic device. Background Art

[0002] At present, in the design of organic light emitting diode (AMOLED) display panels, it is a general trend to use the under-screen camera area for display. Among them, it is a common solution to use transparent wires to electrically connect the pixels in the under-screen camera area to improve the transmittance of the under-screen camera area, thereby realizing transparent display of the under-screen camera area. However, since the transparent wire forms a parasitic capacitance with the gate lead when passing through the gate lead of the driving transistor of the pixel driving circuit, and the transparent wire is unevenly distributed, there is a difference in the parasitic capacitance between the transparent wire and the gate lead. The difference in parasitic capacitance causes the pixel driving circuit to drive the corresponding pixel to also have a display difference, resulting in the problem of uneven display brightness (Mura) in the organic light emitting diode display panel.

[0003] Therefore, it is necessary to propose a technical solution to solve the problem of uneven display caused by the difference in parasitic capacitance between the transparent wire and the gate lead. Summary of the invention

[0004] The purpose of the present application is to provide a display device and an electronic device to improve the problem of uneven display brightness caused by the difference in parasitic capacitance between a transparent wire and a gate lead.

[0005] A display device, the display device having a display light-transmitting area and a transition display area, the transition display area is located outside the display light-transmitting area, the display device comprises:

[0006] A plurality of light emitting devices are arranged in the light-transmitting display area;

[0007] A plurality of pixel driving circuits are arranged in the transition display area, each of the pixel driving circuits comprising:

[0008] a drive transistor, the drive transistor comprising a gate; and

[0009] A gate lead, the gate lead is located above the driving transistor, and the gate lead is electrically connected to the gate of the driving transistor;

[0010] at least one transparent conductive layer, at least one of the transparent conductive layers is located above the plurality of pixel driving circuits, at least one of the transparent conductive layers comprises a plurality of transparent wires, and the plurality of transparent wires electrically connect the plurality of light emitting devices and part of the pixel driving circuits; and

[0011] A shielding layer is located between the plurality of gate leads and at least one of the transparent conductive layers and is arranged corresponding to the plurality of gate leads.

[0012] In the above display device, in the thickness direction of the display device, the orthographic projections of the plurality of gate leads on the substrate of the display device are located inside the orthographic projection of the shielding layer on the substrate of the display device.

[0013] In the above-mentioned display device, the display device also includes a metal grid for transmitting a DC voltage signal, the metal grid is arranged in the same layer as the shielding layer, and the metal grid arranged in the transition display area and located above the plurality of pixel driving circuits extends out of the shielding layer.

[0014] In the above display device, the display device further comprises a plurality of DC power signal lines, the plurality of DC power signal lines are arranged in the same layer as the plurality of gate leads, and the metal grid is electrically connected to the plurality of DC power signal lines.

[0015] In the above-mentioned display device, the display device also has a main display area, the transition display area is located between the main display area and the display transparent area, an insulating layer is arranged between the multiple DC power signal lines and the metal grid, and the insulating layer is provided with vias in the part corresponding to the main display area, and the metal grid is electrically connected to the multiple DC power signal lines through the vias.

[0016] In the above display device, the DC voltage signal is selected from one of an initialization signal and a DC power supply signal.

[0017] In the above display device, each of the pixel driving circuits further includes a compensation transistor and an electrode plate, wherein the electrode plate is arranged corresponding to the gate of the driving transistor and the electrode plate is located between the gate lead and the gate of the driving transistor.

[0018] One end of the gate lead is electrically connected to the active layer of the compensation transistor of the pixel driving circuit, and the other end of the gate lead is connected to the gate of the driving transistor at least through a via hole on the electrode plate.

[0019] In the above display device, part of the transparent conductive wires extends from the transition display area to the display light-transmitting area, and part of the transparent conductive wires is located in the transition display area.

[0020] In the above display device, the display device includes a plurality of the transparent conductive layers, and the plurality of transparent conductive lines are located in different transparent conductive layers.

[0021] In the above-mentioned display device, the display light-transmitting area is circular in shape, the multiple pixel driving circuits form multiple pixel driving circuit islands, the multiple pixel driving circuit islands are arranged around the display light-transmitting area, and the number of pixel driving circuits in at least two of the pixel driving circuit islands is different.

[0022] An electronic device comprises the above-mentioned display device and a photosensitive unit, wherein the photosensitive unit is arranged corresponding to the display light-transmitting area of ​​the display device.

[0023] Beneficial effect: The present application shields the parasitic capacitance between the gate lead and the transparent wire through a shielding layer, thereby preventing the difference in parasitic capacitance from affecting the difference in the potential of the gate of the driving transistor, improving the stability of the driving transistor in driving the light-emitting device, and avoiding the problem of uneven brightness when the light-emitting device of the display device displays. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a plan view schematic diagram of a display device according to an embodiment of the present application;

[0025] Figure 2 for Figure 1 A partial enlarged schematic diagram of the display device shown;

[0026] Figure 3 for Figure 2 A partial schematic diagram of the display device shown;

[0027] Figure 4 for Figure 3 An equivalent circuit diagram of the second pixel driving circuit shown;

[0028] Figure 5 for Figure 4 A driving timing diagram corresponding to the second pixel driving circuit shown;

[0029] Figure 6 is a schematic cross-sectional view of a display device;

[0030] Figure 7 is a plan schematic diagram of a second pixel driving circuit and wiring connected to the second pixel driving circuit;

[0031] Figure 8-Figure 12 For composition Figure 7 A plan view of a second pixel driving circuit and multiple film layers of wiring connected to the second pixel driving circuit is shown. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0033] The present application provides a display device, which may be a liquid crystal display device or an organic light emitting diode display device. Specifically, the display device is an organic light emitting diode display device.

[0034] See also Figure 1 and Figure 2 As shown, Figure 1 is a plan view of a display device according to an embodiment of the present application, Figure 2 for Figure 1 A partial enlarged schematic diagram of the display device shown, Figure 3 for Figure 2 The display device 100 has a light-transmitting display area 100a, a main display area 100c and a transitional display area 100b. The display device 100 includes a plurality of first display pixels, a plurality of first pixel driving circuits (not shown), a plurality of second display pixels, a plurality of pixel driving circuit islands 101 and a plurality of transparent wires 102.

[0035] The transition display area 100b is located at the periphery of the display light-transmitting area 100a, and the transition display area 100b is located between the main display area 100c and the display light-transmitting area 100a. Both the main display area 100c and the transition display area 100b are used for display. While the display light-transmitting area 100a is used for display, it also has a high light transmittance property. The light transmittance of the display light-transmitting area 100a is greater than the light transmittance of the main display area 100c and the transition display area 100b. The area of ​​the main display area 100c is greater than the area of ​​the transition display area 100b and the area of ​​the display light-transmitting area 100a. The shape of the display light-transmitting area 100a is circular, and the shape of the transition display area 100b is annular. The display light-transmitting area 100a is symmetrical about the symmetry axis AA and the symmetry axis BB, and the symmetry axis AA and the symmetry axis BB are perpendicular to each other.

[0036] A plurality of first display pixels are uniformly arranged in the main display area 100c, and each first display pixel includes a first red sub-pixel 100c1, a first green sub-pixel 100c3, and a first blue sub-pixel 100c2. The first red sub-pixel 100c1, the first green sub-pixel 100c3, and the first blue sub-pixel 100c2 are distributed in the main display area 100c in a Pentile design. The first green sub-pixel 100c3 is elliptical in shape, and the first red sub-pixel 100c1 and the first blue sub-pixel 100c2 are octagonal in shape.

[0037] A plurality of first pixel driving circuits are also arranged in the main display area 100c. One first pixel driving circuit corresponds to driving one sub-pixel (one of the first red sub-pixel 100c1, the first green sub-pixel 100c3 and the first blue sub-pixel 100c2) of the main display area 100c to emit light. Each first pixel driving circuit includes a plurality of metal film layers, and the plurality of first pixel driving circuits are arranged in an array in the main display area 100c, resulting in a low light transmittance of the main display area 100c. The first red sub-pixel 100c1, the first green sub-pixel 100c3 and the first blue sub-pixel 100c2 all include light-emitting devices, which are organic light-emitting diodes.

[0038] A plurality of second display pixels are uniformly arranged in the display light transmission area 100a and the transition display area 100b. Each second display pixel includes a second red sub-pixel 100a1, a second green sub-pixel 100a3 and a second blue sub-pixel 100a2. The second red sub-pixel 100a1, the second green sub-pixel 100a3 and the second blue sub-pixel 100a2 are all distributed in a Pentile design in the display light transmission area 100a and the transition display area 100b. The second red sub-pixel 100a1, the second green sub-pixel 100a3 and the second blue sub-pixel 100a2 are all circular in shape. The second red sub-pixel 100a1, the second green sub-pixel 100a3 and the second blue sub-pixel 100a2 all include a light-emitting device, which is an organic light-emitting diode, and each organic light-emitting diode includes an anode, a cathode and an organic light-emitting layer arranged between the anode and the cathode.

[0039] The size of the first red sub-pixel 100c1 is larger than the size of the second red sub-pixel 100a1, the size of the first green sub-pixel 100c3 is larger than the size of the second green sub-pixel 100a3, and the size of the first blue sub-pixel 100c2 is larger than the size of the second blue sub-pixel 100a2, so as to ensure that the display light-transmitting area 100a has a high light transmittance. From the main display area 100c to the transition display area 100b, the size of the sub-pixel becomes smaller.

[0040] Since the sizes of a second red sub-pixel 100a1 and a first red sub-pixel 100c1 are different, the driving powers of the corresponding driving circuits are also different. Similarly, the driving powers of the driving circuits of the first green sub-pixel 100c3 and the second green sub-pixel 100a3 are also different, and the driving powers of the driving circuits of the first blue sub-pixel 100c2 and the second blue sub-pixel 100a2 are also different. Therefore, the first pixel driving circuit can only be used to drive the first red sub-pixel 100c1, the first green sub-pixel 100c3 and the first blue sub-pixel 100c2 in the main display area 100c, but cannot be used to drive the second red sub-pixel 100a1, the second green sub-pixel 100a3 and the second blue sub-pixel 100a2 in the transition display area 100b and the display light-transmitting area 100a.

[0041] Please combine Figure 2 and Figure 3 , a plurality of pixel driving circuit islands 101 are arranged in the transition display area 100b, each pixel driving circuit island 101 includes a plurality of second pixel driving circuits 1011 arranged in an array, each pixel driving circuit island 101 includes m rows and n columns of second pixel driving circuits 1011, m is greater than or equal to 2, n is greater than or equal to 2, that is, each pixel driving circuit island 101 is in a strip shape. The second pixel driving circuits 1011 of the plurality of pixel driving circuit islands 101 are used to drive the plurality of second display pixels to emit light, that is, the second pixel driving circuits 1011 of the plurality of pixel driving circuit islands 101 are used to drive the second display pixels of the transition display area 100b to emit light, and are also used to drive the second display pixels of the display light-transmitting area 100a to emit light, so as to avoid setting a pixel driving circuit in the display light-transmitting area 100a, and avoid the metal film layer of the pixel driving circuit affecting the light transmittance of the display light-transmitting area 100a, thereby further improving the light transmittance of the display light-transmitting area 100a. A plurality of second pixel driving circuits 1011 form a plurality of pixel driving circuit islands 101, which is beneficial to reducing the space required for the plurality of second pixel driving circuits 1011, and is beneficial to realizing that the second pixel driving circuit 1011 drives the second display pixel corresponding to the display light-transmitting area 100a, however, it causes the lines electrically connected to the second pixel driving circuit 1011 to be concentrated in the area where the pixel driving circuit island 101 is arranged. The pixel driving circuit island 101 refers to a plurality of second pixel driving circuits 1011 that are clustered and arranged in an island shape, wherein the spacing between two adjacent pixel driving circuit islands 101 is greater than the spacing between two adjacent second pixel driving circuits 1011 in the same pixel driving circuit island 101.

[0042] Different from the main display area 100c, a second pixel driving circuit 1011 is used to drive at least two of the plurality of second red sub-pixels 100a1, the plurality of second green sub-pixels 100a3, and the plurality of second blue sub-pixels 100a2, so as to reduce the number of second pixel driving circuits 1011 and the space occupied by the pixel driving circuit island 101, so that the size of the display light-transmitting area 100a can be increased or the transition display area 100b has more space without the pixel driving circuit island 101. The second pixel driving circuit 1011 can be used to drive the sub-pixels emitting the same color light and / or the sub-pixels emitting different color light in the plurality of second red sub-pixels 100a1, the plurality of second green sub-pixels 100a3, and the plurality of second blue sub-pixels 100a2. In the display light-transmitting area 100a, the sub-pixels driven by the same second pixel driving circuit 1011 are electrically connected through transparent wires.

[0043] Specifically, the two second red sub-pixels 100a1 are driven by the same second pixel driving circuit 1011 , the two second blue sub-pixels 100a2 are driven by the same second pixel driving circuit 1011 , and the four second green sub-pixels 100a3 are driven by the same second pixel driving circuit 1011 .

[0044] like Figure 2 As shown, a plurality of pixel driving circuit islands 101 are arranged around the display light-transmitting area 100a, and the number of second pixel driving circuits 1011 in at least two pixel driving circuit islands 101 is different, so that the number of sub-pixels driven by the at least two pixel driving circuit islands 101 is different, which is adapted to the situation that when the display light-transmitting area 100a is circular and part of the second pixel driving circuit 1011 of each pixel driving circuit island 101 is used to drive the corresponding sub-pixels in the display light-transmitting area 100a, the number of sub-pixels corresponding to each pixel driving circuit island 101 in the display light-transmitting area 100a changes.

[0045] The plurality of pixel driving circuit islands 101 include a first group of pixel driving circuit islands 1012 (pixel driving circuit islands 101 above the symmetry axis BB) and a second group of pixel driving circuit islands 1013 (pixel driving circuit islands 101 below the symmetry axis BB). The pixel driving circuit islands 101 in the first group of pixel driving circuit islands 1012 and the pixel driving circuit islands 101 in the second group of pixel driving circuit islands 1013 are symmetrically arranged about the symmetry axis BB, the pixel driving circuit islands 101 in the first group of driving circuit islands 1012 are symmetrically arranged about the symmetry axis AA, and the pixel driving circuit islands 101 in the second group of pixel driving circuit islands 1012 are symmetrically arranged about the symmetry axis AA.

[0046] The number of the second pixel driving circuits 1011 in some pixel driving circuit islands 101 in the first group of pixel driving circuit islands 1012 decreases from close to the symmetry axis AA to far away from the symmetry axis AA, and correspondingly, the number of the second pixel driving circuits 1011 in some pixel driving circuit islands 101 in the second group of pixel driving circuit islands 1013 decreases from close to the symmetry axis AA to far away from the symmetry axis AA. One pixel driving circuit island 101 in the first group of pixel driving circuit islands 1012 and one corresponding pixel driving circuit island 101 in the second group of pixel driving circuit islands 1013 drive the sub-pixels in the areas where the two are located and between the two in the light-transmitting area 100a, such as the sub-pixels in the area 100d. Wherein, each pixel driving circuit island 101 in the first group of pixel driving circuit islands 1012 and the second group of pixel driving circuit islands 1013 is used to drive the sub-pixels in the corresponding area of ​​the pixel driving circuit island 101, and also drives the sub-pixels in the light-transmitting area 100a between the pixel driving circuit island 101 and the corresponding pixel driving circuit island in the second group of pixel driving circuit islands 1013.

[0047] like Figure 3 As shown, in order to improve the transmittance of the display light-transmitting area 100a, a plurality of second pixel driving circuits 1011 are electrically connected to the second red sub-pixel 100a1, the second blue sub-pixel 100a2 and the second green sub-pixel 100a3 of the display light-transmitting area 100a through a plurality of transparent wires 102. Since the plurality of second pixel driving circuits 1011 are concentratedly distributed in an island shape, the number of transparent wires 102 provided for the corresponding pixel driving circuit island 101 is relatively large, and some of the transparent wires 102 will overlap with the gate lead electrically connected to the gate of the driving transistor of the second pixel driving circuit 1011 in the pixel driving circuit island 101. The transparent wires 102 are densely distributed and have differences, resulting in differences in the overlapping areas of different gate leads and the transparent wires 102.

[0048] See also Figure 4-Figure 6 , Figure 4 for Figure 3 The equivalent circuit diagram of the second pixel driving circuit shown in FIG. Figure 5 for Figure 4 The driving timing diagram corresponding to the second pixel driving circuit shown in FIG. Figure 6 A schematic cross-sectional view of a display device.

[0049] Each second pixel driving circuit 1011 includes a driving transistor M1, a switching transistor M2, a compensation transistor M3, an initialization transistor M4, a first light emission control transistor M5, a second light emission control transistor M6, an anode reset transistor M7 and a capacitor C. The driving transistor M1, the switching transistor M2, the compensation transistor M3, the initialization transistor M4, the first light emission control transistor M5, the second light emission control transistor M6 and the anode reset transistor M7 are all P-type transistors.

[0050] The display device 100 also includes a plurality of wirings electrically connected to the second pixel driving circuit 1011, the plurality of wirings including an n-1th level scanning signal line SCAN(n-1), an nth level scanning signal line SCAN(n), a data line D(m), an initialization signal line VI, a DC power signal line VDD, and an nth level light emitting control signal line EM(n) arranged in the transition display area 100b. The n-1th level scanning signal line SCAN(n-1) is used to transmit the n-1th level scanning signal. The nth level scanning signal line SCAN(n) is used to transmit the nth level scanning signal. The data line D(m) is used to transmit the data signal. The DC power signal line VDD is used to transmit the DC power signal. The nth level light emitting control signal line EM(n) is used to transmit the nth level light emitting control signal. The initialization signal line VI transmits an initialization signal or a reset signal.

[0051] The gate electrode G1 of the driving transistor M1 is connected to the first electrode plate C1 of the capacitor C, the drain electrode D3 of the compensation transistor M3, and the source electrode S4 of the initialization transistor M4. The source electrode S1 of the driving transistor M1 is connected to the DC power signal line VDD through the first light-emitting control transistor M5, and the source electrode S1 of the driving transistor M1 is connected to the data line D(m) through the switching transistor M2. The drain electrode D1 of the driving transistor M1 is connected to the light-emitting device OLED through the second light-emitting control transistor M6. When the switching transistor M2 is turned on, the driving transistor M1 receives the data signal transmitted by the data line D(m) and provides a driving current to the light-emitting device OLED.

[0052] The gate G2 of the switch transistor M2 is connected to the n-th level scan signal line SCAN(n), the source S2 of the switch transistor M2 is connected to the data line D(m), the drain D2 of the switch transistor M2 is connected to the source S1 of the drive transistor M1, and the drain D2 of the switch transistor M2 is also connected to the DC power supply signal line VDD through the first light-emitting control transistor M5. The switch transistor M2 is turned on or off according to the n-th level scan signal transmitted by the n-th level scan signal line SCAN(n), and controls whether the data signal transmitted by the data line D(m) is written to the source S1 of the drive transistor M1.

[0053] The gate G3 of the compensation transistor M3 is connected to the n-th level scanning signal line SCAN(n), the source S3 of the compensation transistor M3 is connected to the drain D1 of the driving transistor M1, the source S3 of the compensation transistor M3 is also connected to the light-emitting device OLED through the second light-emitting control transistor M6, and the drain D3 of the compensation transistor M3 is connected to the gate G1 of the driving transistor M1, the source S4 of the initialization transistor M4, and the first electrode plate C1 of the capacitor C. The compensation transistor M3 is turned on according to the n-th level scanning signal transmitted by the n-th level scanning signal line SCAN(n), and is electrically connected to the gate G1 of the driving transistor M1 and the drain D1 of the driving transistor M1.

[0054] The gate G4 of the initialization transistor M4 is connected to the n-1th level scanning signal line SCAN (n-1), the drain D4 of the initialization transistor M4 is connected to the drain D7 of the anode reset transistor M7 and the initialization signal line VI, and the source S4 of the initialization transistor M4 is connected to the gate G1 of the driving transistor M1, the drain D3 of the compensation transistor M3 and the first electrode plate C1 of the capacitor C. The initialization transistor M4 is turned on or off according to the n-1th level scanning signal transmitted by the n-1th level scanning signal line SCAN (n-1), and controls whether the initialization signal transmitted by the initialization signal line VI is written into the gate G1 of the driving transistor M1.

[0055] The gate G5 of the first light-emitting control transistor M5 is connected to the n-th level light-emitting control signal line EM(n), the source S5 of the first light-emitting control transistor M5 is connected to the DC power signal line VDD and the second electrode plate C2 of the capacitor C, and the drain D5 of the first light-emitting control transistor M5 is connected to the source S1 of the driving transistor M1 and the drain D2 of the switching transistor M2. The first light-emitting control transistor M5 is turned on or off according to the n-th level light-emitting control signal transmitted by the n-th level light-emitting control signal line EM(n), and controls whether the DC power signal transmitted by the DC power signal line VDD is written to the source S1 of the driving transistor M1.

[0056] The gate G6 of the second light-emitting control transistor M6 is connected to the n-th level light-emitting control signal line EM(n), the source S6 of the second light-emitting control transistor M6 is connected to the drain D1 of the driving transistor M1 and the source S3 of the compensation transistor M3, and the drain D6 of the second light-emitting control transistor M6 is connected to the anode of the light-emitting device OLED. The second light-emitting control transistor M6 is turned on or off according to the n-th level light-emitting control signal transmitted by the n-th level light-emitting control signal line EM(n), and controls whether the driving current flows into the light-emitting device OLED.

[0057] The gate G7 of the anode reset transistor M7 is connected to the n-th level scan signal line SCAN(n), the drain D7 of the anode reset transistor M7 is connected to the drain D4 of the initialization transistor M4 and the initialization signal line VI, and the source S7 of the anode reset transistor M7 is connected to the anode of the light emitting device OLED and the drain D6 of the second light emitting control transistor M6. The anode reset transistor M7 is turned on or off according to the n-th level scan signal transmitted by the n-th level scan signal line SCAN(n), and controls whether the initialization signal transmitted by the initialization signal line VI is written to the anode of the light emitting device OLED.

[0058] The first electrode plate C1 of the capacitor C is connected to the gate G1 of the driving transistor M1, the source S4 of the initialization transistor M4, and the drain D3 of the compensation transistor M3, and the second electrode plate C2 of the capacitor C is connected to the DC power signal line VDD and the source S5 of the first light-emitting control transistor M5. The capacitor C is used to maintain the voltage of the gate of the driving transistor M1 when the driving transistor M1 drives the light-emitting device OLED to emit light.

[0059] Combination Figure 5 In the initialization stage t1, the n-1th level scanning signal line SCAN(n-1) inputs the n-1th level scanning signal of low level, the initialization transistor M4 is turned on, and the initialization signal transmitted by the initialization signal line VI is transmitted to the gate G1 of the driving transistor M1, so as to initialize the gate G1 of the driving transistor M1; the nth level scanning signal line SCAN(n) inputs the nth level scanning signal of high level, the switching transistor M2, the compensation transistor M3 and the anode reset transistor M7 are all turned off; the nth level light-emitting control signal line EM(n) inputs the nth level light-emitting control signal of high level, and the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are both turned off.

[0060] In the threshold voltage compensation and data voltage writing stage t2, the n-1th level scanning signal line SCAN(n-1) inputs the n-1th level scanning signal of high level, and the initialization transistor M4 is turned off; the nth level scanning signal line SCAN(n) inputs the nth level scanning signal of low level, the switch transistor M2, the compensation transistor M3 and the anode reset transistor M7 are all turned on, the turned-on switch transistor M2 writes the data signal transmitted by the data line D(m) into the source of the driving transistor M1, the turned-on compensation transistor M3 makes the gate G1 of the driving transistor M1 and the drain D1 of the driving transistor M1 electrically connected, and the turned-on anode reset transistor M7 outputs the initialization signal transmitted by the initialization signal line VI to the anode of the light-emitting device OLED; the nth level light-emitting control signal line EM(n) inputs the nth level light-emitting control signal of high level, and the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are both turned off. In this stage, the threshold voltage compensation of the driving transistor M1, the writing of the data signal and the initialization of the anode of the light-emitting device OLED are realized.

[0061] In the light-emitting stage t3, the n-1th level scanning signal line SCAN(n-1) inputs a high-level n-1th level scanning signal, and the initialization transistor M4 is turned off; the n-level scanning signal line SCAN(n) inputs a high-level n-1th level scanning signal, and the switching transistor M2, the compensation transistor M3 and the anode reset transistor M7 are all turned off; the n-level light-emitting control signal line EM(n) inputs a low-level n-level light-emitting control signal, the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are both turned on, the driving transistor M1 is turned on and outputs a driving current, and the light-emitting device OLED emits light.

[0062] like Figure 6 As shown, the display device 100 includes a substrate 111, and each second pixel driving circuit 1011 includes a driving transistor M1, a capacitor, a compensation transistor M3, and a second light-emitting control transistor M6. The display device 100 also includes at least one transparent conductive layer disposed in the transition display area 100b and the display light-transmitting area 100a, the at least one transparent conductive layer is located above the plurality of pixel driving circuit islands 101, and the at least one transparent conductive layer includes a plurality of transparent wires 102. The second pixel driving circuit 1011 and the at least one transparent conductive layer are both disposed on the substrate 111. The substrate 111 may be a flexible substrate or a glass substrate.

[0063] The driving transistor M1 includes a driving active layer P1 and a driving gate 121, and the opposite ends of the driving active layer P1 are doped to form a driving source 111b and a driving drain 111c respectively. The second light-emitting control transistor M6 includes a second light-emitting control active layer P6 and a second light-emitting control gate. The opposite ends of the second light-emitting control active layer P6 are doped to form a second light-emitting control source 116b and a second light-emitting control drain 116c respectively. The driving active layer P1 and the second light-emitting control active layer P6 are arranged in the same layer. The driving gate 121 and the second light-emitting control gate are arranged in the same layer. The compensation active layer of the compensation transistor M3 is arranged in the same layer as the driving active layer P1, and the compensation gate of the compensation transistor M3 is arranged in the same layer as the driving gate 121. The capacitor C includes a first electrode plate C1 and a second electrode plate C2, and the first electrode plate C1 is the driving gate 121.

[0064] The driving active layer P1 is disposed on the substrate 111, the driving gate 121 is disposed above the driving active layer P1, and a first insulating layer 107 is disposed between the driving active layer P1 and the driving gate 121. The second electrode plate C2 is disposed directly above the first electrode plate C1, and a second insulating layer 108 is disposed between the driving gate 121 and the second electrode plate C2. The gate lead 141 is located above the driving transistor M1, and the gate lead 141 is located above the second electrode plate C2, and a third insulating layer 109 is disposed between the gate lead 141 and the second electrode plate C2. One end of each gate lead 141 is electrically connected to the compensation active layer of the compensation transistor M3 of the second pixel driving circuit 1011 through a via hole penetrating the first insulating layer 107, the second insulating layer 108, and the third insulating layer 109, and the other end of the gate lead 141 is electrically connected to the driving gate 121 through a via hole penetrating the third insulating layer 109, the second electrode plate C2, and the second insulating layer 108. The gate lead 141 , the first anode lead 144 and the DC power signal line VDD are located in the same film layer. The DC power signal line VDD inputs and transmits a DC power signal and is electrically connected to the second electrode plate C2 through a via hole penetrating the third insulating layer 109 . The first anode lead 144 is electrically connected to the second light-emitting control drain 116c of the second light-emitting control transistor M6 through a via hole penetrating the third insulating layer 109, the second insulating layer 108 and the first insulating layer 107. The second anode lead 153 is located directly above the first anode lead 144. There is a fourth insulating layer 110 between the second anode lead 153 and the first anode lead 144. The second anode lead 153 is electrically connected to the first anode lead 144 through a via hole penetrating the fourth insulating layer 110. A plurality of transparent wires 102 are located above the second anode lead 153. The plurality of transparent wires 102 are electrically connected to the second anode lead 153, and the plurality of transparent wires 102 are electrically connected to the anode of the light-emitting device OLED, so that the plurality of transparent wires 102 are electrically connected to the plurality of light-emitting devices OLED and part of the second pixel driving circuit 1011. The first insulating layer 107, the second insulating layer 108 and the third insulating layer 109 are all inorganic insulating layers, and the materials for preparing the first insulating layer 107, the second insulating layer 108 and the third insulating layer 109 are selected from at least one of silicon nitride and silicon oxide. The fourth insulating layer 110 is an organic insulating layer, and the material for preparing the organic insulating layer is selected from polyimide.

[0065] The plurality of transparent wires 102 are located in the plurality of transparent conductive layers to increase the layout space of the transparent wires 102 and avoid short circuits between the transparent wires 102 due to the small layout space of the transparent wires 102. The transparent wires 102 are made of at least one of indium tin oxide or indium zinc oxide. An organic insulating layer is provided between the transparent wires 102 located in adjacent film layers.

[0066] The display device includes a shielding layer 151, which is disposed in the transition display area 100b, and is located between a plurality of gate leads 141 and at least one transparent conductive layer, and the shielding layer 151 is disposed corresponding to the gate leads 141. The shielding layer 151 shields the parasitic capacitance between the gate leads 141 and the transparent wires 102, thereby preventing the parasitic capacitance from causing instability in the gate potential of the driving transistor M1, and preventing the parasitic capacitance from causing a large difference in the influence of the parasitic capacitance on the gate potential of the driving transistor M1 due to the difference in the parasitic capacitance, thereby improving the working stability of the driving transistor M1, and preventing the display non-uniformity problem from occurring in the display light-transmitting area 100a of the display device.

[0067] In the thickness direction of the display device 100, the orthographic projections of the multiple gate leads 141 on the substrate 111 of the display device 100 are located inside the orthographic projections of the shielding layer 151 on the substrate 111 of the display device 100, so that the area of ​​the shielding layer 151 corresponding to the gate lead 141 is larger than the area of ​​the gate lead 141, so that the shielding layer 151 completely shields the corresponding gate lead 141, and completely avoids the generation of parasitic capacitance between the multiple gate leads 141 and the multiple transparent wires 102.

[0068] The display device 100 also includes a metal grid 152 for transmitting a DC voltage signal, and the shielding layer 151 is arranged in the same layer as the metal grid 152. Part of the metal grid 152 is arranged directly above the multiple pixel driving circuit islands 101, and part of the metal grid 152 is arranged in the main display area 100c, and the metal grid 152 in the main display area 100c is electrically connected to the metal grid 152 directly above the multiple pixel driving circuit islands 101. The metal grid 152 is electrically connected to the DC power signal line VDD to reduce the resistance voltage drop of the DC power signal transmitted by the DC power line VDD. The metal grid 152 is in a grid shape. The preparation material of the metal grid 152 is selected from at least one of molybdenum, aluminum, titanium and copper.

[0069] The metal grid 152 disposed in the transition display area 100b and located above the plurality of second pixel driving circuits 1011 extends out of the shielding layer 151 so that the shielding layer 151 transmits a fixed voltage signal, and a parasitic capacitance is formed between the shielding layer 151 and the gate lead 141. However, the potential of the shielding layer 151 is stable, and the potential stability of the gate lead 141 can also be ensured, thereby avoiding the potential instability of the gate lead 141 caused by the unstable potential of the transparent wire 102, thereby improving the stability of the gate potential of the driving transistor M1, improving the working stability of the driving transistor M1, and thereby improving the brightness uniformity of the sub-pixels driven by the driving transistor M1.

[0070] The DC voltage signal is selected from one of the initialization signal and the DC power signal. Since the initialization signal is transmitted by the initialization signal line VI, the initialization signal line VI can be electrically connected to the metal grid 152 so that the metal grid 152 transmits the DC voltage signal. The initialization signal line VI is arranged on the same layer as the second electrode plate C2. The DC power signal is transmitted by the DC power signal line VDD, and the DC power signal line VDD can also be electrically connected to the metal grid 152 so that the metal grid 152 transmits the DC voltage signal, so that the shielding layer 151 has a fixed voltage.

[0071] The display device 100 further includes a plurality of DC power signal lines VDD. As mentioned above, the plurality of DC power signal lines VDD are disposed in the same layer as the plurality of gate leads 141, and the metal grid 152 is electrically connected to the plurality of DC power signal lines VDD.

[0072] Part of the DC power signal line VDD is arranged in the transition display area 100b and corresponds to the plurality of pixel driving circuit islands 101, and is electrically connected to the second pixel driving circuit 1011 of the plurality of pixel driving circuit islands 101; part of the DC power signal line VDD is arranged in the main display area 100c and is electrically connected to the first pixel driving circuit. Part of the metal grid 152 arranged corresponding to the plurality of pixel driving circuit islands 101 is arranged corresponding to the plurality of DC power signal lines VDD in the transition display area 100b, that is, the part of the metal grid 152 arranged corresponding to the plurality of pixel driving circuit islands 101 is located directly above the plurality of DC power signal lines VDD in the transition display area 100b, so that the routing lines transmitting the same signal are arranged correspondingly to avoid electrical signal interference.

[0073] Since the driving power of the first pixel driving circuit of the main display area 100c is different from that of the second pixel driving circuit 1011 in the pixel driving circuit island 101, the width of the DC power signal line VDD of the main display area 100c is larger than that of the DC power signal line VDD of the transition display area 100b. When the width of the DC power signal line VDD of the transition display area 100b is smaller, the fourth insulating layer 110 is provided with a via 110a for a portion of the main display area 100c, and the DC power signal line VDD of the main display area 100c is electrically connected to the metal grid 152 of the main display area 100c through the via 110a of the main display area 100c, and since the metal grid 152 of the main display area 100c is connected to the metal grid 152 of the transition display area 100b, the DC power signal line VDD of the transition display area 100b is electrically connected to the metal grid 152 of the transition display area 100b. When the width of the DC power signal line VDD in the transition display area 100b is large, the DC power signal line VDD in the transition display area 100b and the metal grid 152 in the transition display area 100b may also be electrically connected through the via hole provided in the fourth insulating layer 110 corresponding to the transition display area 100b.

[0074] Part of the transparent wire 102 extends from the transition display area 100b to the display transparent area 100a, and part of the transparent wire 102 is located in the transition display area 100b, so that the transparent wire 102 connects the second pixel driving circuit 1011 of the transition display area 100b and the second display pixel of the display transparent area 100a.

[0075] The above solution is described in detail below in conjunction with specific embodiments. Figure 7 is a plan view of a second pixel driving circuit and wiring connected to the second pixel driving circuit, Figure 8-Figure 12 For composition Figure 7 A schematic diagram of a second pixel driving circuit and multiple film layers of wiring connected to the second pixel driving circuit is shown. Figure 8 To pattern the semiconductor layer, Fig. 9 To pattern the first metal layer, Fig.10 To pattern the second metal layer, Fig.11 To pattern the third metal layer, Fig.12 The fourth metal layer is patterned. Figure 8 The patterned semiconductor layer and Fig. 9 The first insulating layer 107 is disposed between the patterned first metal layers. Fig. 9 The patterned first metal layer and Fig.10 The second insulating layer 108 is disposed between the patterned second metal layers. Fig.10 The patterned second metal layer is Fig.11 The third insulating layer 109 is disposed between the patterned third metal layers. Fig.11 The patterned third metal layer is Fig.12 The fourth insulating layer 110 is disposed between the patterned fourth metal layers.

[0076] The wiring connected to the second pixel driving circuit 1011 includes a data line D(m), an initialization signal line VI, an nth level scanning signal line SCAN(n), an n-1th level scanning signal line SCAN(n-1), an nth level light emitting control signal line EM(n) and a DC power signal line VDD.

[0077] The second pixel driving circuit 1011 includes a driving transistor M1, a switching transistor M2, a compensation transistor M3, an initialization transistor M4, a first light emission control transistor M5, a second light emission control transistor M6, an anode reset transistor M7 and a capacitor.

[0078] The patterned semiconductor layer 11 includes a driving channel 111a of the driving transistor M1, a switching channel 112a of the switching transistor M2, a compensation channel 113a of the compensation transistor M3, an initialization channel 114a of the initialization transistor M4, a first light-emitting control channel 115a of the first light-emitting control transistor M5, a second light-emitting control channel 116a of the second light-emitting control transistor M6, and an anode reset channel 117a of the anode reset transistor M7. The driving channel 111a, the switching channel 112a, the compensation channel 113a, the initialization channel 114a, the first light-emitting control channel 115a, the second light-emitting control channel 116a, and the anode reset channel 117a are all located in the same layer. The preparation material of the patterned semiconductor layer 11 can be polycrystalline silicon. The patterned semiconductor layer 11 also includes a driving source 111b and a driving drain 111c of the driving transistor M1. The patterned semiconductor layer 11 also includes a switch source 112b and a switch drain 112c of the switch transistor M2. The patterned semiconductor layer 11 also includes a compensation source 113b and a compensation drain 113c of the compensation transistor M3. The patterned semiconductor layer 11 also includes an initialization source 114b and an initialization drain 114c. The patterned semiconductor layer 11 also includes a first light-emitting control source 115b and a first light-emitting control drain 115c of the first light-emitting control transistor M5. The patterned semiconductor layer 11 also includes a second light-emitting control source 116b and a second light-emitting control drain 116c of the second light-emitting control transistor M6. The patterned semiconductor layer 11 also includes an anode reset source 117b and an anode reset drain 117c of the anode reset transistor M7. The source and drain on the patterned semiconductor layer 11 are obtained by doping the active layer to achieve conductorization.

[0079] The patterned first metal layer 12 includes a driving gate 121 of the driving transistor M1, which is also the first electrode plate C1 of the capacitor. The switching gate 122 of the switching transistor M2 and the compensation gate 123 of the compensation transistor M3 are both part of the n-th level scanning signal line SCAN(n), the compensation gate 124 of the initialization transistor M4 is part of the n-1-th level scanning signal line SCAN(n-1), the first light emission control gate 125 of the first light emission control transistor M5 and the second light emission control gate 126 of the second light emission control transistor M6 are both part of the n-th level light emission control signal line EM(n). The anode reset gate 127 of the anode reset transistor M7 is part of the n-th level scanning signal line SCAN(n). The n-1th level scanning signal line SCAN(n-1), the nth level light emitting control signal line EM(n), two nth level scanning signal lines SCAN(n) and the driving gate 121 of the driving transistor M1 all belong to the patterned first metal layer 12. The n-1th level scanning signal line SCAN(n-1), the nth level light emitting control signal line EM(n) and the nth level scanning signal line SCAN(n) are all arranged in parallel with each other, and the driving gate 121 of the driving transistor M1 is rectangular in shape. The preparation material of the patterned first metal layer 12 includes at least one of molybdenum, aluminum, titanium and copper.

[0080] The patterned second metal layer 13 includes two initialization signal lines VI and a second electrode plate C2. The second electrode plate C2 is arranged corresponding to the driving gate 121 of the driving transistor M1, and the driving gate 121 and the second electrode plate C2 form a capacitor. A via C2a is arranged on the second electrode plate C2. The material for preparing the patterned second metal layer 13 includes at least one of molybdenum, aluminum, titanium and copper.

[0081] The patterned third metal layer 14 includes a gate lead 141, a first initialization lead 142, a second initialization lead 143, a data line D(m), a DC power signal line VDD, and a first anode lead 144. One end of the gate lead 141 is electrically connected to the driving gate 121 of the driving transistor M1 through a first via hole 141a penetrating the third insulating layer 109, the second insulating layer 108, and the second electrode plate C2, and the other end of the gate lead 141 is electrically connected to the compensation drain of the compensation transistor M3 through a second via hole 141b penetrating the third insulating layer 109, the first insulating layer 107, and the second insulating layer 108. One end of the first initialization lead 142 is electrically connected to the initialization signal line VI through a third via hole 142a penetrating the third insulating layer 109, and the other end of the first initialization lead 142 is electrically connected to the initialization drain 114c of the initialization transistor M4 through a fourth via hole 142b penetrating the third insulating layer 109, the second insulating layer 108, and the first insulating layer 107. One end of the second initialization lead 143 is electrically connected to the initialization signal line VI through a fifth via hole 143a penetrating the third insulating layer 109, and the other end of the second initialization lead 143 is electrically connected to the anode reset drain 117c of the anode reset transistor M7 through a sixth via hole 143b penetrating the third insulating layer 109, the second insulating layer 108, and the first insulating layer 107. The first anode lead 144 is electrically connected to the second light emission control drain 116c of the second light emission control transistor M6 through a seventh via hole 144a penetrating the third insulating layer 109, the second insulating layer 108, and the first insulating layer 107. The data line D(m) is electrically connected to the switch source 112b of the switch transistor M2 through an eighth via hole 145a penetrating the third insulating layer 109, the second insulating layer 108, and the first insulating layer 107. The DC power signal line VDD is electrically connected to the first light-emitting control source 115b of the first light-emitting control transistor M5 through the ninth via hole 146b penetrating the third insulating layer 109, the second insulating layer 108 and the first insulating layer 107. The DC power signal line VDD is electrically connected to the second electrode plate C2 through the tenth via hole 146a penetrating the third insulating layer 109, so that the second electrode plate C2 imports the DC power signal. The preparation material of the patterned third metal layer 14 includes at least one of molybdenum, aluminum, titanium and copper. The DC power signal line VDD is arranged in parallel with the data line D(m), and the data line D(m) intersects perpendicularly with the initialization signal line VI and the nth level scanning signal line SCAN(n).

[0082] The patterned fourth metal layer 15 includes a metal grid 152, a shielding layer 151 and a second anode lead 153. The metal grid 152 includes a vertical extension portion 1521 and a horizontal extension portion 1522, and the vertical extension portion 1521 and the horizontal extension portion 1522 intersect vertically and form a grid-shaped metal grid 152. The vertical extension portion 1521 is arranged corresponding to the DC power signal line VDD, and the horizontal extension portion 1522 overlaps with a portion of the second electrode plate C2, so that the routing for transmitting the DC power signal is arranged accordingly. The second anode lead 153 is arranged directly above the first anode lead 144 and is connected to the first anode lead 144 through a via hole penetrating the fourth insulating layer 110. The above-mentioned transparent conductive layer is located above the patterned fourth metal layer 15, and the transparent wire 102 is connected between the second anode lead 153 and the anode of the light-emitting device OLED. The metal grid 152 can be connected to the DC power signal line VDD through a via hole penetrating the fourth insulating layer 110 to introduce a DC power signal. The material of the patterned fourth metal layer 15 includes at least one of molybdenum, aluminum, titanium and copper.

[0083] The present application also provides an electronic device, the electronic device comprising the above-mentioned display device and a photosensitive unit, the photosensitive unit being arranged corresponding to the display light-transmitting area of ​​the display device. The photosensitive unit is a camera.

[0084] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technical personnel in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display device, characterized in that: The display device has a first display area and a second display area, the second display area is located outside the first display area, the light transmittance of the first display area is greater than the light transmittance of the second display area, and the display device includes: substrate; A plurality of light emitting devices are located on the substrate, and at least part of the light emitting devices are arranged in the first display area; A plurality of pixel driving circuits are located on the substrate, at least one of the pixel driving circuits comprising: a drive transistor including a gate; and a gate lead, located at a side of the driving transistor away from the substrate and connected to the gate of the driving transistor; at least one transparent conductive layer, located on a side of the plurality of pixel driving circuits away from the substrate, and comprising a plurality of transparent wires, at least some of which connect the light-emitting devices in the first display area with at least some of the pixel driving circuits; and The metal layer is located between the film layer where the gate lead is located and at least one of the transparent conductive layers, and the orthographic projection of the metal layer on the substrate overlaps with the orthographic projection of the gate lead on the substrate.

2. The display device according to claim 1, characterized in that The orthographic projections of the plurality of gate leads on the substrate are located inside the orthographic projection of the metal layer on the substrate.

3. The display device according to claim 1 or 2, characterized in that: A plurality of the pixel driving circuits are located in the second display area; The display device further includes: a metal grid, which is used to transmit a DC voltage signal and is at least located in the second display area and extends out of the metal layer.

4. The display device according to claim 3, characterized in that: The display device further comprises a plurality of DC power signal lines, the plurality of DC power signal lines are arranged in the same layer as the plurality of gate leads, and the metal grid is electrically connected to the plurality of DC power signal lines.

5. The display device according to claim 4, characterized in that: The display device also has a third display area, the second display area is located between the third display area and the first display area, the metal grid is also located in the third display area, an insulating layer is arranged between the plurality of DC power signal lines and the metal grid, the insulating layer includes vias located in the third display area, and the metal grid is electrically connected to the plurality of DC power signal lines through the vias.

6. The display device according to claim 3, characterized in that: The DC voltage signal is selected from one of an initialization signal and a DC power supply signal.

7. The display device according to claim 1, characterized in that: The pixel driving circuit further includes a compensation transistor and an electrode plate, wherein the electrode plate is arranged corresponding to the gate of the driving transistor and the electrode plate is located between the gate lead and the gate of the driving transistor. One end of the gate lead is electrically connected to the active layer of the compensation transistor of the pixel driving circuit, and the other end of the gate lead is connected to the gate of the driving transistor at least through a via hole on the electrode plate.

8. The display device according to claim 1, characterized in that: A portion of the transparent conductive line extends from the second display area to the first display area, and another portion of the transparent conductive line is located in the second display area.

9. The display device according to claim 1, characterized in that: The display device includes a plurality of the transparent conductive layers, and a plurality of the transparent conductive lines are located in different transparent conductive layers.

10. The display device according to claim 1, characterized in that: The plurality of pixel driving circuits form a plurality of pixel driving circuit islands, the distance between two adjacent pixel driving circuit islands is greater than the distance between two adjacent pixel driving circuits in one pixel driving circuit island, and the plurality of pixel driving circuit islands are arranged around the first display area; and / or, The numbers of the pixel driving circuits in at least two of the pixel driving circuit islands are different; and / or, The first display area is circular in shape.

11. An electronic device, characterized in that: The electronic device comprises the display device according to any one of claims 1 to 10 and a photosensitive unit, wherein the photosensitive unit is arranged corresponding to the first display area of ​​the display device.

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