79870 results about "Hemt circuits" patented technology

The present invention relates to the technical field of circuit control, and relates to a direct-current high-voltage generator regulation and control method and system based on intelligent feedback. A fuzzy control logic operation is performed on an output current flux value and an input voltage fluctuation factor of a load experimental object, so as to obtain the disturbance amplitude of a voltage fluctuation state for a current flux change trend; if a step-up transformer can execute a PID control technology by adjusting a transformation ratio, PID real-time adjustment parameters are calculated, and a crossover mutation operation of individuals is performed on the basis of a fitness function, so as to generate a first boost regulation and control scheme; and if the step-up transformer cannot execute the PID control technology by adjusting the transformation ratio, a calibrated state feedback controller is constructed on the basis of a state variable of the current step-up transformer and an adjustment signal output amplitude, so as to generate a second boost regulation and control scheme. The present invention achieves intelligent feedback regulation and control by independently analyzing components of direct-current high-voltage generators, improving the stability and accuracy of outputting high-voltage direct current.

The invention relates to the technical field of integrated circuit test and calibration, and discloses a chip test and calibration method and a chip tester. The chip test calibration method is applied to a chip test module and specifically comprises the following steps that S101, a starting signal sent by a user terminal is received, environment initialization operation is executed, and after initialization is completed, a system automatically enters a standby mode and waits for an external trigger signal or a user instruction; and S102, synchronously capturing input and output signal waveforms of the tested chip at a preset sampling frequency through a high-precision current sensor and a voltage sampling circuit. Through a dynamic parameter acquisition and real-time compensation technology, a voltage reference error is effectively reduced, the temperature control precision is superior to + / -0.3 DEG C, signal distortion caused by environmental interference is effectively inhibited, a multi-dimensional calibration model is combined with time domain, frequency domain and statistical characteristic analysis, nonlinear errors and system drift can be dynamically corrected, and the system performance is improved. And the attenuation error of a test signal transmission path is lower than 0.02 dB.

A parallel processing unit comprises a plurality of processors each being coupled to a memory access hardware circuitry. Each memory access hardware circuitry is configured to receive, from the coupled processor, a memory access request specifying a coordinate of a multidimensional data structure, wherein the memory access hardware circuit is one of a plurality of memory access circuitry each coupled to a respective one of the processors; and, in response to the memory access request, translate the coordinate of the multidimensional data structure into plural memory addresses for the multidimensional data structure and using the plural memory addresses, asynchronously transfer at least a portion of the multidimensional data structure for processing by at least the coupled processor. The memory locations may be in the shared memory of the coupled processor and / or an external memory.

The invention discloses a high-precision current detection circuit calibration system, and belongs to the technical field of current detection circuit calibration. Comprising a shunt resistor, a Hall sensor array, a chopping amplifier, a low-noise operational amplifier, a temperature sensor, an ADC acquisition unit, an RC low-pass filter, a signal conditioning unit, a main control unit, an environmental parameter adaptive compensation module and a gain adaptive adjustment module. After an original signal is obtained from a multi-channel sensor, a dynamic error model is constructed in combination with temperature data, a long-term imbalance trend is extracted by using a moving average or median filtering algorithm, and real-time compensation is performed through a pre-calibrated temperature-drift function, so that the system maintenance period is remarkably prolonged.

The invention discloses a circuit netlist generation method supporting deep learning model multi-stage reasoning, and belongs to the technical field of electronic circuit design and automation, and the method comprises the steps: obtaining a circuit diagram image through optical scanning, carrying out the preprocessing of the image, carrying out the recognition of a component through a deep learning model YOLOv5, and determining the boundary frame coordinates and class information. And further performing port fine identification on the component, and determining the position and the direction of the port. And eliminating character interference by using an optical character recognition technology, performing wire recognition, including Hough straight line detection and jumper processing, and determining starting point and ending point coordinates of the wire. And matching the identification results of the components, the ports and the wires, constructing a topological structure of a circuit diagram, finally generating a circuit netlist, and performing error elimination and JSON format output. According to the method, automatic netlist generation of the analog circuit diagram can be realized, the analog circuit diagram file is converted into the netlist file with device function annotations, and the efficiency and quality of circuit design and simulation are improved.

The invention discloses a photovoltaic power grid fault identification method and system based on circuit analysis, and relates to the technical field of fault identification, and the method comprises the following steps: obtaining the operation parameters of a photovoltaic power grid, and constructing a circuit analysis model; based on the circuit analysis model, equivalent response curves in different fault scenes are extracted, and the reference operation state is compared to generate a differential residual sequence; performing time-frequency joint decomposition on the differential residual sequence, and stripping photovoltaic output fluctuation from a load disturbance component to obtain a pure circuit characteristic component; based on the pure circuit characteristic component, a multi-dimensional characteristic coordinate space is formed, and the fault type is judged by using the dynamic bending rate of the fault response track; and mapping a fault type discrimination result back to the circuit analysis model, and positioning the position of a fault branch in combination with local disturbance distribution of the node impedance matrix. According to the method, pure circuit characteristic component extraction and multi-dimensional characteristic space dynamic analysis are combined, and accurate judgment of complex fault types and fault branch positioning are achieved.

The invention relates to the technical field of resonance suppression, and discloses an active damping control LC resonance suppression method and device. The method comprises the following steps: performing parameter identification processing based on bus voltage to obtain an inductance value, a capacitance value and a resonance frequency of an LC circuit; extracting a resonant current component of the current signal based on the resonant frequency; calculating damping power according to the resonance current component, and converting the damping power into a voltage compensation instruction under an alpha-beta coordinate system; generating a PWM control signal according to the voltage compensation instruction and a voltage reference instruction; and performing on-off control on the inverter based on the PWM control signal, and injecting power opposite to the resonant current component into the LC circuit to generate a virtual damping effect. Virtual impedance characteristics are seamlessly integrated into inverter control, rapid response of the whole process from resonance detection to power injection is ensured, the resonance peak value is effectively suppressed, and the current quality is improved.

The invention discloses a circuit EMI suppression-oriented multi-knowledge collaborative distillation and optimization method and system, and the method comprises the steps: constructing a basic large language model based on the circuit design of the electronic industry as a student model, and carrying out the adaptive optimization of the circuit design field. Thirdly, integrating the formalized EMI rule base, the simulation data / model base and the expert experience case base, constructing a multi-source heterogeneous teacher knowledge system, and generating a comprehensive guidance signal G; then, candidate circuit design generated by a student model is evaluated through the system, and a multi-objective loss function including basic distillation, rule conformity, performance fitting and expert experience consistency is constructed; according to the method, the universality is reserved by quantifying differences, compliance is ensured through punishment, the performance difference is reduced, dynamic weight adjustment is introduced, and the model performance reaches a preset target through iterative distillation. The model can understand and process terminologies and design rules in the field of circuit design, and the defect that a general AI model lacks domain knowledge is overcome.

The invention provides a method and system for preparing a high-temperature anti-aging test board for chip testing, and relates to the technical field of data energy storage and resource scheduling, and the method comprises the steps: designing a schematic circuit diagram and a PCB wiring scheme; a test plate is made of a high-temperature resistant material; bare board verification, electrical performance verification, program setting verification, high temperature verification and junction temperature measurement verification are carried out; using data is recorded, ultrasonic cleaning and drying are carried out, and a performance evaluation model is established through a hardware management system to judge whether maintenance or replacement is needed. According to the invention, the accuracy of chip testing in a high-temperature environment is improved, and the service life of the test board is prolonged.

The invention discloses a FeFET-based XNOR calculation unit, an array and a working method of the FeFET-based XNOR calculation unit. The unit comprises a FeFET transistor F1, a FeFET transistor F2 and an NMOS transistor M0. The source electrode of the F1 is connected to a bit line BL, the source electrode of the F2 is connected to a bit line BLB, the grid electrode of the F2 and the grid electrode of the F1 are jointly connected to a word line WL, and the drain electrode of the F2 and the drain electrode of the F1 are jointly connected to a node X. The grid electrode of the M0 is connected with the node X, the drain electrode is grounded, and the source electrode is connected to the shared charge line Scl. F1 and F2 are configured to store a weight bit, and by applying a read voltage to WL and applying a voltage corresponding to an input bit to BL and BLB, a voltage level of Scl outputs an XNOR logic calculation result. The array includes a plurality of XNOR computing units arranged in m rows * n columns. WL and Scl ends of each unit are shared in each column, and BL and BLB are shared in each row. According to the invention, the control peripheral circuit of the array word line is simplified, the variability of current is effectively avoided, and the problems of hardware overhead and the like are effectively solved.

The invention relates to the technical field of power electronics, in particular to a filter equivalent circuit design simulation system suitable for an energy storage converter, which comprises a main circuit topology unit, a control strategy unit, a parameter optimization and design unit, a simulation engine unit and a performance evaluation unit, wherein the main circuit topology unit is used for building a filter equivalent circuit topology of the energy storage converter and configuring passive element parameters of an inductor, a capacitor and a resistor. According to the method, automatic high-robustness optimization of filter parameters is realized through genetic algorithm-particle swarm hybrid optimization, multi-objective collaborative optimization and digital twinning auxiliary optimization, and a'design-optimization-verification-iteration 'closed loop is formed by combining dynamic working condition evaluation, reliability modeling and artificial intelligence auxiliary analysis, so that the method has the advantages of high robustness and high robustness. The harmonic suppression capability, efficiency and long-term operation reliability of the filter are remarkably improved, the design period is shortened, and the development cost is reduced.

The present invention discloses an integrated circuit chip with an address code, a key, and a mechanical keyboard. The integrated circuit chip contains a programmable address code, integrates a magnetic induction circuit, a GRB magic color drive circuit, and includes a power pin, a ground pin, and a data pin. The power pins of n integrated circuit chips are connected in parallel to share a power network VCC, the ground pins are connected in parallel to share a ground network GND, and the data pins are connected in parallel to share a data line network DIO connected to an MCU, and data information is transmitted on the data line network DIO. Another integrated circuit chip with an address code only requires a power network VCC and a ground network GND, and data information is modulated and transmitted on the power network, which greatly saves wiring space, reduces the difficulty of PCB design, and exponentially reduces the number of electronic components. In addition, a variety of different customized code sending methods and working modes are provided, making its application simpler, more efficient, and more reliable.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

The invention discloses a charging and discharging control method and device for an elevator energy storage system, a medium and a product, and relates to the field of data processing. The method comprises the steps that real-time operation data such as the position and the load capacity of an elevator car are obtained, and the instantaneous power generation power and the power change rate of a traction machine are determined accordingly; determining a power change predicted value in a future preset time period based on the parameters, and obtaining the total amount of power generation energy required to be stored by the energy storage system through zero setting of a positive value, integral operation and efficiency compensation; according to the power change rate, the state of the energy storage unit and the power grid electricity price time period, the charging and discharging priorities fed back by the super capacitor, the lithium battery and the power grid are determined; controlling the bidirectional DC / DC circuit to switch charging and discharging modes according to the priority, and adjusting the PWM duty ratio of the brake resistor; and based on the charging and discharging mode and the duty ratio, charging and discharging control over the elevator energy storage system is achieved. According to the method, the problem of inaccurate real-time matching of the dynamic load and the energy fluctuation of the current elevator energy storage system can be relieved.

An electronic device can be validated at a circuit-level or device-level to provide supply chain verification of an integrated circuit (IC) product. A modern integrated circuit package can comprise multiple dies, systems and circuitry built from a variety of device-level structures. Device-level verification disclosed herein can confirm that a device-level (sub-) component of an integrated circuit product is sourced by a known or otherwise valid manufacturer. This serves to mitigate or avoid a hacking attempt involving illicit replacement of a component of an IC product by an intermediate handler of the IC product within a supply chain.

The application discloses a pixel driving circuit, a display panel and a display device. The pixel driving circuit comprises a first pixel driving unit, a second pixel driving unit and a third pixel driving unit. The first pixel driving unit comprises a first driving transistor and a first light emitting element. The first driving transistor has a first threshold value adjustment gate and receives a first adjustment signal. The second pixel driving unit comprises a second driving transistor and a second light emitting element. The second driving transistor has a second threshold value adjustment gate and receives a second adjustment signal. The light emitting colors of the first light emitting element and the second light emitting element are different from each other. When the first light emitting element and the second light emitting element display a target gray scale, the voltage values of the first adjustment signal and the second adjustment signal are different.

The invention discloses a high-speed multi-photon detection system and method. The system comprises a detector and a signal processing circuit, wherein the detector is composed of a window plated with a photoelectric cathode, a micro-channel plate stack and an anode; a plurality of incident photons are converted into a plurality of photoelectrons by the photoelectric cathode, and the photoelectrons are converted into electron cloud by the micro-channel plate stack; the incident electron cloud is divided into multiple paths by three layers of staggered metal strip electrodes of the anode, and charge collection is carried out to obtain charge short pulses of each layer of electrode; the signal processing circuit converts the charge short pulses transmitted by the three layers of electrodes into digital pulse signals, obtains the centroid coordinates of the electron cloud from the digital pulse signals as the abscissa value, the ordinate value and the verification value of the incident photon position, combines the abscissa value, the ordinate value and the verification value based on the screening condition to obtain the target two-dimensional coordinates, and finally obtains the target two-dimensional coordinates. And transmitting to a terminal for imaging display. According to the invention, a plurality of synchronous photons can be detected, the overall counting rate of the detector is greatly improved, and the detection efficiency is improved.

A voltage mode driver circuit has a first driver slice has a pullup structure that includes a first transistor and a second transistor and a pulldown structure that includes a third transistor and a fourth transistor. The first transistor has a gate that receives a first version of a first data signal. The second transistor has a gate that receives a first version of a second data signal. The third transistor has a gate that receives a second, complementary version of the first data signal. The fourth transistor has a gate that receives a second, complementary version of the second data signal. The first data signal encodes data in a first mode and enables the pullup and pulldown structures in a second mode of operation. The second data signal encodes data in the second mode of operation and enables the pullup and pulldown structures in the first mode of operation.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

The invention discloses a digital calibration system and method for dynamic response parameters of a surge protection circuit, relates to the technical field of power electronic protection and test calibration, and is used for solving the problem that an existing surge protection circuit calibration method cannot reflect device degradation and dynamic response mismatch. Surge event voltage and current waveforms are collected through a synchronous trigger mechanism, non-stationary signal features are extracted through combined time-frequency analysis, and a voltage-current phase trajectory diagram is constructed to generate a response feature matrix; performing phase-space reconstruction on the matrix, calculating Kolmogorov entropy quantification system stability, and establishing a material degradation transfer function in combination with an energy absorption sequence to generate a grain boundary degradation index; key parameters are screened through L1 regularization regression, and a quantitative relation between a grain boundary degradation index and a protection threshold value is established to realize adaptive threshold value calculation; and executing strategy switching from calibration to predictive maintenance according to the degradation trend and threshold fluctuation change, and outputting a maintenance signal to complete dynamic accurate calibration and reliable operation of the surge protection circuit.

Described are concepts, systems, system architectures, circuits, methods, and techniques directed toward power management and control. In particular, described are concepts, systems, system architectures, circuits, methods, and techniques for implementing power converters that may not have a right-hand pole zero in their linearized, averaged control-to-output transfer function, but that may still have buck and boost functionality.

A multi-layer display including an upper substrate including light emitting diodes (LEDs) fabricated on a topside of the upper substrate, and LED bonding pads fabricated on a bottomside of the upper substrate. The LED bonding pads being electrically connected to the LEDs through vias extending through the upper substrate. The display also including a lower substrate including LED driver circuits and driver bonding pads fabricated on a topside of the lower substrate. The driver bonding pads being electrically connected to the LED driver circuits, where the LED bonding pads and driver bonding pads are aligned and electrically connected to each other, thereby electrically connecting the LED driver circuits to the LEDs.

The invention discloses a high-voltage circuit for an electric flame stove. The high-voltage circuit comprises a PFC circuit, a high-frequency conversion circuit, a boosting transformer, an energy coupling circuit and a voltage doubling circuit which are electrically connected in sequence. According to the EMI filter circuit, common-mode interference and differential-mode interference are filtered out, and pure alternating current input is provided for a back-end PFC circuit; two chips are adopted in the PFC circuit, so that the PFC circuit 300 finally realizes the consistency of the current waveform and the voltage phase; in the other embodiment of the invention, double chips are adopted, so that'fault linkage protection 'is realized; stable discharging of multiple groups of positive and negative electrodes is achieved through multiple groups of single energy coupling capacitors and independent voltage doubling rectifier bridges which are connected in parallel.

The invention relates to the technical field of medical instruments, in particular to a high-precision time interference non-invasive brain deep electrical stimulation method, equipment and system, and solves the problems that two stimulation electrodes are used for each pair of current in traditional time interference-based non-invasive brain deep electrical stimulation, so that the current distribution is relatively dispersed, and the stimulation focusing performance is relatively poor. According to the method, high-precision 4 * 1 electrode configuration is used, two electrodes for applying a stimulation current are changed into a 4 * 1 electrode form, the flowing path of the current is effectively limited, the current is more focused, and the focusing performance of the interference current is further improved. According to the device, high-precision current control is realized through the anti-phase output circuit, the 4 * 1 voltage division circuit, the constant current source module and the impedance detection module; the system supports forward and reverse electrode position optimization, a personalized real finite element head model simulation system based on MRI data is used for guiding practical application, the focusing performance of each pair of current in a target brain region is improved, and therefore the overall stimulation precision in the target brain region is improved.

A multi-phase LLC resonant converter circuit (10) includes: first to third LLC resonant converters each including a series circuit (S1 to S3) of a first switch and a second switch that are connected in parallel to a DC power supply, a high-frequency transformer (T1 to T3) including a primary-side winding and a secondary-side winding, a resonant circuit including a resonant reactor (Lr1 to Lr3) connected between a connection point of the first switch and the second switch and one end of the primary-side winding, a resonant capacitor (Cr1 to Cr3) in which one end is connected to the other end of the primary-side winding, and a divided resonant capacitor (Cn1 to Cn3) in which one end is connected to a connection point of the primary-side winding and the resonant capacitor; a first neutral line (N1) that connects the other end of the resonant capacitor; a neutral line reactor (Ln) connected between the first neutral line and a power supply line of the DC power supply; and a second neutral line (N2) that connects the other end of the divided resonant capacitor.

The invention discloses a pulse stable output control method and system for an ns-level high repetition frequency fast pulse power supply, and relates to the technical field of automatic control, the system is composed of a plurality of functional modules, and the system comprises a self-adaptive absorption module, a control module and an output control module, and the self-adaptive absorption module obtains power supply parameters through real-time sampling, and the power supply parameters comprise load impedance and switch tube parasitic parameters; dynamically optimizing R and C parameters of the RCD absorption circuit and the active clamping circuit based on power supply parameters; the feed-forward prediction module is used for extracting derivative state information according to the power supply parameters, acquiring load current feed-forward and resonant circuit states based on the derivative state information, modeling based on the load current feed-forward and resonant circuit states, and predicting the drain-source voltage valley bottom moment of the switch tube; and the multi-section variable impedance transmission module adopts a three-section variable impedance structure, performs broadband impedance matching based on R and C parameters of the optimized RCD absorption circuit and the active clamping circuit, inhibits pulse leading edge reflection distortion, and outputs undistorted pulse signals.

The invention discloses a nanosecond-order delay transistor reliability test system and method, and belongs to the technical field of transistor test. The test system is divided into three parts, namely a voltage stress value and stress duration control module, a current control module and a hard switch transient and on-resistance test module. The drain voltage stresses are respectively used for controlling the drain voltage stress value and the drain voltage stress duration of the transistor to be tested; the current during hard switch testing is determined; and the conduction time is long. The test system processes signals through a hardware circuit, can convert an input single-path pulse signal into two paths of inverted pulse signals with dead time, and improves the safety of the test system. The voltage stress duration, the current and the conduction duration of the drain electrode of the transistor to be tested can be flexibly regulated and controlled only by inputting a pulse signal to each of the three modules. Simulation and experiments prove that the measurement delay of switching to the test state after the drain electrode voltage stress is ended is nanosecond magnitude, and the method has important significance for monitoring performance degradation after the transistor drain electrode voltage stress is monitored in real time.

The invention relates to a retiming circuit applied to an ultra-high-speed and high-precision DAC (Digital-to-Analog Converter), which comprises an alignment module, a cross point adjusting module, a coding module, a phase detection module and a digital module, the coding module is connected with the alignment module, the phase detection module is connected with the cross point adjusting module and the coding module, and the digital module is connected with the phase detection module and the alignment module. According to the circuit structure provided by the invention, the sampling clock can be accurately aligned to the center of a data eye pattern, so that the delay difference between a clock tree and a data path caused by process deviation and the like is effectively reduced, the high-frequency spurious suppression performance is improved by eliminating nonlinear distortion caused by time sequence errors, the SFDR is greatly improved, and compared with a traditional scheme, the SNR is effectively improved.

The invention relates to the technical field of integrated circuits, and provides a clock domain crossing synchronization circuit and method based on a multiphase clock, and the circuit comprises a selector, an asynchronous clock synchronization module and a digital signal processor. Wherein serial data to be transmitted and a low-frequency clock are input into the selector, and the selector is used for outputting corresponding RX parallel data to the asynchronous clock synchronization module according to the serial data and the low-frequency clock; the asynchronous clock synchronization module is used for outputting corresponding alignment data to the digital signal processor according to the input RX parallel data, the clock of the digital signal processor and the low-frequency clock; the asynchronous clock synchronization module is used for performing phase alignment on the RX parallel data and a clock of the digital signal processor; and the digital signal processor is used for carrying out data processing on the alignment data. According to the invention, stable transmission of low-delay cross-clock domain data can be realized.

Luminance information and luminance change information are obtained at the same timing with high resolution. In one example, a solid-state imaging device includes pixels and a control circuit. Each of the pixels includes a photoelectric conversion element that generates an electrical signal based upon incident light, a first pixel circuit that converts the electrical signal into first information, and a second pixel circuit that converts the electrical signal into second information. The control circuit controls each of the pixels such that the photoelectric conversion element is connected to either the first pixel circuit or the second pixel circuit.