111034 results about "Hemt circuits" patented technology

An electrosurgical instrument comprising an end effector is disclosed. The end effector comprises a first jaw and a second jaw. The first jaw comprises a first electrode. The end effector is movable from an open configuration to a closed configuration to grasp tissue. The second jaw comprises a second electrode configured to deliver a first monopolar energy to the tissue, a third electrode, and a conductive circuit selectively transitionable between a connected configuration with the third electrode and a disconnected configuration with the third electrode. In the connected configuration, the third electrode is configured to cooperate with the first electrode to deliver bipolar energy to the tissue. The conductive circuit defines a return path for the bipolar energy. In the disconnected configuration, the first electrode is configured to deliver a second monopolar energy to the tissue.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

The present invention relates to the technical field of circuit control, and relates to a direct-current high-voltage generator regulation and control method and system based on intelligent feedback. A fuzzy control logic operation is performed on an output current flux value and an input voltage fluctuation factor of a load experimental object, so as to obtain the disturbance amplitude of a voltage fluctuation state for a current flux change trend; if a step-up transformer can execute a PID control technology by adjusting a transformation ratio, PID real-time adjustment parameters are calculated, and a crossover mutation operation of individuals is performed on the basis of a fitness function, so as to generate a first boost regulation and control scheme; and if the step-up transformer cannot execute the PID control technology by adjusting the transformation ratio, a calibrated state feedback controller is constructed on the basis of a state variable of the current step-up transformer and an adjustment signal output amplitude, so as to generate a second boost regulation and control scheme. The present invention achieves intelligent feedback regulation and control by independently analyzing components of direct-current high-voltage generators, improving the stability and accuracy of outputting high-voltage direct current.

The invention provides a single-tube boost PFC circuit control method and system for single-cycle control, and relates to the technical field of data processing, and the method comprises the steps: generating a self-adaptive PWM control signal according to a duty ratio adjustment amount and a frequency compensation factor, and dynamically limiting the pulse current amplitude of a power switch tube through a peak current prediction algorithm, a load current change rate is generated based on the real-time relevance between the pulse current amplitude and the load current; setting a first monitoring point in a dynamic duty ratio change path of the PWM control signal, and extracting a duty ratio change rate and a switching frequency fluctuation parameter in real time; setting a second monitoring point in a feedback path of a load current change rate, and extracting a load current slope characteristic and a transient change amplitude in real time; and based on the parameters of the first monitoring point and the second monitoring point, generating a correction factor through a dynamic response correlation model. According to the invention, a high power factor can be realized under wide input voltage and load fluctuation.

The invention discloses a power semiconductor device aging on-line diagnosis method, which relates to the field of power electronics, and comprises the following steps: integrating an intelligent sensor and an aging test circuit, and establishing a multi-physics field coupling simulation model; based on the multi-physics field coupling simulation model, evaluating the aging state of the current device to obtain the health index of the device; based on the multi-dimensional data matrix, constructing an anomaly detection model, and outputting an anomaly detection result; predicting the failure probability and the remaining service life of the semiconductor device according to an abnormal detection result; generating a maintenance suggestion based on the predicted failure probability and remaining useful life of the semiconductor device; according to the method, the maintenance suggestion is generated according to the prediction result, the user is guided to take preventive maintenance measures in time, the accuracy of aging state evaluation is improved, the timeliness of fault early warning is enhanced, and economic losses and technical risks caused by sudden faults are reduced.

The invention relates to a V2G-based alternating current charging power adjusting method and device. The method comprises the following steps: carrying out multi-scale data acquisition and preprocessing on a V2G alternating current charging system to obtain a standardized system state data set; constructing a system dynamic model comprising a power grid voltage characteristic and a charging power characteristic; carrying out decomposition to obtain a power output mapping relation calculation, and obtaining a power modulation control parameter; establishing a fast and slow time scale coordination control framework, and designing a power regulation agent and a voltage regulation agent to obtain a coordination control strategy; checking a charging power limit value constraint, a voltage limit value constraint and a power factor constraint to obtain a constraint violation judgment result, and executing constraint projection calculation to obtain a target control instruction; and controlling a power conversion circuit of the charging pile to execute power regulation operation. According to the invention, a hierarchical control structure is adopted, the control complexity of the system is reduced, and the robustness and the adaptive ability of the control strategy are improved.

The invention relates to the technical field of integrated circuit test and calibration, and discloses a chip test and calibration method and a chip tester. The chip test calibration method is applied to a chip test module and specifically comprises the following steps that S101, a starting signal sent by a user terminal is received, environment initialization operation is executed, and after initialization is completed, a system automatically enters a standby mode and waits for an external trigger signal or a user instruction; and S102, synchronously capturing input and output signal waveforms of the tested chip at a preset sampling frequency through a high-precision current sensor and a voltage sampling circuit. Through a dynamic parameter acquisition and real-time compensation technology, a voltage reference error is effectively reduced, the temperature control precision is superior to + / -0.3 DEG C, signal distortion caused by environmental interference is effectively inhibited, a multi-dimensional calibration model is combined with time domain, frequency domain and statistical characteristic analysis, nonlinear errors and system drift can be dynamically corrected, and the system performance is improved. And the attenuation error of a test signal transmission path is lower than 0.02 dB.

A multi-chip package includes a ball-grid-array (BGA) substrate; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the ball-grid-array (BGA) substrate; a plurality of first metal bumps between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and ball-grid-array (BGA) substrate, wherein each of the plurality of first metal bumps has a top end joining the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and a bottom end joining the ball-grid-array (BGA) substrate; a non-volatile-memory (NVM) integrated-circuit (IC) chip package over the ball-grid-array (BGA) substrate, wherein the non-volatile-memory (NVM) integrated-circuit (IC) chip package comprises a circuit substrate, a non-volatile-memory (NVM) integrated-circuit (IC) chip over and coupling to the circuit substrate and a plurality of second metal bumps under and on the circuit substrate and bonded to the ball-grid-array (BGA) substrate; and a plurality of tin-containing bumps under and on the ball-grid-array (BGA) substrate.

The invention relates to the technical field of battery management, and discloses an equalizing charging method, device and equipment for a power battery pack. The method comprises the following steps: performing parameter acquisition on a power battery pack, measuring terminal voltage values, temperature values and charge and discharge current values of each single battery, and calculating a state-of-charge value and an internal resistance change rate of each single battery; inputting into a multi-head self-attention network for feature extraction, and generating a state correlation feature matrix; constructing an Actor network and a Critic network based on the state correlation characteristic matrix, and outputting an equalization current value, a constant-current or constant-voltage equalization mode and equalization time through the Actor network; according to the equalization current value, the equalization mode and the equalization time, the DC-DC converter in the main equalization loop is controlled to generate constant current output, or the Buck-Boost converter in the secondary equalization loop is controlled to generate constant voltage output, the equalization efficiency of the power battery pack is guaranteed, meanwhile, energy loss is reduced, and temperature self-adaptive control over the equalization circuit is achieved.

The embodiment of the invention provides a pixel circuit and a display module, and relates to the field of display panels. The pixel circuit comprises a driving module which is electrically connected with a first electrode of a light-emitting element and is used for driving the light-emitting element to emit light; the first end of the shunt branch is electrically connected with the first electrode of the light-emitting element, the second end of the shunt branch is electrically connected with a first reference voltage signal line, and the shunt branch is used for transmitting part of driving current provided by the driving module to the first reference voltage signal line. According to the pixel circuit and the display module provided by the embodiment of the invention, the problem that the display brightness of a display panel is not uniform can be fully improved, so that the display effect and the use performance of the display panel are effectively improved.

The invention relates to a reverse polarity protected electronic circuit with a negative and a positive supply voltage line and with an electrical application circuit. The electrical application circuit has a positive and a negative power supply terminal. The reverse polarity protected electronic circuit comprises a reverse polarity protection circuit (1). The reverse polarity protection circuit (1) has a first and a second N-channel enhancement transistor as part of a reverse polarity protection transistor group (17). The first and second N-channel enhancement transistors are electrically connected in anti-series via a center terminal (86) of the reverse polarity protection circuit (1). The reverse polarity protection circuit (1) includes a control device (4) which is connected to the positive and negative supply voltage lines.Only when connected with the correct polarity does the control device (4) switch the first and second N-channel enhancement transistors of the reverse polarity protection transistor group (17) on. The control device (4) includes its own additional control reverse polarity protection circuit (81) which prevents damage to the control device (4) if connected with incorrect polarity, so that the control device (4) does not switch on the first and second N-channel enhancement transistors if connected with incorrect polarity.

A parallel processing unit comprises a plurality of processors each being coupled to a memory access hardware circuitry. Each memory access hardware circuitry is configured to receive, from the coupled processor, a memory access request specifying a coordinate of a multidimensional data structure, wherein the memory access hardware circuit is one of a plurality of memory access circuitry each coupled to a respective one of the processors; and, in response to the memory access request, translate the coordinate of the multidimensional data structure into plural memory addresses for the multidimensional data structure and using the plural memory addresses, asynchronously transfer at least a portion of the multidimensional data structure for processing by at least the coupled processor. The memory locations may be in the shared memory of the coupled processor and / or an external memory.

A method of manufacturing a circuit package is described that includes connecting a photonic interposer and a second interposer, connecting a die to both the photonic interposer and the second interposer, where the die partially overlaps both the photonic interposer and the second interposer, and connecting an optical element to the photonic interposer.

The invention discloses a high-precision current detection circuit calibration system, and belongs to the technical field of current detection circuit calibration. Comprising a shunt resistor, a Hall sensor array, a chopping amplifier, a low-noise operational amplifier, a temperature sensor, an ADC acquisition unit, an RC low-pass filter, a signal conditioning unit, a main control unit, an environmental parameter adaptive compensation module and a gain adaptive adjustment module. After an original signal is obtained from a multi-channel sensor, a dynamic error model is constructed in combination with temperature data, a long-term imbalance trend is extracted by using a moving average or median filtering algorithm, and real-time compensation is performed through a pre-calibrated temperature-drift function, so that the system maintenance period is remarkably prolonged.

The invention discloses a multichannel high-precision PAF signal synchronous acquisition system and a multichannel high-precision PAF signal synchronous acquisition method, and relates to the technical field of phased array signal acquisition and processing, the multichannel high-precision PAF signal synchronous acquisition system is characterized in that a hydrogen atomic clock time-frequency distribution module is in signal connection with a plurality of signal acquisition processing boards, and each signal acquisition processing board comprises a double-loop phase determination clock circuit and an RFSoC circuit; and the double-loop phase determination clock circuit is in signal connection with the RFSoC circuit. The time-frequency distribution module adopts a time-frequency signal output by a hydrogen atomic clock as a reference, so that the synchronization precision is ensured; the clock architecture of the acquisition processing board card adopts a phase determination mode, so that a Tile clock and a PL logic clock in the board are strictly in phase with an external input reference clock, and ADC acquisition synchronization of all channels is ensured; a phase clock circuit design is determined by adopting double loops, and all output clocks and an input reference clock keep a strict phase relationship; the system adopts a three-step synchronization process, so that the synchronous acquisition of hundreds of paths of PAF signals reaches the ps-level precision.

An optical element driving mechanism is provided. The optical element driving mechanism includes a movable portion, a fixed portion, a driving assembly, and a circuit assembly. The movable portion is used for connecting to a first optical element. The movable portion is movable relative to the fixed portion. The driving assembly is used for driving the movable portion to move relative to the fixed portion. The circuit assembly is electrically connected to the driving assembly. The driving assembly is electrically connected to an external circuit through the circuit assembly.

Embodiments of an integrated circuit (IC) package including a package substrate, a first microelectronic assembly including a plurality of first IC die, each first IC die having memory circuitry and a first surface, an opposing second surface, and a third surface orthogonal to the first and second surfaces; and a second IC die having a first surface and an opposite second surface, wherein the third surfaces of the first IC die are coupled to the second surface of the second IC die, and the first surface of the second IC die is coupled to the package substrate; a third IC die having a first surface and an opposing second surface, wherein the first surface third IC die is coupled to the package substrate; and a plurality of fourth IC die, each fourth IC die including compute circuitry and electrically coupled to the second surface of the third IC die.

The invention relates to a reverse polarity protected electronic circuit with a negative and a positive supply voltage line and with an electrical application circuit. The electrical application circuit has a positive and a negative power supply terminal. The reverse polarity protected electronic circuit comprises a reverse polarity protection circuit (1). The reverse polarity protection circuit (1) has a first and a second N-channel enhancement transistor as part of a reverse polarity protection transistor group (17). The first and second N-channel enhancement transistors are electrically connected in anti-series via a center terminal (86) of the reverse polarity protection circuit (1). The reverse polarity protection circuit (1) includes a control device (4) which is connected to the positive and negative supply voltage lines.Only when connected with the correct polarity does the control device (4) switch the first and second N-channel enhancement transistors of the reverse polarity protection transistor group (17) on. The control device (4) includes its own additional control reverse polarity protection circuit (81) which prevents damage to the control device (4) if connected with incorrect polarity, so that the control device (4) does not switch on the first and second N-channel enhancement transistors if connected with incorrect polarity.

Sonde devices for providing magnetic field signals for use with utility locators or other devices are disclosed. In one embodiment a sonde device includes a housing, a core comprising a plurality of core sections, and one or more support structures, which may include windings. Circuit and / or power supply elements may be disposed fully or partially within the core to control generation of predefined magnetic field frequencies and waveforms.

The invention belongs to the technical field of circuit boards, and discloses a composite pressing process of a high multilayer rigid-flex circuit board, which comprises the following steps: performing microstructure processing on the surface of a rigid base material to form a three-dimensional reinforced interface, and performing chemical grafting modification treatment on a flexible base material to generate a multilayer pretreated substrate; identifying the positioning mark of each layer of substrate through an optical positioning system, establishing a lamination stress prediction model in combination with the thermodynamic parameters of the material, and outputting a lamination configuration scheme containing an interlayer matching relationship; placing the configured laminated structure in a multi-temperature-zone press, and executing a three-stage gradient heating and pressurizing program to realize interface fusion between adjacent layers of substrates; monitoring an interlayer deformation difference value of the substrate in real time through a sensing network, and eliminating the deformation difference to obtain a press-fit molded circuit substrate; through heterogeneous interface strengthening design, multi-physical field cooperative pressing and real-time deformation compensation, accurate interface fusion and low-warpage forming of the high-multilayer rigid-flex circuit board are realized.

The invention relates to the technical field of battery model construction, in particular to a construction method and system of a lithium ion battery equivalent circuit model and a medium. The method comprises the following steps: collecting initial battery electrochemical parameters, obtaining ion migration characteristic data through charge density gradient decoupling, further reconstructing a polarization potential field to generate a lithium ion battery charge-discharge curve, performing potential migration analysis on the curve, mapping the curve into time domain charge mapping data, and calculating the time domain charge mapping data according to the time domain charge mapping data. Voltage distribution data are captured through transient voltage, circuit topology is reconstructed, circuit temperature distribution data are obtained, electric field-temperature field cross locking is carried out to determine a temperature influence coefficient, an initial equivalent circuit model is corrected based on the temperature influence coefficient, charging and discharging simulation is carried out on the corrected model, and aging factors are embedded. And finally generating an equivalent circuit model of the lithium ion battery. The method for constructing the equivalent circuit model of the lithium ion battery is more reliable and more intelligent.

The invention discloses a circuit netlist generation method supporting deep learning model multi-stage reasoning, and belongs to the technical field of electronic circuit design and automation, and the method comprises the steps: obtaining a circuit diagram image through optical scanning, carrying out the preprocessing of the image, carrying out the recognition of a component through a deep learning model YOLOv5, and determining the boundary frame coordinates and class information. And further performing port fine identification on the component, and determining the position and the direction of the port. And eliminating character interference by using an optical character recognition technology, performing wire recognition, including Hough straight line detection and jumper processing, and determining starting point and ending point coordinates of the wire. And matching the identification results of the components, the ports and the wires, constructing a topological structure of a circuit diagram, finally generating a circuit netlist, and performing error elimination and JSON format output. According to the method, automatic netlist generation of the analog circuit diagram can be realized, the analog circuit diagram file is converted into the netlist file with device function annotations, and the efficiency and quality of circuit design and simulation are improved.

A display device includes: a display operable in a landscape mode and a portrait mode; a stand and including a power circuit configured to receive external power, a first battery, and a charging and discharging circuit configured to control charging and discharging of the first battery; and one or more processors configured to: control the charging and discharging circuit to charge the first battery using the external power, based on a user command for turning on the display being received, provide a portion of the external power to the display as first driving power, and control the charging and discharging circuit to provide another portion of the external power to the first battery as charging power, where the one or more processors are configured to provide output power of the first battery to the display as second driving power in a battery priority use mode.

The invention relates to the technical field of circuit control, in particular to a control method and system of a bidirectional charging and discharging circuit. The method comprises the following steps: collecting current monitoring data and voltage monitoring data of a bidirectional charging and discharging circuit in real time; performing arc characteristic analysis on the current monitoring data and the voltage monitoring data to obtain arc characteristic data; analyzing a high-frequency harmonic component and a current ripple fluctuation amplitude of the bidirectional charging and discharging circuit based on the arc characteristic data; performing direct-current arc detection on the bidirectional charging and discharging circuit according to the high-frequency harmonic component and the current ripple fluctuation amplitude to generate a direct-current arc fault judgment result; and calculating the instantaneous current change rate of the current monitoring data, and carrying out short-circuit detection on the bidirectional charging and discharging circuit through the instantaneous current change rate. By monitoring current and voltage data in real time, arc and short circuit characteristics are accurately analyzed, relay control is optimized, an accurate control instruction is generated, and the safety and reliability of the two-way charging and discharging circuit are improved.

A system includes a processing chamber configured to perform a plasma process with respect to one or more substrates. The system further includes an electrostatic chuck disposed within the processing chamber. The electrostatic chuck includes one or more electrodes. The system further includes an analog filter electrically coupled to at least one electrode of the one or more electrodes. The analog filter includes an air-core coil including a first coil and a second coil disposed within the first coil. The first coil and the second coil together form an inductor.

The invention relates to the technical field of molded case circuit breaker control, and discloses an intelligent molded case circuit breaker control method and system based on big data, and the method comprises the steps: collecting the operation data of a circuit breaker and the related data of a circuit system in real time through a plurality of sensors disposed on the molded case circuit breaker, and obtaining multi-source heterogeneous data; constructing a deep generative adversarial network to carry out abnormal data detection on the collected multi-source heterogeneous data, and processing to obtain preprocessed data; constructing a risk assessment model by adopting a CNN-LSTM-Transform neural network, inputting the preprocessed data into the risk assessment model, and outputting a risk assessment result; according to a risk assessment result, combining an operation environment and a load condition of a current circuit, and based on an adaptive threshold decision algorithm and fuzzy logic control, dynamically adjusting an action threshold of the circuit breaker, and formulating a corresponding control strategy; according to the invention, the control intelligence level and reliability of the circuit breaker are improved.

The invention relates to the technical field of power management, and provides a power distribution method based on BMS power control and related equipment thereof. The method comprises the following steps of: performing multi-mode synchronous acquisition and self-adaptive preprocessing on detected battery pack global state data to obtain a battery state tensor, and performing unsteady-state signal decomposition and time-space feature extraction on a received load power demand signal to obtain a power component matrix; performing multi-constraint dynamic planning on the battery state tensor and the power component matrix to obtain an initial power distribution strategy, performing dynamic correction in combination with a deep reinforcement learning model to obtain an adaptive distribution strategy, and performing multi-layer circuit equalization optimization on the adaptive distribution strategy to obtain a power regulation instruction set; and finally, performing multi-physics field coupling verification and fault-tolerant reconstruction on the power regulation instruction set to obtain an execution signal sequence. According to the invention, through data fusion, demand prediction, strategy optimization and deep learning, power distribution is accurately regulated and controlled according to the battery state and the load power demand.

Embodiments provided herein generally include apparatus, plasma processing systems and methods for tuning in a radio frequency (RF) plasma processing system for improving substrate processing metrics. Some embodiments are directed to an apparatus for processing a substrate in a plasma processing system. The apparatus generally includes: an impedance for a match circuit configured to perform impedance matching for a plasma load; a diode-based switch coupled to the impedance for the match circuit; at least one signal generator coupled to the diode-based switch and configured to bias the diode-based switch to a first position based on a first impedance generated in the plasma load; and a second position based on a second impedance generated in the plasma load and an RF signal generator configured to provide an RF signal to the plasma load.

Apparatuses and methods per row activation counter testing (PRACT). A memory includes an aggressor detector circuit, which determines a row address to be an aggressor address after the row address is accessed a number of times. In a normal mode the address is an aggressor after a first number of activations, while in a PRACT mode the address is an aggressor after a second (generally lower) number of activations. For example, when the row is accessed a first value may be added to a count in the normal mode and a second (generally larger) value in the PRACT mode. When the count crosses a threshold, the row is an aggressor.