59115 results about "Hemt circuits" patented technology

A parallel processing unit comprises a plurality of processors each being coupled to a memory access hardware circuitry. Each memory access hardware circuitry is configured to receive, from the coupled processor, a memory access request specifying a coordinate of a multidimensional data structure, wherein the memory access hardware circuit is one of a plurality of memory access circuitry each coupled to a respective one of the processors; and, in response to the memory access request, translate the coordinate of the multidimensional data structure into plural memory addresses for the multidimensional data structure and using the plural memory addresses, asynchronously transfer at least a portion of the multidimensional data structure for processing by at least the coupled processor. The memory locations may be in the shared memory of the coupled processor and / or an external memory.

The invention discloses a high-precision current detection circuit calibration system, and belongs to the technical field of current detection circuit calibration. Comprising a shunt resistor, a Hall sensor array, a chopping amplifier, a low-noise operational amplifier, a temperature sensor, an ADC acquisition unit, an RC low-pass filter, a signal conditioning unit, a main control unit, an environmental parameter adaptive compensation module and a gain adaptive adjustment module. After an original signal is obtained from a multi-channel sensor, a dynamic error model is constructed in combination with temperature data, a long-term imbalance trend is extracted by using a moving average or median filtering algorithm, and real-time compensation is performed through a pre-calibrated temperature-drift function, so that the system maintenance period is remarkably prolonged.

The invention relates to the technical field of resonance suppression, and discloses an active damping control LC resonance suppression method and device. The method comprises the following steps: performing parameter identification processing based on bus voltage to obtain an inductance value, a capacitance value and a resonance frequency of an LC circuit; extracting a resonant current component of the current signal based on the resonant frequency; calculating damping power according to the resonance current component, and converting the damping power into a voltage compensation instruction under an alpha-beta coordinate system; generating a PWM control signal according to the voltage compensation instruction and a voltage reference instruction; and performing on-off control on the inverter based on the PWM control signal, and injecting power opposite to the resonant current component into the LC circuit to generate a virtual damping effect. Virtual impedance characteristics are seamlessly integrated into inverter control, rapid response of the whole process from resonance detection to power injection is ensured, the resonance peak value is effectively suppressed, and the current quality is improved.

The invention discloses a FeFET-based XNOR calculation unit, an array and a working method of the FeFET-based XNOR calculation unit. The unit comprises a FeFET transistor F1, a FeFET transistor F2 and an NMOS transistor M0. The source electrode of the F1 is connected to a bit line BL, the source electrode of the F2 is connected to a bit line BLB, the grid electrode of the F2 and the grid electrode of the F1 are jointly connected to a word line WL, and the drain electrode of the F2 and the drain electrode of the F1 are jointly connected to a node X. The grid electrode of the M0 is connected with the node X, the drain electrode is grounded, and the source electrode is connected to the shared charge line Scl. F1 and F2 are configured to store a weight bit, and by applying a read voltage to WL and applying a voltage corresponding to an input bit to BL and BLB, a voltage level of Scl outputs an XNOR logic calculation result. The array includes a plurality of XNOR computing units arranged in m rows * n columns. WL and Scl ends of each unit are shared in each column, and BL and BLB are shared in each row. According to the invention, the control peripheral circuit of the array word line is simplified, the variability of current is effectively avoided, and the problems of hardware overhead and the like are effectively solved.

An electronic device can be validated at a circuit-level or device-level to provide supply chain verification of an integrated circuit (IC) product. A modern integrated circuit package can comprise multiple dies, systems and circuitry built from a variety of device-level structures. Device-level verification disclosed herein can confirm that a device-level (sub-) component of an integrated circuit product is sourced by a known or otherwise valid manufacturer. This serves to mitigate or avoid a hacking attempt involving illicit replacement of a component of an IC product by an intermediate handler of the IC product within a supply chain.

The application discloses a pixel driving circuit, a display panel and a display device. The pixel driving circuit comprises a first pixel driving unit, a second pixel driving unit and a third pixel driving unit. The first pixel driving unit comprises a first driving transistor and a first light emitting element. The first driving transistor has a first threshold value adjustment gate and receives a first adjustment signal. The second pixel driving unit comprises a second driving transistor and a second light emitting element. The second driving transistor has a second threshold value adjustment gate and receives a second adjustment signal. The light emitting colors of the first light emitting element and the second light emitting element are different from each other. When the first light emitting element and the second light emitting element display a target gray scale, the voltage values of the first adjustment signal and the second adjustment signal are different.

The invention discloses a high-speed multi-photon detection system and method. The system comprises a detector and a signal processing circuit, wherein the detector is composed of a window plated with a photoelectric cathode, a micro-channel plate stack and an anode; a plurality of incident photons are converted into a plurality of photoelectrons by the photoelectric cathode, and the photoelectrons are converted into electron cloud by the micro-channel plate stack; the incident electron cloud is divided into multiple paths by three layers of staggered metal strip electrodes of the anode, and charge collection is carried out to obtain charge short pulses of each layer of electrode; the signal processing circuit converts the charge short pulses transmitted by the three layers of electrodes into digital pulse signals, obtains the centroid coordinates of the electron cloud from the digital pulse signals as the abscissa value, the ordinate value and the verification value of the incident photon position, combines the abscissa value, the ordinate value and the verification value based on the screening condition to obtain the target two-dimensional coordinates, and finally obtains the target two-dimensional coordinates. And transmitting to a terminal for imaging display. According to the invention, a plurality of synchronous photons can be detected, the overall counting rate of the detector is greatly improved, and the detection efficiency is improved.

The invention discloses a digital calibration system and method for dynamic response parameters of a surge protection circuit, relates to the technical field of power electronic protection and test calibration, and is used for solving the problem that an existing surge protection circuit calibration method cannot reflect device degradation and dynamic response mismatch. Surge event voltage and current waveforms are collected through a synchronous trigger mechanism, non-stationary signal features are extracted through combined time-frequency analysis, and a voltage-current phase trajectory diagram is constructed to generate a response feature matrix; performing phase-space reconstruction on the matrix, calculating Kolmogorov entropy quantification system stability, and establishing a material degradation transfer function in combination with an energy absorption sequence to generate a grain boundary degradation index; key parameters are screened through L1 regularization regression, and a quantitative relation between a grain boundary degradation index and a protection threshold value is established to realize adaptive threshold value calculation; and executing strategy switching from calibration to predictive maintenance according to the degradation trend and threshold fluctuation change, and outputting a maintenance signal to complete dynamic accurate calibration and reliable operation of the surge protection circuit.

A multi-layer display including an upper substrate including light emitting diodes (LEDs) fabricated on a topside of the upper substrate, and LED bonding pads fabricated on a bottomside of the upper substrate. The LED bonding pads being electrically connected to the LEDs through vias extending through the upper substrate. The display also including a lower substrate including LED driver circuits and driver bonding pads fabricated on a topside of the lower substrate. The driver bonding pads being electrically connected to the LED driver circuits, where the LED bonding pads and driver bonding pads are aligned and electrically connected to each other, thereby electrically connecting the LED driver circuits to the LEDs.

The invention discloses a high-voltage circuit for an electric flame stove. The high-voltage circuit comprises a PFC circuit, a high-frequency conversion circuit, a boosting transformer, an energy coupling circuit and a voltage doubling circuit which are electrically connected in sequence. According to the EMI filter circuit, common-mode interference and differential-mode interference are filtered out, and pure alternating current input is provided for a back-end PFC circuit; two chips are adopted in the PFC circuit, so that the PFC circuit 300 finally realizes the consistency of the current waveform and the voltage phase; in the other embodiment of the invention, double chips are adopted, so that'fault linkage protection 'is realized; stable discharging of multiple groups of positive and negative electrodes is achieved through multiple groups of single energy coupling capacitors and independent voltage doubling rectifier bridges which are connected in parallel.

The invention discloses a pulse stable output control method and system for an ns-level high repetition frequency fast pulse power supply, and relates to the technical field of automatic control, the system is composed of a plurality of functional modules, and the system comprises a self-adaptive absorption module, a control module and an output control module, and the self-adaptive absorption module obtains power supply parameters through real-time sampling, and the power supply parameters comprise load impedance and switch tube parasitic parameters; dynamically optimizing R and C parameters of the RCD absorption circuit and the active clamping circuit based on power supply parameters; the feed-forward prediction module is used for extracting derivative state information according to the power supply parameters, acquiring load current feed-forward and resonant circuit states based on the derivative state information, modeling based on the load current feed-forward and resonant circuit states, and predicting the drain-source voltage valley bottom moment of the switch tube; and the multi-section variable impedance transmission module adopts a three-section variable impedance structure, performs broadband impedance matching based on R and C parameters of the optimized RCD absorption circuit and the active clamping circuit, inhibits pulse leading edge reflection distortion, and outputs undistorted pulse signals.

The invention relates to a retiming circuit applied to an ultra-high-speed and high-precision DAC (Digital-to-Analog Converter), which comprises an alignment module, a cross point adjusting module, a coding module, a phase detection module and a digital module, the coding module is connected with the alignment module, the phase detection module is connected with the cross point adjusting module and the coding module, and the digital module is connected with the phase detection module and the alignment module. According to the circuit structure provided by the invention, the sampling clock can be accurately aligned to the center of a data eye pattern, so that the delay difference between a clock tree and a data path caused by process deviation and the like is effectively reduced, the high-frequency spurious suppression performance is improved by eliminating nonlinear distortion caused by time sequence errors, the SFDR is greatly improved, and compared with a traditional scheme, the SNR is effectively improved.

The invention relates to the technical field of integrated circuits, and provides a clock domain crossing synchronization circuit and method based on a multiphase clock, and the circuit comprises a selector, an asynchronous clock synchronization module and a digital signal processor. Wherein serial data to be transmitted and a low-frequency clock are input into the selector, and the selector is used for outputting corresponding RX parallel data to the asynchronous clock synchronization module according to the serial data and the low-frequency clock; the asynchronous clock synchronization module is used for outputting corresponding alignment data to the digital signal processor according to the input RX parallel data, the clock of the digital signal processor and the low-frequency clock; the asynchronous clock synchronization module is used for performing phase alignment on the RX parallel data and a clock of the digital signal processor; and the digital signal processor is used for carrying out data processing on the alignment data. According to the invention, stable transmission of low-delay cross-clock domain data can be realized.

Luminance information and luminance change information are obtained at the same timing with high resolution. In one example, a solid-state imaging device includes pixels and a control circuit. Each of the pixels includes a photoelectric conversion element that generates an electrical signal based upon incident light, a first pixel circuit that converts the electrical signal into first information, and a second pixel circuit that converts the electrical signal into second information. The control circuit controls each of the pixels such that the photoelectric conversion element is connected to either the first pixel circuit or the second pixel circuit.

The invention relates to the technical field of circuit design, in particular to a digital circuit simulation design method and system. The method comprises the following steps: identifying a design demand document, performing deep semantic analysis and demand constraint mining, and constructing a demand specification constraint parameter set; performing demand complexity evaluation and multi-level division according to the demand specification constraint parameter set, and constructing a basic circuit architecture design blueprint; circuit routing path planning is carried out according to the basic circuit architecture design blueprint, and a standardized circuit topology network is constructed; performing electric signal propagation simulation on the standardized circuit topology network, and performing global circuit adaptability adjustment to obtain a circuit topology design scheme; and carrying out an extreme condition simulation test based on the circuit topology design scheme, and carrying out comprehensive performance evaluation to obtain a circuit performance evaluation report. By deeply understanding the user demand intention, the circuit layout matched with the user demand is designed, and the overall circuit performance is improved.

The invention discloses a broadband wave-absorbing material based on an MAX-phase metasurface structure and an impedance matching optimization method of the broadband wave-absorbing material. The wave-absorbing material comprises an MAX-phase ceramic substrate and periodic metasurface structures which are arranged on the surface of the MAX-phase ceramic substrate in an array mode and composed of conductive resonance units. The resonance units are isolated through gaps, an equivalent R1L1C1 series resonance circuit is formed in an electromagnetic field, and a base body is equivalent to a parallel resistor R2. By establishing an equivalent circuit model and optimizing parameters R1, L1, C1 and R2, impedance matching of the wave-absorbing material in a target frequency band can be regulated and controlled, so that the wave-absorbing material at least has an absorption peak of which the reflection loss is less than-10 dB. According to the optimization method, electromagnetic simulation and circuit simulation are combined, optimized circuit parameters are reversely mapped into structure geometric parameters, material preparation is guided, and accurate design and broadband absorption of the wave absorbing performance are achieved.

The invention relates to the technical field of ink-jet printing, and discloses a nozzle driving method, system and device and a storage medium, and the method comprises the steps: generating a digital waveform signal based on a printing demand, and converting the digital waveform signal into an analog voltage waveform through a digital-to-analog conversion module; performing waveform configuration on the analog voltage waveform through an analog switch matrix to generate a target analog waveform; controlling a high-voltage amplification circuit to boost and amplify the target analog waveform to output an initial driving level; driving a nozzle to jet ink droplets based on the initial driving level, and collecting ink droplet state parameters by using an ink droplet monitoring module; comparing the ink droplet state parameters with a preset target value to obtain a comparison result, and generating an adjustment parameter set according to the comparison result; optimizing the initial driving level generation process based on the adjustment parameter set to obtain an optimized driving level; according to the invention, through a closed-loop control process, the problem of poor driving signal adaptability caused by existing open-loop control is effectively solved.

The invention discloses a circuit module, an electric control heat dissipation assembly and heating and ventilation equipment, and the circuit module comprises a circuit board and a heat conduction assembly. The circuit board comprises a substrate and at least one first electronic element mounted on the substrate, the substrate comprises a first board and a second board which are oppositely arranged, and the at least one first electronic element is mounted on the first board; the heat conduction assembly is arranged on the second plate surface, the heat conduction assembly is in heat conduction contact with the second plate surface and the at least one first electronic element, and the projection of the at least one first electronic element is within the projection range of the heat conduction assembly when observed in the direction perpendicular to the plate surface. According to the technical scheme, the heat dissipation problem of the circuit module can be effectively solved, and meanwhile cost is reduced.

The invention provides a display device and a driving chip of a display panel. The display device comprises the display panel and the driving chip. The driving chip comprises a first comparator and a second comparator; the driving chip is used for dividing the output channels corresponding to the at least two data lines into a first channel with positive polarity and a second channel with negative polarity; a first comparator for comparing the first voltage with a first reference voltage to output a first level; the second comparator is used for comparing the second voltage with a second reference voltage and outputting a second level; and the driving chip is also used for continuously monitoring the first level and the second level so as to detect whether a short circuit between the data lines occurs in the display panel or not. The data line is divided into the positive and negative polarity channels through the driving chip, the comparator is used for comparing the channel voltage with the reference voltage, the level change is monitored to detect the short circuit, an amplifier and a complex switch assembly do not need to be additionally arranged, the circuit structure is simplified, and the manufacturing cost is reduced.

The invention discloses a method and system for testing a direct-current offset compensation circuit of an optical transceiving driving chip and a medium, and relates to the technical field of photoelectric integrated circuit testing, and the method comprises the following steps: carrying out the time alignment of a test waveform and an offset track of the optical transceiving driving chip, extracting the phase dislocation amount and the amplitude kick amount between beats, and carrying out the calculation of the phase offset amount and the amplitude kick amount; a continuous change result is mapped into a time sequence conflict observation band which is used for identifying a beat overlapping region; and on the basis of the phase dislocation trend of the time sequence conflict observation band, determining a beat overlapping point of the direct current offset compensation loop, and generating an overlapping beat index according to the duration of amplitude kick and the polarity direction for identifying an interference node. According to the method, millisecond-level beat observation and microsecond-level overlapping identification are realized in a test stage, interference nodes are accurately extracted, a coupling strength graph is constructed, and by combining beat rearrangement and an energy unloading strategy, nonlinear oscillation is inhibited, oscillation and overload risks are reduced, eye pattern quality and error code stability are improved, and chip test precision and robustness are enhanced.

The invention provides a device for inhibiting drain-source overvoltage and overcurrent through active gate drive of a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), aiming at solving the problem of voltage or current overshoot caused by circuit parasitic parameters in a high-speed switching process of the SiC MOSFET and simultaneously considering the switching speed and energy loss balance. According to the device, drain-source voltage vdc and direct-current bus voltage of the SiC MOSFET are collected to serve as feedback signals, and gate driving voltage and equivalent gate resistance are dynamically adjusted; in a key stage (a Miller plateau switching-on period and a voltage rising period switching-off period) of a switch transient state, a gate resistance network is switched through a logic control circuit, and suppression of drain current overshoot and drain-source voltage overshoot is realized. Simulation verification shows that the device can reduce voltage overshoot by 20%-30% and current overshoot by 25%-60%, only a single voltage feedback channel is needed, the cost is obviously lower than that of a traditional multi-signal acquisition active gate driving scheme, and the device is suitable for a high-efficiency SiC MOSFET power converter.

Various embodiments provide an antenna assembly and associated systems, devices, and methods. The antenna assembly may include two or more antennas, including a first antenna and a second antenna, coupled to a ground plane. The antenna assembly may further include an isolation network coupled to the ground plane between the first and second antennas. The isolation network may include a conductive structure between conductive antenna portions of the first and second antennas, and an isolation circuit coupled between the conductive structure and the ground plane. The isolation circuit may include a resistor, an inductor, and / or a capacitor (e.g., coupled in parallel with one another). Other embodiments may be described and claimed.

The invention discloses an early fault diagnosis method for an analog circuit based on subsequence division and Transform. According to the method, an analog circuit time domain response signal is taken as input, a multi-class fault data set constructed by combining PSpice simulation and a Monte Carlo method is divided through a sliding window to generate subsequences, and then local time sequence characteristics are extracted by using depth separable convolution and an SE module and resistance and capacitance fault sensitive frequency bands are adaptively enhanced; the method comprises the following steps: firstly, position coding is carried out on a device, then time sequence information which keeps cross-subsequence with position coding is embedded through token, a Transform encoder modeling global dependency relationship is input, meanwhile, a time sequence coupling effect generated by multi-device collaborative degradation is captured, and finally, multi-class fault diagnosis is completed through a full-connection fault diagnosis module. According to the method, weak fault features and cross-time slice long-range correlation caused by early degradation can be effectively recognized, and experimental results show that the method has high precision and good engineering application value under complex working conditions.

The invention discloses a high-voltage power amplifier with an over-temperature and over-current protection circuit, and relates to the technical field of integrated circuits. The high-voltage operational amplifier comprises a high-voltage operational amplifier core unit and a self-adaptive protection circuit unit, the high-voltage operational amplifier core unit comprises a rail-to-rail input stage, a gain amplification stage and an AB type push-pull output stage which are sequentially cascaded, and the AB type push-pull output stage comprises a PMOS upper power tube and an NMOS lower power tube; the self-adaptive protection circuit unit comprises a PMOS (P-channel Metal Oxide Semiconductor) current-limiting protection circuit, an NMOS (N-channel Metal Oxide Semiconductor) current-limiting protection circuit and an over-temperature protection circuit; the PMOS current-limiting protection circuit is used for generating a high-voltage domain over-current control signal when the power tube on the PMOS is over-current; the NMOS current-limiting protection circuit is used for generating a low-voltage domain overcurrent control signal when the NMOS lower power tube is in overcurrent; the over-temperature protection circuit is used for generating high-voltage domain over-temperature turn-off signals and low-voltage domain over-temperature turn-off signals when the amplifier is over-temperature; and finally, carrying out logic synthesis on the corresponding over-current control signal and the over-temperature turn-off signal to generate a gate clamping signal.

A power supply control device includes: an output stage circuit having a high-side transistor provided between an application terminal of an input voltage and a switch terminal, and a low-side transistor provided between the switch terminal and a ground terminal; a high-side driver; a low-side driver; a switching control circuit for controlling on / off state of the high-side and low-side transistors using the low-side and high-side drivers; a boot terminal for applying a boot voltage; a rectifying element for supplying a charging current to a boot capacitor during an on period of the low-side transistor; a reverse current detection circuit for detecting a specific reverse current state in which a reverse current flows from an output terminal to which the output voltage is applied, toward the low-side transistor via the coil and the switch terminal; and a monitor circuit for monitoring a height of the boot voltage.

The utility model relates to a radio frequency power amplification circuit with a harmonic suppression function and a radio frequency chip. The radio frequency power amplification circuit comprises an input matching unit, a first-stage power amplification unit, a first-stage bias unit, a first-stage power supply unit, an inter-stage matching unit, a second-stage power amplification unit, a second-stage bias unit, a second-stage power supply unit and an output matching unit. According to the utility model, the LC type trap circuits are designed and used in the power supply unit and the inter-stage matching unit, so that secondary, tertiary and high-order harmonic suppression is realized in the radio frequency power amplification circuit; meanwhile, based on LC circuit structures in the power supply unit and the inter-stage matching unit, the inter-stage matching bandwidth is widened, and the linearity of the multi-stage power amplification unit is improved.

A display device is provided, which includes a display panel. The display panel includes a first substrate, a second substrate, a cholesteric liquid-crystal (ChLC) layer, and a driving circuit section. A plurality of first electrodes formed on the first substrate extend in a first direction. A plurality of second electrodes formed on the second substrate extend in a second direction different from the first direction. The ChLC layer is formed between the first substrate and the second substrate. The driving circuit section is configured to apply a plurality of alternating-current (AC) voltage pulses to pixel circuits at intersections between the first electrodes and the second electrodes. The driving circuit section is further configured to perform a full screen reset procedure to the display panel followed by a pulse-width modulation (PWM) scanning procedure to control cholesteric molecules within the pixel circuits to enter a focal conic state.

The various implementations described herein include techniques and apparatuses for multi-channel biopotential signal acquisition, biopotential signal pre-processing, and adaptive signal conditioning. In one aspect, an analog frontend circuit includes an instrumentation amplifier (INA) and an analog-to-digital circuit (ADC) in a forward signal path. A digital circuit receives input from the ADC. An adaptive baseline tracking and compensation circuit tracks and compensates moving motion artifact driven changes. A power line interference (PLI) detection and compensation circuit tracks a desired number of PLI harmonics, and magnitude, phase and frequency for the PLI harmonics in real time. A digital-to-analog converter (DAC) circuit combines output of the adaptive baseline tracking and compensation circuit and the PLI detection and compensation circuit to output an analog output. A passive filter receives the analog output and drives an analog compensation signal at an input of the INA.

According to the driving control circuit for the electrostatic chuck power supply and the electrostatic chuck power supply, the driving control circuit is arranged in the electrostatic chuck power supply, a high-voltage output voltage signal of a high-voltage amplifying circuit can be obtained through a signal generating and processing feedback circuit, and according to a negative feedback adjusting mechanism, the driving control circuit is used for driving the electrostatic chuck power supply. A power supply waveform control signal for controlling a high-voltage amplification circuit to output a high-voltage output voltage signal is adjusted, and the high-voltage output voltage signal output by the high-voltage amplification circuit is adjusted to be output, so that the effect of controlling the signal precision of the high-voltage output voltage signal output by the electrostatic chuck power supply is achieved, and the output stability of the electrostatic chuck power supply is improved. Therefore, the stability of an electrostatic field generated by the electrostatic chuck is guaranteed, and the wafer fixing process precision of the electrostatic chuck is ensured.