1373 results about "Parasitic capacitance" patented technology

The invention discloses a silicon carbide TrenchMOS device and a manufacturing method thereof, and belongs to the field of semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; the arc-shaped lightly-doped N layer is additionally arranged in the middle of the arc-shaped heavily-doped N layer, electric field distribution under reverse bias is smoothed through the doping concentration lower than that of the heavily-doped N layer, the interface electric field sudden change risk is reduced, dynamic loss is reduced, meanwhile, the doping concentration of the central area is diluted through the arc-shaped inner side lightly-doped N layer, a depletion area is promoted to be expanded, and the performance of the device is improved. Electric field distribution between drain gates is optimized, and stray capacitance is reduced to improve high-frequency performance.

The utility model discloses a digital auxiliary simulation LDO circuit without an off-chip capacitor. A simulation main loop of the circuit comprises an error amplifier, a buffer stage circuit, a simulation power stage circuit and a VG voltage detection circuit. The digital auxiliary loop includes a digital control logic circuit, a ring oscillator circuit, and a digital power stage circuit. By introducing the digital power adjusting tube, the parasitic capacitance of the grid electrode of the analog power tube is reduced, the pole of the grid electrode is located at high frequency, and on the basis, the super source follower is added to push the pole to higher frequency, so that the circuit has better loop stability. In a steady state, the digital auxiliary loop is forbidden, and the analog main loop can ensure strict adjustment, low quiescent current and no switching noise at the output end; when a load current suddenly changes, a ring oscillator in the digital auxiliary loop is called to generate a clock signal, and the number of conducted digital power tubes is changed, so that response time is not limited by a clock period, dependence on an external clock is avoided, meanwhile, voltage precision and rapid transient response are guaranteed, and static power consumption of the circuit is reduced.

A nanosheet device is provided that has high quality epitaxially grown source / drain regions and reduced parasitic capacitance which are afforded by forming an air gap between an epitaxially grown source / drain region and a semiconductor substrate. The isolation provided by the air gap does not need to extend beneath the channel region of the nanosheet device.

The invention is applicable to the technical field of magnetic field measurement, and provides a current sensor magnetic field measurement method based on a tunneling magnetoresistance effect, which comprises the following steps of: analyzing a real-time output signal through a machine learning algorithm based on a mapping relation model of a parasitic capacitance parameter and a signal characteristic of a tunneling magnetoresistance sensor circuit; determining an actual value of a parasitic capacitance parameter; controlling a negative capacitance generation circuit and a numerical control resistance network to adjust an equivalent negative capacitance value and a resistance value according to the actual value of the parasitic capacitance parameter, and generating a matched compensation parameter set; feature extraction is carried out on the compensated signal, and an effective magnetic field component is obtained through multi-resolution time domain decomposition and phase consistency detection; calculating the magnetic field intensity and the change gradient based on the effective magnetic field component, and determining the effective working frequency range of the sensor according to the signal attenuation characteristic; and dynamically adjusting a compensation strategy according to a comparison result of the effective working frequency range and a preset target frequency band, and reducing measurement errors.

A high-linearity grid voltage bootstrap circuit relates to the technical field of analog-to-digital conversion and comprises a first charge pump boosting unit, a second charge pump boosting unit and a grid voltage bootstrap unit, working states of a sampling switch are divided into a sampling state and a holding state, an input voltage VIN is boosted to a VG through the grid voltage bootstrap unit in a sampling stage, and the sampling switch is switched on; and the holding stage sampling switch is cut off, and charges are injected to the upper polar plates of the capacitors C3 and C4 of the gate voltage bootstrap unit through the first charge pump boosting unit and the second charge pump boosting unit respectively. According to the invention, the problem that the actual gate-source voltage is reduced due to the grid parasitic capacitance of the sampling switch is solved, and the layout area occupation is greatly reduced while the bootstrap voltage is improved; the proportion of the capacitor C3 and the capacitor C4 can be flexibly set to obtain the required bootstrap voltage; and the problem that the on-resistance of the sampling switch is increased due to the reduction of the gate-source voltage can be solved, and the linearity of the sampling switch is improved.

Amplification circuitry is disclosed that couples neutralization transistors to amplification transistors to neutralize parasitic capacitance of the amplification transistors. Gates of a first amplification transistor and a first neutralization transistor are coupled together, and gates of a second amplification transistor and a second neutralization transistor are also coupled together. Drains of the first amplification transistor and the second neutralization transistor are coupled together, and drains of the second amplification transistor and the first neutralization transistor are also coupled together. Sources of neutralization transistors are coupled together at a node, such that a voltage swing of a first signal in the first neutralization transistor may be canceled by a voltage swing of a second signal in the second neutralization transistor. The node also couples to a resistor that prevents charge building in the neutralization transistors.

The invention discloses an automatic layout generation method based on an experience module and a related device, and relates to the technical field of computers.The method comprises the steps that a template file is extracted, an independent device is generated based on the template file, and an experience module library is constructed based on the independent device; determining coordinate mapping and size constraints of the device, and performing multi-channel chip canvas hierarchical construction based on the coordinate mapping and size constraints of the device to obtain multi-channel chip canvas hierarchical representation; based on the empirical module library and the multi-channel chip canvas hierarchical representation, a reinforcement learning model is used for layout wiring, a target layout is obtained, and the reinforcement learning model comprises a state generation model, a value network and a strategy network. Layout and wiring of devices can be controlled more accurately, stray capacitance and resistance are effectively reduced, and the performance and reliability of an analog integrated circuit are effectively improved.

The invention relates to the technical field of semiconductor testing, in particular to a radio frequency testing bonding pad and a radio frequency testing structure. The radio frequency test pad comprises a substrate; the connection supporting layer is located on the substrate, and the connection supporting layer comprises a metal layer; the connection ports are located on the connection supporting layer, and the connection ports comprise a grounding port and a signal port; the grounding port is conductively connected through the metal layer; the signal port and the metal layer are not conductive. The signal port and the metal layer are arranged to be non-conductive, so that potential difference between the signal port and a structure below is avoided, parasitic capacitance is inhibited, and the accuracy of radio frequency testing is further improved.

A semiconductor IC structure may include a first stacked transistor and a second stacked transistor. A conductive contact is at least partially between the first stacked transistor and the second stacked transistor. The conductive contact includes a deep via and an airgap spacer exists around the deep via and is in contact with respective source / drain regions and gates of the first stacked transistor and the second stacked transistor. The airgap spacer may reduce respective parasitic capacitances that exist between the conductive contact and the first and second stacked transistors. For example, the airgap spacer may relatively reduce capacitance between the deep via and the respective source / drain regions and gates of the first stacked transistor and the second stacked transistor.

A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.

The invention relates to the technical field of integrated circuit manufacturing, in particular to a wafer-level multi-chip metal wiring method and a wafer. Metal wires are arranged in a layered mode, and preset intervals are set for isolation; jumper connection between the metal wires of different metal layers is achieved through the through holes at the intersections of the scribing grooves, high-density signal transmission is achieved through the multiple layers of metal wires, and the situation that two adjacent metal wires are short-circuited together due to cutting extrusion during scribing can be prevented through cross-layer jumpers and interval isolation arrangement of the metal wires. By means of the layered metal wiring structure and spaced wiring, efficient data burning of thousands of chips on the wafer is achieved, stray capacitance and short circuit risks are remarkably reduced, meanwhile, the wafer utilization rate and burning efficiency are improved, the number and grouping mode of the chip arrays can be flexibly adjusted according to requirements, and the method is suitable for large-scale popularization and application. And the manufacturing requirements of chips with different scales are met.

A piezoelectric actuator-system includes an inductor and driver-circuit having switches for transferring energy between first and second actuators and the inductor, and between a voltage-supply node and the inductor. Control circuitry determines whether a next phase in which to operate the driver-circuit is a charging-phase or a recovery-phase. Either the charging-phase or recovery-phase may include, after a freewheeling sub-phase, a pre-charge sub-phase to place a given one of the switches connected to the first actuator near a zero-voltage switching condition. Either the charging-phase or recovery-phase may include, after a sub-phase in which a parasitic capacitance is charged, an additional recovery sub-phase in which the charge from the parasitic capacitance is recovered to the voltage-supply node.

The invention belongs to the field of module parasitic parameter reduction, and discloses a multi-loop decoupling-based low electromagnetic parasitic parameter SiC power semiconductor module, which is characterized in that an independent copper substrate is adopted as an alternating current copper layer to be laminated on a DBC (Direct Bond Copper) ceramic substrate, and a lower tube chip is flipped and then welded on the lower DBC substrate which is disconnected from a radiator; an upper tube chip and a lower tube chip are connected with a copper substrate above through a copper-molybdenum-copper cushion block, and an alternating current output end of the module is suspended above the DBC substrate through the chips and the cushion block. According to the invention, parasitic capacitance of the module AC output end to the grounding radiator can be almost completely eliminated, power-heat transfer loop capacitive decoupling is realized, common-mode current of a SiC device under high-speed switching is significantly reduced, and electromagnetic interference of a high-frequency switching circuit to a driving circuit and a control system is effectively reduced. And meanwhile, the parasitic inductance of the module is remarkably reduced, and orthogonal decoupling of a signal-power loop magnetic flux space is realized.

The invention relates to the related technical field of performance testing, in particular to a performance testing method and system based on an ultrathin touch switch color film.The method comprises the steps that electrical performance testing parameters are configured to be connected with a signal generator and an oscilloscope, touch and force data are introduced, correlation between stray capacitance disturbance signals and time frequency is analyzed, and interference intensity and time delay are determined; and associating the physical defect type mapping failure path to generate a reminding signal. The technical problems that a single-point testing means is limited in analysis capacity for stray capacitance disturbance signals and cannot accurately grasp signal interference characteristics are solved, self-adaptive configuration of electrical performance testing parameters driven by building material parameters is achieved, the testing parameters can be automatically adjusted according to different color film material characteristics, the testing accuracy and effectiveness are improved, and the testing efficiency is improved. And meanwhile, the limitation of the traditional single-point test is broken through, the signal interference characteristics are accurately quantified, the signal interference condition is deeply known, the failure mechanism analysis is combined, the fault source is quickly positioned, and the fault occurrence probability is reduced.

An optical semiconductor chip of the present disclosure includes a high frequency line between an electrode pad receiving a modulation signal and a modulation electrode on the optical waveguide having a light absorption layer. The depletion layer capacitance generated in the light absorption layer is canceled by an inductor component of the high frequency line. When a portion directly below the high frequency line is embedded with a low-dielectric-constant material or is made hollow, the parasitic capacitance is further reduced. The high frequency line may have a zigzag shape as well as a linear shape. The electrode pad on the optical semiconductor chip can be connected to other substrates including RF lines for modulation signal input by bumps or wire bonding.

A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.

A semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer, a gate electrode, a silicide barrier, a source contact plug, a drain contact plug, and a field plate plug. The gate insulating layer, disposed between the drain region and the source region, includes a first gate insulating layer having a first thickness and a second gate insulating layer having a second thickness larger than the first thickness. A bottom surface of the first gate insulating layer and a bottom surface of the second gate insulating layer are parallel to each other. The gate electrode is disposed on the first and second gate insulating layers. The silicide barrier layer is disposed in contact with a top surface of the second gate insulating layer and a top surface of the gate electrode. The source contact plug is connected to the source region.

The invention relates to the technical field of semiconductor devices, in particular to an MEMS inertial sensor and a preparation method thereof, and the sensor comprises a first supporting substrate and a first wafer which are stacked; a first groove is formed in one side, close to the first wafer, of the first supporting substrate; the first wafer comprises a fixed electrode, the projection of the fixed electrode on the first supporting substrate is located in the first groove, and a gap is formed between the bottom surface of the first groove and the fixed electrode; and a supporting column which extends along the direction vertical to the first wafer and is connected with the fixed electrode is arranged in the first groove. On the premise of ensuring sufficient mechanical support, stray capacitance between the bottom electrode and the substrate is effectively reduced so as to adapt to engineering application requirements in diversified working condition environments.

Systems and Methods for capacitance testing of a unit under test with parasitic capacitance directed to a guard rail. The system includes test points, wherein the plurality of test points are divided into at least two groups; a stimulus source; a first group guard relay electrically connected to each of the test points in a first; a second group guard relay electrically connected to each of the test points in a second; a guard rail coupled to the first group guard relay and the second group guard relay; a first group return relay electrically connected to each of the test points in a first group; a second group return relay electrically connected to each of the test points in a second group; a current measurement rail coupled to the first group return relay and the second group return relay; a current meter coupled to the measurement rail; and a controller.

The invention relates to the technical field of sensors, in particular to a passive wireless temperature sensing method for a high-temperature strong electromagnetic interference environment. Comprising the following steps that a temperature signal is collected through a sensing circuit, and the sensing circuit comprises an inductor and a capacitor; obtaining a resonance signal by utilizing magnetic coupling of a reading circuit and the sensing circuit; processing the resonance signal to obtain a temperature measurement value; the resonant frequency is dynamically corrected by considering the coupling effect of the temperature, the coil line width thermal expansion, the parasitic capacitance temperature coefficient and the working frequency; the mutual inductance coefficient is compensated by considering the cooperative influence of the magnetic conductivity, the loss angle tangent and the coupling distance; errors caused by electromagnetic interference are corrected through beat frequency characteristics of the electromagnetic interference frequency and the resonant frequency, and the multi-physical-field coupling influence under the high-temperature and strong-electromagnetic-interference environment can be dealt with.

The invention discloses a grid voltage bootstrapped switch circuit with compensation and an ADC, and belongs to the technical field of integrated circuits. The circuit comprises a compensation charge pump circuit and a grid voltage bootstrapped switch circuit. A charge pump branch power supply end in the grid voltage bootstrap switch circuit is connected to an output compensation voltage end of the compensation charge pump circuit; when the input clock signal CLK1 is low and the input clock signal CLK2 is high in level, the power supply end of the charge pump branch is switched off, and the capacitor in the charge pump circuit is compensated for charging; when the level of the CLK1 is high and the level of the CLK2 is low, the power supply end of the charge pump branch is switched on, a bootstrap capacitor in the grid voltage bootstrap switch circuit is charged, and the Vboost provides compensation voltage. The compensation charge pump circuit provides higher power supply voltage for the grid voltage bootstrap switch, grid voltage drop of the sampling switch tube caused by parasitic capacitance at the positive end of the bootstrap capacitor can be compensated back, input parasitic capacitance is reduced, on-resistance of the sampling switch tube is reduced, and sampling linearity is improved.

The invention discloses a fractional-turn winding structure applied to a boost planar transformer and a design method, and relates to a fractional-turn winding structure and a design method. The planar transformer aims to solve the problems that an existing planar transformer is large in stray capacitance and large in work loss. The fractional turn winding structure applied to the boost type planar transformer comprises three winding units, and the three winding units are sequentially arranged between a first magnetic core and a second magnetic core of the boost type planar transformer in an overlapped mode from top to bottom. The invention belongs to the technical field of power conversion.

The invention discloses a high-reliability storage unit fault-tolerant control system, which relates to the technical field of storage unit fault-tolerant control and comprises a dynamic charge mapping model module, a potential inversion driving link module, a multi-channel phase conjugate regulation and control module, a nonlinear charge turn-back channel module and a self-adaptive capacitance balance control module. And the dynamic charge mapping model module is used for constructing a dynamic charge mapping model, extracting a potential transition curve in a high-frequency read-write switching stage by taking a parasitic capacitance real-time response parameter of a parallel bit line in the storage unit as an input variable, and generating a dynamic coupling map for identifying a pseudo-synchronous charge accumulation region based on the potential transition curve. According to the invention, real-time suppression and energy balance of parasitic capacitance are realized through dynamic charge mapping and potential inversion, and potential stability of a bit line is maintained; and energy closed-loop control is realized through nonlinear charge turn-back and self-adaptive capacitance regulation and control, charge regeneration is prevented, so that the stability and the reliability of the storage unit are improved, and the service life of the storage unit is prolonged.

A semiconductor module includes first to fourth semiconductor elements, a plurality of wiring patterns, a first power source terminal, second power source terminals, a first intermediate point terminal and a second intermediate point terminal, and a full bridge circuit is formed in the semiconductor module. The semiconductor module further includes a temperature detection element; first and second temperature detection wiring patterns; and first and second temperature detection terminals. The temperature detection element is disposed in a region surrounded by a first switching path and a second switching path. The semiconductor module is configured to reduce noises caused by a parasitic capacitance between a second wiring pattern and a first temperature detection wiring pattern, and a parasitic capacitance between a fourth wiring pattern and a first temperature detection wiring pattern.

To provide a semiconductor module capable of more accurately performing a temperature detection.SOLUTION: A semiconductor module 1 includes: first to fourth semiconductor elements Q1 to Q4; a plurality of wiring patterns; a first power supply terminal 51; second power supply terminals 52 and 53; a first midpoint terminal 61; and a second midpoint terminal 62, in which a full bridge circuit is configured. The semiconductor module 1 further includes: a temperature detection element 90; first and second temperature detection wiring patterns 93 and 94; and first and second temperature detection terminals T1 and T2. The temperature detection element 90 is disposed in a region surrounded by a first switching path A and a second switching path B, and is configured to reduce noise based on a parasitic capacitance between a second wiring pattern 20 and the first temperature detection wiring pattern 93 and the parasitic capacitance between a fourth wiring pattern 40 and the first temperature detection wiring pattern 93.SELECTED DRAWING: Figure 4

An example page buffer circuit includes a plurality of page buffer circuits and a plurality of cache latches connected with the plurality of page buffer circuits through a combined sensing node. Each of the plurality of page buffer circuits includes a main latch connected with a corresponding sensing node. The main latch includes a first transistor connected with a corresponding sensing node and configured to be driven by a monitoring signal, a first latch circuit configured to latch data, and a second transistor connected with the first transistor and configured to be driven by a voltage level of a node latching data in the first latch circuit, and a parasitic capacitor corresponding to a parasitic capacitance caused by a junction of the first transistor and the second transistor is connected between the first transistor and the second transistor.

Provided is a semiconductor device that is easy to miniaturize. Provided is a semiconductor device in which parasitic capacitance is reduced. The semiconductor device includes a transistor, a first insulating layer and a second insulating layer. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a third insulating layer. The first insulating layer is over the first conductive layer and has a first opening to the first conductive layer. The second conductive layer is over the first insulating layer. The semiconductor layer is in contact with the second conductive layer, a side surface of the first insulating layer in the first opening, and a top surface of the first conductive layer. The third insulating layer is in contact with a top surface of the first insulating layer and the semiconductor layer in the first opening. The second insulating layer is over the third insulating layer and has a second opening to the third insulating layer at a position overlapping the first opening. The third conductive layer is provided so as to fill the second opening and the first opening.

The embodiment of the invention provides a fingerprint sensor device and method and electronic equipment, the fingerprint sensor device part comprises an electrode layer, stray capacitance exists between the electrode layer and a metal layer or a metal wire or an equivalent metal structure of an adjacent structure of the electrode layer, and the distance between the electrode layer and the adjacent structure is reduced when a pressing action occurs. And when the pressing action is removed, resetting is carried out. And the fingerprint sensor chip is electrically connected with the electrode layer and is used for detecting the capacitance value of the parasitic capacitor and outputting a pressure value corresponding to the pressing action according to the capacitance value. According to the embodiment of the invention, additional pressure detection hardware is not needed, and the hardware cost of pressure detection can be reduced.

Various embodiments of the present disclosure are directed towards an integrated circuit (IC) in which cavities separate wires of an interconnect structure. For example, a conductive feature overlies a substrate, and an intermetal dielectric (IMD) layer overlies the conductive feature. A first wire and a second wire neighbor in the IMD layer and respectively have a first sidewall and a second sidewall that face each other while being separated from each other by the IMD layer. Further, the first wire overlies and borders the conductive feature. A first cavity and a second cavity further separate the first and second sidewalls from each other. The first cavity separates the first sidewall from the IMD layer, and the second cavity separates the second sidewall from the IMD layer. The cavities reduce parasitic capacitance between the first and second wires and hence resistance-capacitance (RC) delay that degrades IC performance.

The invention belongs to the field of semiconductor devices, and particularly discloses a gallium arsenide-based heterojunction bipolar transistor and a preparation method thereof. The GaAs-based HBT device disclosed by the invention adopts an inverted structure, and the semiconductor substrate in the processing technology is used as a conductive N-type semiconductor layer to participate in the conduction of the device; according to the technical scheme of the invention, the parasitic capacitance between the P-type GaAs base and the N-type InGaP layer of the GaAs-based HBT device is small, the contact resistance between the topmost layer in the collector region and the electrode of the collector region can be effectively reduced, the physical isolation between the adjacent GaAs-based HBT devices can be realized by etching the mesa so as to improve the isolation effect, the heat dissipation effect of the emitter region is good, and the service life of the emitter region is prolonged. And a traditional substrate through hole process is not needed, so that the process cost is saved.