5748 results about "Parasitic capacitance" patented technology

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

The invention provides a display device in which parasitic capacitance associated with data lines and driving circuits is prevented using a bank layer whose primary purpose is to define areas on a substrate in which an organic semiconductor film is formed. When the organic semiconductor film for forming a luminescent element such as an electroluminescent element or an LED is formed is formed in pixel regions (7), the organic semiconductor film is formed in the areas surrounded by the bank layer (bank) formed of a black resist. The bank layer (bank) is also formed between an opposite electrode (op) and data lines (sig) for supplying an image signal to first TFTs (20) and holding capacitors (cap) in the pixel regions (7) thereby preventing parasitic capacitance associated with the data lines (sig).

Multi-gate NOR flash thin-film transistor (TFT) string arrays are organized as three dimensional stacks of active strips. Each active strip includes a shared source sublayer and a shared drain sublayer that is connected to substrate circuits. Data storage in the active strip is provided by charge-storage elements between the active strip and a multiplicity of control gates provided by adjacent local word-lines. The parasitic capacitance of each active strip is used to eliminate hard-wire ground connection to the shared source making it a semi-floating, or virtual source. Pre-charge voltages temporarily supplied from the substrate through a single port per active strip provide the appropriate voltages on the source and drain required during read, program, program-inhibit and erase operations. TFTs on multiple active strips can be pre-charged separately and then read, programmed or erased together in a massively parallel operation.

The present invention provides a high-k gate dielectric/metal gate MOSFET that has a reduced parasitic capacitance. The inventive structure includes at least one metal oxide semiconductor field effect transistor (MOSFET) 100 located on a surface of a semiconductor substrate 12. The least one MOSFET 100 includes a gate stack including, from bottom to top, a high-k gate dielectric 28 and a metal-containing gate conductor 30. The metal-containing gate conductor 30 has gate corners 31 located at a base segment of the metal-containing gate conductor. Moreover, the metal-containing gate conductor 30 has vertically sidewalls 102A and 102B devoid of the high-k gate dielectric 28 except at the gate corners 31. A gate dielectric 18 laterally abuts the high-k gate dielectric 28 present at the gate corners 31 and a gate spacer 36 laterally abuts the metal-containing gate conductor 30. The gate spacer 36 is located upon an upper surface of both the gate dielectric 18 and the high-k gate dielectric that is present at the gate corners 31.

Implantable medical devices (IMDS) having RF telemetry capabilities for uplink transmitting patient data and downlink receiving programming commands to and from an external programmer having an improved RF module configured to occupy small spaces within the IMD housing to further effect the miniaturization thereof. An RF module formed of an RF module substrate and at least one IC chip and discrete components has a volume and dimensions that are optimally minimized to reduce its volumetric form factor. Miniaturization techniques include: (1) integrating inductors into one or more IC chips mounted to the RF module substrate; (2) mounting each IC chip into a well of the RF module substrate and using short bonding wires to electrically connect bond pads of the RF module substrate and the IC chip; and (3) surface mounting discrete capacitors over IC chips to reduce space taken up on the RF module substrate. The integrated inductors are preferably fabricated as planar spiral wound conductive traces formed of high conductive metals to reduce trace height and width while maintaining low resistance, thereby reducing parasitic capacitances between adjacent trace side walls and with a ground plane of the IC chip. The spiral winding preferably is square or rectangular, but having truncated turns to eliminate 90° angles that cause point-to-point parasitic capacitances. The planar spiral wound conductive traces are further preferably suspended over the ground plane of the RF module substrate by micromachining underlying substrate material away to thereby reduce parasitic capacitances.

In order to charge and discharge parasitic capacitance of a source signal line sufficiently and program a predetermined current value into a pixel transistor, it is necessary to output a relatively large current from the source driver circuit.

However, if such a large current is passed through the source signal line, the value of this current is programmed into the pixel, causing a larger than desired current to flow through an EL element 15.

For example, if a 10 times larger current is used for programming, a 10 times larger current flows through the EL element 15, and thus the EL element 15 illuminates 10 times more brightly. To obtain predetermined emission brightness, the time during which the current flows through the EL element can be reduced to 1/10 of one frame (1 F). This way, the parasitic capacitance of the source signal line can be charged and discharged sufficiently and the predetermined emission brightness can be obtained.

An organic light emitting diode (OLED) display includes at least one shield electrode between a cathode layer and an OLED drive circuit. The OLED drive circuit has at least one thin-film transistor (TFT), and the shield electrode is disposed to correspond to the thin-film transistor and closer to the cathode layer, covering an entire region between the source and drain of the thin-film transistor. The shield electrode is either grounded or tied to the gate of the thin-film transistor, to thereby minimize parasitic capacitances in the pixels of the display to enhance the display performance. The presented architecture enables high density drive circuit integration in amorphous silicon or other technologies, yet preserving a high display aperture ratio.

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

An EL display apparatus according to the present invention includes EL device (15) adapted to emit light at a luminance corresponding to a current fed thereto. A source driver (14) outputs a current higher than a current corresponding to an image signal to the EL device (16) through a source signal line (18). This operation charges/discharges a parasitic capacitance present in the source signal line (18). A transistor (11d) formed between the EL device (15) and the source driver (14) operates so that the EL device (15) is fed with the current for only a part of a one-frame period. As a result, the El device (15) emits light for only the part of the period.

A pixel current driver comprises a plurality of thin film transistors (TFTs) each having dual gates and for driving OLED layers. A top gate of the dual gates is formed between a source and a drain of each of the thin film transistors, to thereby minimize parasitic capacitance. The top gate is grounded or electrically tied to a bottom gate. The plurality of thin film transistors may be two thin film transistors formed in voltage-programmed manner or five thin film transistors formed in a current-programmed ΔV_T-compensated manner. Other versions of the current-programmed circuit with different numbers of thin film transistors are also presented that compensate for δV_T. The OLED layer are continuous and vertically stacked on the plurality of thin film transistors to provide an aperture ratio close to 100%.

A solar energy plant may include a DC bus, photovoltaic panels coupled in parallel to the DC bus, each photovoltaic panel having a DC/DC converter, and a first controller controlling the DC/DC converter depending on whether a voltage on the DC bus is equal to or greater than a first threshold and lower than or equal to a second threshold. The solar energy plant may include a DC/AC inverter coupled to the DC bus and outputting an output AC voltage, an auxiliary start-up power supply charging a parasitic capacitance on the DC bus up to the first threshold, and a second controller turning on the auxiliary start-up power supply based upon a start command, and turning off the auxiliary start-up power supply and simultaneously turning on the DC/AC inverter.

It is an object to provide a semiconductor device with less power consumption as a semiconductor device including a thin film transistor using an oxide semiconductor layer. It is an object to provide a semiconductor device with high reliability as a semiconductor device including a thin film transistor using an oxide semiconductor layer. In the semiconductor device, a gate electrode layer (a gate wiring layer) intersects with a wiring layer which is electrically connected to a source electrode layer or a drain electrode layer with an insulating layer which covers the oxide semiconductor layer of the thin film transistor and a gate insulating layer interposed therebetween. Accordingly, the parasitic capacitance formed by a stacked-layer structure of the gate electrode layer, the gate insulating layer, and the source or drain electrode layer can be reduced, so that low power consumption of the semiconductor device can be realized.

A three-band antenna device with resonance generation includes a dielectric layer having an upper surface and a lower surface, a grounding element, a first radiating element, and a second radiating element. The first radiating element is arranged on the upper surface for providing a first frequency band. The second radiating element is arranged on the lower surface and stacked below the first radiating element via the dielectric layer for providing a second frequency band, so as to generate a parasitic capacitance therebetween. A third frequency band is provided by the resonance of the parasitic capacitance and the parasitic inductance in the second radiating element.

Compensation of pixels included in a touch sensor panel that generate erroneous readings (so called “negative pixels”) due to a poor grounding condition of the object touching the touch sensor panel is disclosed herein. To compensate for the erroneous readings, sense lines of the touch sensor panel can include reverse driving circuits to facilitate calculation of an object-to-ground capacitance. If the calculated object-to-ground capacitance indicates the presence of a poor grounding condition, then the object-to-ground capacitance and detected pixel touch output values are used to estimate new pixel touch output values that are used instead of the detected pixel touch output values to determine touch event(s).

An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided.

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Embodiments of the invention relate to correction of erroneous touch data on a touch sensor panel. Erroneous touch data may occur when a user is touching locations on the touch sensor panel but fails to be in good contact with another part of the device including the touch sensor panel. These erroneous readings may be statistically compensated for. A capacitance value that combines various external capacitances that may cause erroneous results can be calculated. Then, if necessary, received touch data can be modified to take into account the external capacitance. Accordingly, improved accuracy is provided for determining touch event(s) on a touch sensor panel.

The present invention discloses a testing circuit and method for thin film transistor display array, for testing the yield of thin film transistor array. The testing circuit comprising: An array tester, a test panel (DUT), a sense amplifier array. The sense amplifier is composed by a plurality of trans- impedance amplifier unit and a plurality of parasitic capacitance discharge circuit unit. Every sense amplifier includes: a trans-impedance amplifier, which is implemented by an operational amplifier, two switches and an operation capacitance, the trans-impedance amplifier is used to form an integrated circuit, the output is transmitted to a sampling/hold circuit via a switch; a parasitic capacitance discharge circuit is used to form a discharge rout for the charge of the parasitic capacitance.

An active matrix liquid crystal display having a high aperture ratio is provided. Retaining capacitors are created between a black matrix and pixel electrodes via a dielectric layer made from an organic resinous material or inorganic material. Those regions of the black matrix which cover TFTs are fully utilized. Therefore, wider area can be used to display an image than heretofore. In the present invention, the difference in relative dielectric constant between different dielectric layers is employed. Therefore, retaining capacitors can be created without the need to take account of parasitic capacitance.