801 results about "Parasitic capacitance" patented technology

A high-linearity grid voltage bootstrap circuit relates to the technical field of analog-to-digital conversion and comprises a first charge pump boosting unit, a second charge pump boosting unit and a grid voltage bootstrap unit, working states of a sampling switch are divided into a sampling state and a holding state, an input voltage VIN is boosted to a VG through the grid voltage bootstrap unit in a sampling stage, and the sampling switch is switched on; and the holding stage sampling switch is cut off, and charges are injected to the upper polar plates of the capacitors C3 and C4 of the gate voltage bootstrap unit through the first charge pump boosting unit and the second charge pump boosting unit respectively. According to the invention, the problem that the actual gate-source voltage is reduced due to the grid parasitic capacitance of the sampling switch is solved, and the layout area occupation is greatly reduced while the bootstrap voltage is improved; the proportion of the capacitor C3 and the capacitor C4 can be flexibly set to obtain the required bootstrap voltage; and the problem that the on-resistance of the sampling switch is increased due to the reduction of the gate-source voltage can be solved, and the linearity of the sampling switch is improved.

The invention discloses an automatic layout generation method based on an experience module and a related device, and relates to the technical field of computers.The method comprises the steps that a template file is extracted, an independent device is generated based on the template file, and an experience module library is constructed based on the independent device; determining coordinate mapping and size constraints of the device, and performing multi-channel chip canvas hierarchical construction based on the coordinate mapping and size constraints of the device to obtain multi-channel chip canvas hierarchical representation; based on the empirical module library and the multi-channel chip canvas hierarchical representation, a reinforcement learning model is used for layout wiring, a target layout is obtained, and the reinforcement learning model comprises a state generation model, a value network and a strategy network. Layout and wiring of devices can be controlled more accurately, stray capacitance and resistance are effectively reduced, and the performance and reliability of an analog integrated circuit are effectively improved.

A semiconductor IC structure may include a first stacked transistor and a second stacked transistor. A conductive contact is at least partially between the first stacked transistor and the second stacked transistor. The conductive contact includes a deep via and an airgap spacer exists around the deep via and is in contact with respective source / drain regions and gates of the first stacked transistor and the second stacked transistor. The airgap spacer may reduce respective parasitic capacitances that exist between the conductive contact and the first and second stacked transistors. For example, the airgap spacer may relatively reduce capacitance between the deep via and the respective source / drain regions and gates of the first stacked transistor and the second stacked transistor.

The invention relates to the technical field of semiconductor devices, in particular to an MEMS inertial sensor and a preparation method thereof, and the sensor comprises a first supporting substrate and a first wafer which are stacked; a first groove is formed in one side, close to the first wafer, of the first supporting substrate; the first wafer comprises a fixed electrode, the projection of the fixed electrode on the first supporting substrate is located in the first groove, and a gap is formed between the bottom surface of the first groove and the fixed electrode; and a supporting column which extends along the direction vertical to the first wafer and is connected with the fixed electrode is arranged in the first groove. On the premise of ensuring sufficient mechanical support, stray capacitance between the bottom electrode and the substrate is effectively reduced so as to adapt to engineering application requirements in diversified working condition environments.

Systems and Methods for capacitance testing of a unit under test with parasitic capacitance directed to a guard rail. The system includes test points, wherein the plurality of test points are divided into at least two groups; a stimulus source; a first group guard relay electrically connected to each of the test points in a first; a second group guard relay electrically connected to each of the test points in a second; a guard rail coupled to the first group guard relay and the second group guard relay; a first group return relay electrically connected to each of the test points in a first group; a second group return relay electrically connected to each of the test points in a second group; a current measurement rail coupled to the first group return relay and the second group return relay; a current meter coupled to the measurement rail; and a controller.

The invention relates to the technical field of sensors, in particular to a passive wireless temperature sensing method for a high-temperature strong electromagnetic interference environment. Comprising the following steps that a temperature signal is collected through a sensing circuit, and the sensing circuit comprises an inductor and a capacitor; obtaining a resonance signal by utilizing magnetic coupling of a reading circuit and the sensing circuit; processing the resonance signal to obtain a temperature measurement value; the resonant frequency is dynamically corrected by considering the coupling effect of the temperature, the coil line width thermal expansion, the parasitic capacitance temperature coefficient and the working frequency; the mutual inductance coefficient is compensated by considering the cooperative influence of the magnetic conductivity, the loss angle tangent and the coupling distance; errors caused by electromagnetic interference are corrected through beat frequency characteristics of the electromagnetic interference frequency and the resonant frequency, and the multi-physical-field coupling influence under the high-temperature and strong-electromagnetic-interference environment can be dealt with.

The invention discloses a high-reliability storage unit fault-tolerant control system, which relates to the technical field of storage unit fault-tolerant control and comprises a dynamic charge mapping model module, a potential inversion driving link module, a multi-channel phase conjugate regulation and control module, a nonlinear charge turn-back channel module and a self-adaptive capacitance balance control module. And the dynamic charge mapping model module is used for constructing a dynamic charge mapping model, extracting a potential transition curve in a high-frequency read-write switching stage by taking a parasitic capacitance real-time response parameter of a parallel bit line in the storage unit as an input variable, and generating a dynamic coupling map for identifying a pseudo-synchronous charge accumulation region based on the potential transition curve. According to the invention, real-time suppression and energy balance of parasitic capacitance are realized through dynamic charge mapping and potential inversion, and potential stability of a bit line is maintained; and energy closed-loop control is realized through nonlinear charge turn-back and self-adaptive capacitance regulation and control, charge regeneration is prevented, so that the stability and the reliability of the storage unit are improved, and the service life of the storage unit is prolonged.

An example page buffer circuit includes a plurality of page buffer circuits and a plurality of cache latches connected with the plurality of page buffer circuits through a combined sensing node. Each of the plurality of page buffer circuits includes a main latch connected with a corresponding sensing node. The main latch includes a first transistor connected with a corresponding sensing node and configured to be driven by a monitoring signal, a first latch circuit configured to latch data, and a second transistor connected with the first transistor and configured to be driven by a voltage level of a node latching data in the first latch circuit, and a parasitic capacitor corresponding to a parasitic capacitance caused by a junction of the first transistor and the second transistor is connected between the first transistor and the second transistor.

Various embodiments of the present disclosure are directed towards an integrated circuit (IC) in which cavities separate wires of an interconnect structure. For example, a conductive feature overlies a substrate, and an intermetal dielectric (IMD) layer overlies the conductive feature. A first wire and a second wire neighbor in the IMD layer and respectively have a first sidewall and a second sidewall that face each other while being separated from each other by the IMD layer. Further, the first wire overlies and borders the conductive feature. A first cavity and a second cavity further separate the first and second sidewalls from each other. The first cavity separates the first sidewall from the IMD layer, and the second cavity separates the second sidewall from the IMD layer. The cavities reduce parasitic capacitance between the first and second wires and hence resistance-capacitance (RC) delay that degrades IC performance.

The invention relates to the technical field of analog and digital-analog hybrid integrated circuits, and discloses a bootstrap sampling switch circuit with a pre-charging function and an analog-to-digital converter. The circuit comprises a sampling switch module and a time sequence control module. The sampling switch module sequentially works at a holding phase, a pre-charging phase and a tracking phase under the control of a multi-phase clock signal generated by the time sequence control module, the pre-charging phase is added before the tracking phase, the grid voltage of a sampling switch is pre-boosted, and the pre-charging time is dynamically controlled by using an adjustable clock circuit, so that the pre-charging time of the sampling switch is dynamically controlled. Therefore, the charge sharing effect caused by the gate parasitic capacitance is effectively suppressed. The analog-to-digital converter comprises the sampling switch circuit. The linearity and the conduction characteristic of the sampling switch are remarkably improved, and the sampling switch has excellent time sequence configurability and is suitable for a high-speed and high-precision analog-to-digital conversion system.

One or more systems, devices, and / or methods of fabrication provided herein relate to reduced parasitic capacitance of power via bars. According to one embodiment, a semiconductor device can comprise a field-effect transistor (FET), and a power via bar coupled to a backside power rail, wherein the power via bar has greater height adjacent to a source and drain region of the field-effect transistor (FET) relative to a gate of the FET to mitigates parasitic capacitance within the device.

The invention discloses a packaging structure, a packaging method and an electronic component, and relates to the technical field of semiconductors, and the packaging structure comprises a first chip, a second chip, a first electric connection part, a second electric connection part and a rewiring layer. Through the superposition cross layout of the first chip and the second chip, while the integration level is ensured, the wiring space is expanded by using the radial distribution of the non-overlapping area, and the coverage connection of the re-wiring layer is matched, so that the high-density interconnection is realized, and the parasitic inductance and parasitic capacitance are reduced; meanwhile, the signal transmission path is shortened through the combination of the cross layout and the rewiring layer, and the parasitic inductance and the parasitic capacitance are further reduced; besides, paths of different signals can be physically isolated through independent distribution of the non-overlapping areas, parasitic inductance and parasitic capacitance are further reduced, signal delay, reflection and coupling interference are reduced, and the problem of poor signal transmission performance caused by wiring limitation in traditional packaging is effectively solved.

The invention discloses a wavelength-tunable high-speed EML laser which comprises a substrate and four functional areas which are arranged on the substrate and are connected in sequence, wherein the four functional areas include an electric absorption modulation area (EAM), a gain area, a phase regulation and control area and a distributed Bragg reflection area (DBR). Wherein the P / N type electrodes of the functional areas are uniformly distributed on the same main surface of the chip to form a coplanar electrode structure; according to the laser, a coplanar P / N electrode structure is adopted, an EAM area, a gain area, a phase regulation and control area and a DBR area are integrated, the refractive indexes of the phase regulation and control area and the DBR area are jointly regulated and controlled through current injection, fast-response wide-range wavelength tuning is achieved, all the electrodes are evenly distributed on the same main surface of a chip, stray capacitance is remarkably reduced, high-frequency modulation performance is improved, and the laser is suitable for wide-range wavelength tuning. The device grows based on the semi-insulating InP substrate, so that the electrical isolation is enhanced, the transverse electric leakage and the crosstalk between the function intervals are effectively inhibited, and the integration consistency and stability are improved.

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory.SOLUTION: Thin film transistor integrated circuits such as an LSI, a CPU, and a memory are manufactured using semiconductors whose channel regions are formed using semiconductors which are intrinsic or substantially intrinsic by removal of an impurity which serves as an electronic donor (donor) and whose energy gap is larger than that of silicon semiconductors. With the use of the thin film transistor, power consumption due to leakage current can be reduced.SELECTED DRAWING: Figure 1

The invention provides a laser chip and a preparation method thereof. The laser chip comprises a light emitting region and an electric absorption modulation region. The electric absorption modulation area comprises a substrate, an active layer, a waveguide layer and a modulation electrode. The waveguide layer comprises a ridge structure, a first ridge groove and a second ridge groove, wherein the first ridge groove and the second ridge groove are located on two sides of the ridge structure. A first filling medium is arranged in the first ridge groove, and a second filling medium is arranged in the second ridge groove. The first filling medium and the second filling medium are both low-dielectric-constant media. One end of the modulation electrode is arranged on the surface of the ridge structure, and the other end is arranged on the surface of the first filling medium, namely the first filling medium is arranged between the modulation electrode and the laser chip. In the invention, when the first ridge groove and the second ridge groove are respectively filled with the low dielectric constant medium, the parasitic capacitance introduced when the modulation electrode covers along the two sides of the ridge structure can be reduced, and the dielectric loss is reduced, so that the influence of parasitic parameters on the modulation bandwidth of the laser chip is reduced, and the modulation bandwidth of the laser chip is improved.

A method and system for parasitic extraction in semiconductor layouts using spatial localization and point reduction, thereby improving efficiency of predictive models for identifying parasitic capacitance in electronic circuit design. Candidate physical layouts are generated from electrical design. Transistors and wiring are spatially modeled as three-dimensional structures. Geometrical points are identified from the three-dimensional structures being modeled and used as nodes in a neural network. A subset of the nodes is selected, and the subset is further limited to a limited region surrounding the given node to be evaluated. Nodes can have weighting based on relative geometrical position. Parasitic extraction is performed on the limited number of nodes for efficient evaluation of candidate layouts.

The embodiment of the invention provides a three-dimensional semiconductor memory which comprises a substrate, a plurality of active layers located on the substrate and arranged on the substrate in an array mode, a plurality of bit lines connected to one ends of the active layers respectively, extending in the second direction and stacked on the substrate in the third direction, and a plurality of memory units arranged on the substrate in a stacked mode. The plurality of bit lines are respectively connected to the other end of the active layer, the shielding structure comprises a main body part and a plurality of shielding parts, the shielding parts extend along the second direction, the main body part and the shielding parts are made of conductive materials, the main body part is electrically connected with the shielding parts, and at least one shielding part is arranged between adjacent bit lines along the third direction. In the embodiment of the invention, the shielding part is formed between the stacked bit lines, the shielding part is electrically connected to the main body part, and the main body part is connected to the fixed potential end, so that the electrical isolation between the stacked bit lines is realized, the parasitic capacitance between the bit lines is reduced, and the electrical performance of the stacked device is improved.

A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.

The invention discloses a trapezoidal wave current soft switching method of an interleaving DC-DC converter, which is used for a two-phase interleaving bidirectional DC-DC converter based on a coupling inductor and a multi-phase interleaving converter thereof, and is characterized in that an inductive current adopts a trapezoidal wave mode, so that the converter works in an approximate critical conduction mode; a fixed switching frequency control or hybrid control method is adopted, so that the device can work in a Buck mode and can also work in a Boost mode. The method for realizing the soft switching is characterized in that the parasitic capacitance or the external resonant capacitor of the switching tube is discharged to be zero under the resonance action of the inductor and the capacitor in the dead zone time when the upper bridge arm switch and the lower bridge arm switch are alternately switched on, so that the zero-voltage switching-on of all the switching tubes is realized. And each phase current sharing control is adopted in the multi-phase interleaving parallel topological structure. According to the invention, the problems of large current peak value and high turn-off loss of a traditional triangular wave current mode are solved, the output ripple current is reduced, a soft switching method is provided, the switching loss is reduced, and the conversion efficiency of the converter is improved.

This power conversion device is provided with: a first inverter which is connected to a power line connected to a power storage device, and which is connected to each phase of an open-winding motor; a second inverter connected to the power line and connected to each phase of the open winding motor; and a line connection switching element attached to a positive electrode side line of the power line between the first inverter and the second inverter. A switching element for line connection is configured from a semiconductor switching element having a higher parasitic capacitance than the switching elements of the first inverter and the second inverter.

The application discloses a source line abnormality detection circuit and method based on charge sharing. The circuit comprises a source drive array, a display panel, a comparator and a reference module. The application adds a reference capacitor with a capacitance not greater than the parasitic capacitance of the source line, and converts the size of the parasitic capacitance of the source line which is difficult to directly measure into a detection voltage which can be compared with a reference voltage by using the voltage division principle after charge sharing, so that the faults such as disconnection or short circuit with adjacent lines of the source line can be accurately judged. The application realizes online and non-invasive abnormality monitoring of the source line, and can effectively improve the reliability and maintainability of the display chip and the display panel.

The invention provides a high-frequency parasitic parameter extraction and electromagnetic interference source modeling method for a vehicle high-voltage high-power IGBT (Insulated Gate Bipolar Transistor) module, which comprises the following steps of: extracting parasitic capacitance to ground and lead inductance of each pole of the IGBT module by adopting a finite element method, and combining entity port impedance measurement with a simulation mode to obtain parasitic parameters among the poles of the IGBT; corresponding high-frequency equivalent circuit models are established for electromagnetic interference sources such as bridge arms, laminated busbars and cables in sequence, finally, a double-pulse simulation and entity test platform is established by integrating parasitic parameters and the models, and the accuracy of modeling of the IGBT electromagnetic interference sources can be effectively verified by comparing simulation and test results under the same working condition. And theoretical support can be provided for analysis and optimization of an electromagnetic interference mechanism of a high-voltage system of the new energy automobile.

Provided is a transistor having good electrical characteristics. Provided is a transistor having a large on-state current. Provided is a transistor having low parasitic capacitance. Provided are a transistor, a semiconductor device, or a memory device capable of achieving miniaturization or high integration. In the semiconductor device, a first conductive layer and a second conductive layer, which are located at different heights across a first insulating layer, are one or the other of a source electrode and a drain electrode of a first transistor, the first insulating layer and the second conductive layer include a first opening that reaches the first conductive layer, and a semiconductor layer is provided so as to cover the opening. The gate electrode includes a third conductive layer provided so as to cover the opening, and a fourth conductive layer laminated on the third conductive layer, the fourth conductive layer covering the upper end of the opening.

The invention relates to the technical field of intelligent kitchen appliances, in particular to a pot body material detection method, a dry-out detection method and an intelligent kitchen appliance applying the same, and the dry-out detection method comprises the following steps: determining a current equivalent voltage corresponding to an equivalent parasitic capacitance between a target pot body and a pot body material detection device; preset equivalent voltages corresponding to the pot bodies made of different materials are obtained; according to the current equivalent voltage and the preset equivalent voltage corresponding to the pot bodies made of the different materials, equivalent voltage difference values corresponding to the pot bodies made of the different materials are determined; and determining the material of the target pot body based on the equivalent voltage difference values corresponding to the pot bodies made of different materials. Therefore, more accurate detection of the material of the pot body can be realized.

The invention discloses a lap winding topological optimization method for a proportion coil of a low-temperature current comparator, and relates to the technical field of metering test instruments, and the method comprises the steps: determining the winding parameter requirements of the proportion coil based on the design structure of the low-temperature current comparator and the requirements of the system bandwidth for the resonant frequency in combination with a coil parasitic capacitance calculation formula; according to the winding parameter requirement of the proportional coil, winding the discrete coils with different turn ratios according to the consistent inner diameter and outer diameter by using an enameled wire; the wound discrete coils are fixedly combined together, and then the proportional coil is wound and wrapped with an insulating raw adhesive tape; the proportion coil is wrapped by a thin lead sheath to form an optimized proportion coil. According to the invention, the winding process difficulty and parasitic capacitance can be effectively reduced. And in terms of process difficulty, coils with various turn ratios are separately wound, and any group of coils can be directly replaced after being broken, so that the process difficulty and risk are obviously reduced.

This invention relates to the field of semiconductor technology, disclosing a semiconductor structure and its fabrication method, and a heterojunction bipolar transistor, comprising: forming a germanium-silicon layer on one side of a substrate layer, and forming a polysilicon layer on the side of the germanium-silicon layer facing away from the substrate layer; patterning the substrate layer and the germanium-silicon layer to obtain a predetermined collector region based on the substrate layer and a base region based on the germanium-silicon layer; performing ion implantation on the side of the predetermined collector region facing away from the base region to form a collector region; exposing a portion of the surface of the base region on the side of the collector region; patterning the polysilicon layer to form an emitter structure; and the width of the collector region being less than or equal to the width of the emitter structure. This invention can reduce the lateral dimensions of the device, increase integration density, reduce parasitic capacitance and resistance, and also improve the reliability of the collector region, ensuring that the doping concentration distribution of the collector region is within the target range.

The invention discloses a half-bridge module and a switching power supply circuit. The half-bridge module comprises an enhancement mode device serving as an upper tube and a depletion mode device serving as a lower tube; the source electrode of the enhancement mode device and the drain electrode of the depletion mode device are electrically connected and form a common node, and the node is used for inputting or outputting power; the drain electrode of the enhanced device is used as the high-voltage end of the half-bridge module, and the source electrode of the depletion device is used as the low-voltage end of the half-bridge module; the grid electrode of the enhancement type device is used for accessing an upper tube driving signal, the grid electrode of the depletion type device is used for accessing a lower tube driving signal, and the enhancement type device and the depletion type device are configured to be in complementary conduction. According to the half-bridge module provided by the invention, the enhanced device is naturally closed when no control signal exists, and a built-in safety characteristic is provided. The depletion type device reduces conduction loss and switching loss and improves overall efficiency due to low conduction resistance and stray capacitance of the depletion type device.

The application relates to the fields of microelectronic packaging and novel display technology, and discloses a packaging method suitable for a hybrid device packaging structure of a MicroLED, which comprises the following steps: preparing a wide-bandgap semiconductor driving chip, a logic control chip and a light-emitting pixel chip; transferring and fixing the wide-bandgap semiconductor driving chip, the logic control chip and the light-emitting pixel chip on the surface of a carrier plate in a coplanar mode; depositing a dielectric layer on the surface of the carrier plate to expose electrode contacts; manufacturing metal wires to build an internal electrical interconnection structure and lead out a peripheral interface; coating a packaging material on the surface of the carrier plate to insulate and coat the internal electrical interconnection structure; curing and cutting to separate an independent pixel packaging body; and assembling the pixel packaging body to a display panel substrate and connecting the peripheral interface to a global power supply network. The application suppresses the hot carrier effect under high-temperature working conditions, solves the problem of thermal failure, reduces the parasitic capacitance of high-frequency driving interconnection, removes potential failure products before macroscopic mounting, and improves the assembly yield of a display panel array.

A sensor system having a MEMS gyroscope is claimed, the sensor system comprising at least: - a seismic mass which can be excited to oscillate, the seismic mass having at least one electrode assembly for capacitively detecting a measurement signal, - a drive circuit for generating a drive voltage for exciting and maintaining a defined oscillatory motion of the seismic mass, wherein a parasitic capacitive coupling exists between the drive circuit and the at least one electrode assembly, - a detection circuit for reading the measurement signal and for generating a rotation rate signal on the basis of the measurement signal, characterized by circuit means for compensating for an offset of the rotation rate signal from the drive voltage.

To reduce parasitic capacitance in a semiconductor device including a transistor having an oxide semiconductor.SOLUTION: The transistor includes a first gate electrode, a first gate insulating film over the first gate electrode, an oxide semiconductor film over the first gate insulating film, a source electrode electrically connected to the oxide semiconductor film, and a drain electrode electrically connected to the oxide semiconductor film. The oxide semiconductor film includes a first oxide semiconductor film on the first gate electrode side and a second oxide semiconductor film over the first oxide semiconductor film. The first oxide semiconductor film has a higher atomic proportion of In than that of M (M is Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf), and the second oxide semiconductor film has a lower atomic proportion of In than the first oxide semiconductor film.SELECTED DRAWING: Figure 1