2005 results about "Parasitic capacitance" patented technology

To provide: a transistor with favorable electrical characteristics; a transistor with a high on-state current; a transistor with low parasitic capacitance; or a transistor, a semiconductor device, or a memory device which can be miniaturized or highly integrated.SOLUTION: There is provided a transistor including an oxide semiconductor layer, a semiconductor device, or a memory device. The oxide semiconductor layer includes a first region, a second region over the first region, and a third region over the second region. The first region is located in a range from a surface on which the oxide semiconductor layer is to be formed to greater than or equal to 0 nm to less than or equal to 3 nm in a direction substantially perpendicular to the surface. In cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright spots arranged in a layered manner in a direction parallel to the surface on which the oxide semiconductor layer is to be formed are observed in each of the first region, the second region, and the third region.SELECTED DRAWING: Figure 1

The invention discloses a silicon carbide TrenchMOS device and a manufacturing method thereof, and belongs to the field of semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; the arc-shaped lightly-doped N layer is additionally arranged in the middle of the arc-shaped heavily-doped N layer, electric field distribution under reverse bias is smoothed through the doping concentration lower than that of the heavily-doped N layer, the interface electric field sudden change risk is reduced, dynamic loss is reduced, meanwhile, the doping concentration of the central area is diluted through the arc-shaped inner side lightly-doped N layer, a depletion area is promoted to be expanded, and the performance of the device is improved. Electric field distribution between drain gates is optimized, and stray capacitance is reduced to improve high-frequency performance.

A semiconductor IC device includes an inverted gate cut region with a relatively larger bottom surface area compared to its top surface area. As a result, an associated gate structure may have a relatively larger top contact landing surface area relative to its bottom surface area. The increased landing area further enables the frontside contact to be in further perimeter locations. The inverted gate cut region also results in improved resistance characteristics through the gate structure. Specifically, the inverted gate cut region enables a wide region between a top channel and the inverted gate cut region that provides a relatively lower electrical resistance therethrough. Similarly, the inverted gate cut region causes a bottom perimeter region with decreased conductive material therein which advantageously results in lower associated parasitic capacitances.

Provided are a transistor with favorable electrical characteristics, a transistor with a high on-state current, a transistor with low parasitic capacitance, or a transistor, a semiconductor device, or a memory device which can be miniaturized or highly integrated. An oxide semiconductor layer included in the transistor, the semiconductor device, or the memory device includes a first region, a second region over the first region, and a third region over the second region. The first region is located in a range from a surface on which the oxide semiconductor layer is to be formed to greater than or equal to 0 nm to less than or equal to 3 nm in a direction substantially perpendicular to the surface. In cross-sectional observation of the oxide semiconductor layer using a transmission electron 10 microscope, bright spots arranged in a layered manner in a direction parallel to the surface are observed in each of the first region, the second region, and the third region.

A display substrate and a display apparatus. In the display substrate, the first connection structure is connected with the gate electrode of the driving transistor and a first electrode plate of the storage capacitor, both the data line and the first connection structure extend along a first direction, and the data line includes an overlapping part, the first connection structure is opposite to the overlapping part of the data line in a second direction which is parallel to the base substrate and perpendicular to the first direction; the first connection structure and the overlapping part of the data line are insulated from each other, and respectively constitute a first electrode plate and a second electrode plate of a parasitic capacitance; and a ratio of a capacitance value of the parasitic capacitance to a capacitance value of the storage capacitor is greater than 0.001 and less than 0.01.

The invention discloses a semiconductor device, relates to the technical field of semiconductors, and aims to reduce stray capacitance between gate stack structures and improve alternating current characteristics of the semiconductor device. The semiconductor device comprises a semiconductor substrate, a first gate-all-around transistor, a second gate-all-around transistor, an insulating layer, a first dielectric isolation layer and a second dielectric isolation layer. The insulating layer is disposed between the source / drain region included in the first gate-all-around transistor and the source / drain region included in the second gate-all-around transistor. And the first dielectric isolation layer and the second dielectric isolation layer are alternately stacked between a channel region included in the first gate-all-around transistor and a channel region included in the second gate-all-around transistor. A gate stack structure included in the first gate-all-around transistor and / or a gate stack structure included in the second gate-all-around transistor are located on the periphery of the first dielectric isolation layers and the second dielectric isolation layers which are alternately stacked, and film layers, located on the bottom layer and the top layer, in the first dielectric isolation layers and the second dielectric isolation layers which are alternately stacked are the first dielectric isolation layers.

The utility model discloses a digital auxiliary simulation LDO circuit without an off-chip capacitor. A simulation main loop of the circuit comprises an error amplifier, a buffer stage circuit, a simulation power stage circuit and a VG voltage detection circuit. The digital auxiliary loop includes a digital control logic circuit, a ring oscillator circuit, and a digital power stage circuit. By introducing the digital power adjusting tube, the parasitic capacitance of the grid electrode of the analog power tube is reduced, the pole of the grid electrode is located at high frequency, and on the basis, the super source follower is added to push the pole to higher frequency, so that the circuit has better loop stability. In a steady state, the digital auxiliary loop is forbidden, and the analog main loop can ensure strict adjustment, low quiescent current and no switching noise at the output end; when a load current suddenly changes, a ring oscillator in the digital auxiliary loop is called to generate a clock signal, and the number of conducted digital power tubes is changed, so that response time is not limited by a clock period, dependence on an external clock is avoided, meanwhile, voltage precision and rapid transient response are guaranteed, and static power consumption of the circuit is reduced.

A display panel comprises a virtual driving transistor, a grid electrode of the virtual driving transistor and a virtual common electrode input reference signal, the virtual common electrode is connected with a source electrode of the virtual driving transistor, and a virtual pixel electrode is electrically connected with the source electrode of the virtual driving transistor, which is equivalent to that the virtual pixel electrode accesses the reference signal. Therefore, no parasitic capacitance exists between the virtual pixel electrode and the virtual common electrode, the virtual driving transistor is opened, a reference signal is written into the suspended drain electrode of the virtual driving transistor, the drain electrode and the grid electrode of the virtual driving transistor are both reference signals, and no parasitic capacitance exists between the drain electrode and the grid electrode of the virtual driving transistor. Therefore, the display panel can effectively reduce the load of the peripheral common signal line and improve the recovery speed after the voltage of the reference signal is pulled. The invention further provides a display device comprising the display panel.

The invention discloses a display panel, a driving method and a display device. The disclosed display panel comprises a driving chip, a driving power supply and a plurality of pixel units, each pixel unit comprises a transistor and a light emitting diode; the driving chip is connected with the control end of each transistor through a scanning line or a data line, and the driving power supply is connected with each light emitting diode through each transistor; and the line width of the data line and / or the scanning line is smaller than that of the transmission line between the driving power supply and the light-emitting diode. The driving chip outputs a PWM scanning control signal to any transistor through a scanning line, or outputs a PWM data control signal to any transistor through a data line; when the transistor receives the PWM scanning control signal or the PWM data control signal, the driving power supply is connected to the light-emitting diode in the same pixel unit, so that the driving power supply drives the light-emitting diode, a large line width does not need to be designed, the stray capacitance of a wire can be reduced, and power consumption waste is avoided.

A nanosheet device is provided that has high quality epitaxially grown source / drain regions and reduced parasitic capacitance which are afforded by forming an air gap between an epitaxially grown source / drain region and a semiconductor substrate. The isolation provided by the air gap does not need to extend beneath the channel region of the nanosheet device.

The invention is applicable to the technical field of magnetic field measurement, and provides a current sensor magnetic field measurement method based on a tunneling magnetoresistance effect, which comprises the following steps of: analyzing a real-time output signal through a machine learning algorithm based on a mapping relation model of a parasitic capacitance parameter and a signal characteristic of a tunneling magnetoresistance sensor circuit; determining an actual value of a parasitic capacitance parameter; controlling a negative capacitance generation circuit and a numerical control resistance network to adjust an equivalent negative capacitance value and a resistance value according to the actual value of the parasitic capacitance parameter, and generating a matched compensation parameter set; feature extraction is carried out on the compensated signal, and an effective magnetic field component is obtained through multi-resolution time domain decomposition and phase consistency detection; calculating the magnetic field intensity and the change gradient based on the effective magnetic field component, and determining the effective working frequency range of the sensor according to the signal attenuation characteristic; and dynamically adjusting a compensation strategy according to a comparison result of the effective working frequency range and a preset target frequency band, and reducing measurement errors.

A high-linearity grid voltage bootstrap circuit relates to the technical field of analog-to-digital conversion and comprises a first charge pump boosting unit, a second charge pump boosting unit and a grid voltage bootstrap unit, working states of a sampling switch are divided into a sampling state and a holding state, an input voltage VIN is boosted to a VG through the grid voltage bootstrap unit in a sampling stage, and the sampling switch is switched on; and the holding stage sampling switch is cut off, and charges are injected to the upper polar plates of the capacitors C3 and C4 of the gate voltage bootstrap unit through the first charge pump boosting unit and the second charge pump boosting unit respectively. According to the invention, the problem that the actual gate-source voltage is reduced due to the grid parasitic capacitance of the sampling switch is solved, and the layout area occupation is greatly reduced while the bootstrap voltage is improved; the proportion of the capacitor C3 and the capacitor C4 can be flexibly set to obtain the required bootstrap voltage; and the problem that the on-resistance of the sampling switch is increased due to the reduction of the gate-source voltage can be solved, and the linearity of the sampling switch is improved.

Amplification circuitry is disclosed that couples neutralization transistors to amplification transistors to neutralize parasitic capacitance of the amplification transistors. Gates of a first amplification transistor and a first neutralization transistor are coupled together, and gates of a second amplification transistor and a second neutralization transistor are also coupled together. Drains of the first amplification transistor and the second neutralization transistor are coupled together, and drains of the second amplification transistor and the first neutralization transistor are also coupled together. Sources of neutralization transistors are coupled together at a node, such that a voltage swing of a first signal in the first neutralization transistor may be canceled by a voltage swing of a second signal in the second neutralization transistor. The node also couples to a resistor that prevents charge building in the neutralization transistors.

The invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate; the memory unit is arranged on the substrate, the memory unit comprises a transistor and a capacitor, the transistor comprises a first source / drain electrode, a grid electrode, a second source / drain electrode and a semiconductor layer surrounding the side wall of the grid electrode, the first source / drain electrode, the second source / drain electrode and the semiconductor layer are sequentially arranged in the first direction, and the first source / drain electrode and the second source / drain electrode are connected with the grid electrode through the semiconductor layer; the capacitor is arranged on one side of the second source / drain electrode and covers part of the side surface of the semiconductor layer; the bit line is arranged on one side of the first source / drain electrode and covers part of the side face of the semiconductor layer, the contact area of the bit line and the semiconductor layer is smaller than the contact area of the capacitor and the semiconductor layer, the contact area of the bit line and the transistor is reduced, and the opposite area of the bit line and the grid electrode of the transistor is reduced; therefore, the parasitic capacitance between the bit line and the grid electrode of the transistor is reduced, and the reading capability of the transistor is improved.

The invention discloses an automatic layout generation method based on an experience module and a related device, and relates to the technical field of computers.The method comprises the steps that a template file is extracted, an independent device is generated based on the template file, and an experience module library is constructed based on the independent device; determining coordinate mapping and size constraints of the device, and performing multi-channel chip canvas hierarchical construction based on the coordinate mapping and size constraints of the device to obtain multi-channel chip canvas hierarchical representation; based on the empirical module library and the multi-channel chip canvas hierarchical representation, a reinforcement learning model is used for layout wiring, a target layout is obtained, and the reinforcement learning model comprises a state generation model, a value network and a strategy network. Layout and wiring of devices can be controlled more accurately, stray capacitance and resistance are effectively reduced, and the performance and reliability of an analog integrated circuit are effectively improved.

The invention relates to the technical field of semiconductor testing, in particular to a radio frequency testing bonding pad and a radio frequency testing structure. The radio frequency test pad comprises a substrate; the connection supporting layer is located on the substrate, and the connection supporting layer comprises a metal layer; the connection ports are located on the connection supporting layer, and the connection ports comprise a grounding port and a signal port; the grounding port is conductively connected through the metal layer; the signal port and the metal layer are not conductive. The signal port and the metal layer are arranged to be non-conductive, so that potential difference between the signal port and a structure below is avoided, parasitic capacitance is inhibited, and the accuracy of radio frequency testing is further improved.

A semiconductor IC structure may include a first stacked transistor and a second stacked transistor. A conductive contact is at least partially between the first stacked transistor and the second stacked transistor. The conductive contact includes a deep via and an airgap spacer exists around the deep via and is in contact with respective source / drain regions and gates of the first stacked transistor and the second stacked transistor. The airgap spacer may reduce respective parasitic capacitances that exist between the conductive contact and the first and second stacked transistors. For example, the airgap spacer may relatively reduce capacitance between the deep via and the respective source / drain regions and gates of the first stacked transistor and the second stacked transistor.

The invention provides an EML laser and a preparation method of an air bridge, belongs to the technical field of optical communication lasers, and is used for solving the problem that the stray capacitance of connecting metal between a waveguide electrode and a PAD electrode of the EML laser is too large. The preparation method of the air bridge process of the EML comprises the following steps: growing a mask layer on the surface of an epitaxial InP wafer, photoetching to form a ridge waveguide pattern, etching the mask layer by adopting ICP (Inductively Coupled Plasma), and removing photoresist; etching the ohmic contact layer by adopting ICP (Inductively Coupled Plasma) and removing the mask layer; gluing and photoetching the surface of the wafer to form a pier pattern; adopting ICPCVD to grow a dielectric film at low temperature; gluing and photoetching the surface of the wafer to form a dielectric film bridge pattern; carrying out ICP etching on the dielectric film and removing the bridge and pier photoresist to form a dielectric film bridge; and performing wet etching on the InP epitaxial layer to the etching stop layer. According to the method, the dielectric film bridge is built at the connecting metal between the waveguide electrode and the PAD electrode, the low dielectric constant characteristic of air is utilized, the distance between the metal and the quantum well is greatly increased, the stray capacitance of the EML is reduced, and the bandwidth is improved.

A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.

The invention relates to the technical field of integrated circuit manufacturing, in particular to a wafer-level multi-chip metal wiring method and a wafer. Metal wires are arranged in a layered mode, and preset intervals are set for isolation; jumper connection between the metal wires of different metal layers is achieved through the through holes at the intersections of the scribing grooves, high-density signal transmission is achieved through the multiple layers of metal wires, and the situation that two adjacent metal wires are short-circuited together due to cutting extrusion during scribing can be prevented through cross-layer jumpers and interval isolation arrangement of the metal wires. By means of the layered metal wiring structure and spaced wiring, efficient data burning of thousands of chips on the wafer is achieved, stray capacitance and short circuit risks are remarkably reduced, meanwhile, the wafer utilization rate and burning efficiency are improved, the number and grouping mode of the chip arrays can be flexibly adjusted according to requirements, and the method is suitable for large-scale popularization and application. And the manufacturing requirements of chips with different scales are met.

A piezoelectric actuator-system includes an inductor and driver-circuit having switches for transferring energy between first and second actuators and the inductor, and between a voltage-supply node and the inductor. Control circuitry determines whether a next phase in which to operate the driver-circuit is a charging-phase or a recovery-phase. Either the charging-phase or recovery-phase may include, after a freewheeling sub-phase, a pre-charge sub-phase to place a given one of the switches connected to the first actuator near a zero-voltage switching condition. Either the charging-phase or recovery-phase may include, after a sub-phase in which a parasitic capacitance is charged, an additional recovery sub-phase in which the charge from the parasitic capacitance is recovered to the voltage-supply node.

The invention provides a power main transformer structure. The power main transformer structure comprises a magnetic core, a first framework, a second framework, a primary winding and a secondary winding. The magnetic core comprises a magnetic column, the first framework and the second framework are arranged on the magnetic column in a sleeving mode, and the first framework is arranged on the outer side of the second framework in a sleeving mode. One of the primary winding and the secondary winding is wound on the first framework, and the other one is wound on the second framework. A gap is formed between the first skeleton and the second skeleton. According to the invention, the first skeleton and the second skeleton sleeve the magnetic column and are arranged in an overlapped manner, so that it can be ensured that the transmission energy of unit turns is higher than that of non-overlapped arrangement, and meanwhile, the magnetic flux leakage is small, the precision is high, and the structure is suitable for various power levels. The first framework and the second framework are spaced, so that stray capacitance between the primary winding and the secondary winding is smaller, meanwhile, the gap is used for heat dissipation and ventilation, and the loss problem and the power density problem caused by heat dissipation can be effectively reduced.

The invention belongs to the field of module parasitic parameter reduction, and discloses a multi-loop decoupling-based low electromagnetic parasitic parameter SiC power semiconductor module, which is characterized in that an independent copper substrate is adopted as an alternating current copper layer to be laminated on a DBC (Direct Bond Copper) ceramic substrate, and a lower tube chip is flipped and then welded on the lower DBC substrate which is disconnected from a radiator; an upper tube chip and a lower tube chip are connected with a copper substrate above through a copper-molybdenum-copper cushion block, and an alternating current output end of the module is suspended above the DBC substrate through the chips and the cushion block. According to the invention, parasitic capacitance of the module AC output end to the grounding radiator can be almost completely eliminated, power-heat transfer loop capacitive decoupling is realized, common-mode current of a SiC device under high-speed switching is significantly reduced, and electromagnetic interference of a high-frequency switching circuit to a driving circuit and a control system is effectively reduced. And meanwhile, the parasitic inductance of the module is remarkably reduced, and orthogonal decoupling of a signal-power loop magnetic flux space is realized.

The invention belongs to the technical field of chip design, and particularly relates to a method for estimating interconnection line parasitic capacitance based on integrated learning in a pre-layout stage, which can improve the accuracy of dynamic power consumption calculation in the early stage of physical design. Comprising the following steps: S1, extracting original data of a circuit and calculating physical characteristics of an interconnection line; s2, establishing a feature-capacitance label supervision training data set of the interconnection line; s3, training an interconnection line parasitic capacitance prediction model; and S4, after the training stage is ended, entering a prediction stage, and taking the physical characteristics of the interconnection line in the current design pre-layout stage as the input of an interconnection line stray capacitance prediction model to obtain predicted stray capacitance. The method is simple and easy to use, the pre-layout information and the final design result have high consistency, the accuracy of circuit power consumption calculation in the early stage of physical design can be improved, and the design period is shortened.

The invention relates to the related technical field of performance testing, in particular to a performance testing method and system based on an ultrathin touch switch color film.The method comprises the steps that electrical performance testing parameters are configured to be connected with a signal generator and an oscilloscope, touch and force data are introduced, correlation between stray capacitance disturbance signals and time frequency is analyzed, and interference intensity and time delay are determined; and associating the physical defect type mapping failure path to generate a reminding signal. The technical problems that a single-point testing means is limited in analysis capacity for stray capacitance disturbance signals and cannot accurately grasp signal interference characteristics are solved, self-adaptive configuration of electrical performance testing parameters driven by building material parameters is achieved, the testing parameters can be automatically adjusted according to different color film material characteristics, the testing accuracy and effectiveness are improved, and the testing efficiency is improved. And meanwhile, the limitation of the traditional single-point test is broken through, the signal interference characteristics are accurately quantified, the signal interference condition is deeply known, the failure mechanism analysis is combined, the fault source is quickly positioned, and the fault occurrence probability is reduced.

The invention discloses an electrostatic comb tooth driving MEMS micromirror with an independent electrode structure and a manufacturing method, and belongs to the field of micro-optical electro-mechanical systems, and the electrostatic comb tooth driving MEMS micromirror comprises a mirror surface, comb tooth electrodes, a comb tooth supporting structure, a torsion beam, a bonding pad, a cavity and a fixed frame. And the driving movable comb tooth electrode and the detection movable comb tooth electrode are connected with the bonding pad through the torsion beam. According to the micro-mirror, comb electrodes are divided into detection comb electrodes and driving comb electrodes by filling isolation channels, and parasitic capacitance is reduced by removing silicon substrates at the bottoms of the comb electrodes, so that feed-through interference of driving signals on detection signals is avoided, and the capacitance detection precision of the electrostatic MEMS micro-mirror is improved. According to the back cavity etching priority sequence, the invention further discloses two manufacturing methods of the electrostatic MEMS micromirror with the independent electrode structure, and according to the manufacturing methods of the electrostatic MEMS micromirror, the isolation and interconnection of different comb teeth electrodes are realized by filling a channel, an insulating layer and a metal wire with a polymer.

An optical semiconductor chip of the present disclosure includes a high frequency line between an electrode pad receiving a modulation signal and a modulation electrode on the optical waveguide having a light absorption layer. The depletion layer capacitance generated in the light absorption layer is canceled by an inductor component of the high frequency line. When a portion directly below the high frequency line is embedded with a low-dielectric-constant material or is made hollow, the parasitic capacitance is further reduced. The high frequency line may have a zigzag shape as well as a linear shape. The electrode pad on the optical semiconductor chip can be connected to other substrates including RF lines for modulation signal input by bumps or wire bonding.

A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.

The invention belongs to the technical field of inertial sensors, and particularly discloses an MEMS accelerometer with low parasitic capacitance and a preparation method. According to the invention, the hollow area is formed at the position directly facing the back of the pickup electrode, so that the directly facing area between the pickup electrode and the upper cover silicon substrate is reduced, and the parasitic capacitance is reduced. In addition, a grounding polar plate is arranged between the pickup electrodes, so that the relative movement between the excitation electrode and the silicon substrate of the upper cover plate is shielded, and the influence of stray capacitance between the excitation electrode and the silicon substrate is further reduced. The hollow area is formed on the back of the pickup electrode of the MEMS accelerometer through the thin film supporting structure in combination with plasma dry etching, and the preparation method is simple in process, suitable for various capacitive MEMS accelerometers or gravimeters and good in compatibility and practicability.

Embodiments relate to systems and methods for compensating nonlinear distortions. The system receives a signal corresponding to an input sound pressure which is detected by a capacitive MEMS microphone. The capacitive MEMS microphone includes an active capacitance and a parasitic capacitance. The system determines a nonlinear relationship between the signal and the input sound pressure; and determines, based on the signal, an input parameter associated with the active capacitance and the parasitic capacitance. The system further determines an output signal based on the input parameter and the output signal and the input sound pressure have a linear relationship. The system compensates the signal based on the determined output signal and outputs the compensated signal as an output so that the output has the linear relationship with the input sound pressure.