1964 results about "Shift register" patented technology

The invention provides a mixed data precision matrix multiplication and addition unit and a calculation method, the matrix multiplication and addition unit comprises a calculation unit, and the calculation unit comprises a format division module, a multiplication array module, an addition tree module, an accumulator module, a normalization module and a shift register module. The calculation unit converts the first input matrix and the second input matrix into input data in a middle floating point format; executing parallel multiplication operation on the input data to generate an intermediate product result; performing index alignment and accumulation on the intermediate product result to generate an intermediate accumulated value; accumulating the intermediate product result and the value of the third input matrix in a form of accumulating an intermediate accumulated value, and outputting an accumulated result; and converting an accumulation result into a normalized result and outputting the normalized result. The format division module supports various precisions and converts data with different widths into an intermediate floating point format, so that other hardware units can be reused, and the problems that hardware resources are complex and different model reasoning scenes are difficult to meet are solved.

The invention discloses an X-waveband low-cost wave control system and method based on an FPGA, and belongs to the technical field of phased-array antennae, and the system comprises an FPGA module which is used for receiving and analyzing a control instruction from an upper computer, and executing a processing thread of a corresponding mode according to an analysis result; a FLASH module is mounted outside the FPGA module and used for achieving real-time programming curing and reconfiguration of storage parameters, the FPGA module is connected with a plurality of T / R assemblies in parallel through a plurality of data lines, the T / R assemblies on a single data line are mounted in a daisy chain mode, multi-channel data frames are sequentially sent into a first assembly shifting register in a serial mode, and the first assembly shifting register is connected with a second assembly shifting register in parallel. And the first T / R component serially outputs the data frame and transmits the data frame to the next component, and when the data frame shifts into a register of the corresponding T / R component, the data frame is read by controlling a time sequence.

The invention discloses a circuit for simultaneously switching transimpedances of multiple channels by adopting a shift register. The circuit is characterized in that an FPGA (Field Programmable Gate Array) is connected with a signal acquisition and conversion circuit module through an analog-to-digital converter and a clock generation and distribution module; the signal acquisition and conversion circuit module comprises a bias voltage setting module, a pi-type filter, a photoelectric sensor and a transimpedance amplification module which are connected in series; the input end of a transimpedance amplifier in the transimpedance amplification module is connected with a transimpedance gain access circuit, the transimpedance gain access circuit is connected with the output end of the transimpedance amplifier through an analog switch, and the control end of the analog switch is connected with the FPGA through a shifting register. According to the circuit and the method for simultaneously switching the transimpedances of the multiple channels by adopting the shift register, the transimpedance gain of the transimpedance amplifier is judged and switched according to the size of the signal, the range of the input signal is expanded, the resolution is improved, and the IO resources of the FPGA are saved and the cost is reduced by utilizing the storage function and the serial-parallel conversion function of the shift register.

A display panel includes pixel circuits, first shift register(s), second shift register(s), third shift register(s), and fourth shift register(s). A pixel circuit includes a driving transistor, a bias sub-circuit, a data writing sub-circuit, a compensation sub-circuit, a leakage prevention sub-circuit, a reset sub-circuit, and a light-emission control sub-circuit. The bias sub-circuit is electrically connected to a first shift register, which transmits a first scanning signal to the bias sub-circuit. The data writing and compensation sub-circuits are electrically connected to a second shift register, which transmits a second scanning signal to the data writing and compensation sub-circuits. The leakage prevention sub-circuit is electrically connected to a third shift register, which transmits a third scanning signal to the leakage prevention sub-circuit. The light-emission control sub-circuit is electrically connected to a fourth shift register, which transmits a fourth scanning signal to the light-emission control sub-circuit.

A shift register unit, a display driving circuit, a display panel, and a control method. The shift register unit includes: an input circuit configured to provide signals of an input signal terminal (IN) and a power signal terminal (VGH) to first and second pull-up nodes (Q1, Q2); a first control circuit configured to control potentials of the first pull-down node (QB1), and the first pull-up node (Q1); a second control circuit configured to control potentials of the second pull-up node (Q2) and the second pull-down node (QB2) based on the first pull-up node (Q1) and the first pull-down node (QB1); and an output circuit configured to provide the signal of one of the power signal terminal (VGH) and the reference signal terminal (VGL) to an output signal terminal (OUT) under control of the second pull-up node (Q2) and the second pull-down node (QB2).

A display driver circuit and a control method therefor, and a display device are disclosed. The display driver circuit includes: at least one first scan driving circuit, the at least one first scan driving circuit including: a plurality of first shift registers arranged in cascade, the first shift register including a register input terminal and a register output terminal, and the first shift registers are configured to output a plurality of scan signals; and at least one cascade control module, the at least one cascade control module being connected between a current-stage register output terminal and a next-stage register input terminal, and the at least one cascade control module being connected to a cascade control signal.

The embodiment of the invention discloses a shift register, a gate drive circuit and a display panel, and is characterized in that a node voltage control module controls the voltage of a first node and a second node according to an input signal, and a first output module outputs a first gate drive signal according to the voltage of the first node and the second node; and the second output module outputs a second gate driving signal according to the voltage of the first node and / or the second node, and the first gate driving signal is different from the second gate driving signal. Thus, two different gate driving signals can be output through the same shift register, the driving requirement for a pixel circuit can be met, the frame of the display panel can be reduced, and the user experience can be improved.

The invention discloses a shift register and a driving method thereof, a gate driving circuit and a display substrate, and the shift register comprises a cascade sub-circuit which is configured to provide a signal of a second clock signal end for a first node under the control of signals of a signal input end, a first clock signal end and the second clock signal end, a signal of a signal input end is provided for the second node, and a signal of a first power supply end or a second power supply end is provided for a cascade output signal end under the control of the signals of the first node and the second node; and the gating sub-circuit is configured to provide a signal of the first power supply end or the second power supply end to the driving output signal end under the control of signals of the masking signal end, the first control signal end, the second control signal end, the third control signal end, the first node and the second node.

Provided are a display panel, a display apparatus and a method for driving the display panel. The display panel includes: multiple gate lines; and multiple shift register units, a target shift register unit of the shift register units includes: a frame trigger selecting circuit and a gate driving circuit; the frame trigger selecting circuit is coupled to a frame trigger input terminal and frame starting signal terminals corresponding to N cascade groups, and outputs, in response to an nth turn-on signal of N turn-on signals corresponding to an nth cascade group, a starting signal input to the frame trigger input terminal to a frame starting signal terminal corresponding to the nth cascade group; 1≤n≤N, and n is an integer; the nth cascade group scans the gate lines coupled thereto line by line after the frame starting signal terminal corresponding thereto receives the starting signal.

A gate driving circuit includes a first gate driving circuit and a second gate driving circuit. The first driving circuit includes 1st to Nth first shift registers that are configured to output 1st to Nth first scan signals to N number of scan lines, respectively. The second driving circuit includes 1st to Nth second shift registers that are configured to output 1st to Nth second scan signals to the other N number of scan lines, respectively. The number of transistors in each of the 1st to Nth second shift registers is less than the number of transistors in each of the 1st to Nth first shift registers.

The present disclosure provides a gate driving circuit and a display panel. by the control of one of the fourth node, the output end of the second output module, and the first node of the shift register of the next stage, the voltage regulating module may utilize a low voltage signal to stabilize or reduce the gate voltage of the second transistor, so that the second transistor is stable or preferably in the cut-off state to reduce the leakage current. In this way, voltage level of the second gate driving signal can be maintained at a high voltage level or a pulse amplitude.

The invention provides a driving chip, a display module and a display device. The display module comprises a display panel, a first gate drive circuit and a drive chip. The first gate drive circuit comprises a plurality of first shift registers which are arranged in a cascade mode, and the signal output end of each first shift register is electrically connected with the reset control end of at least one reset sub-circuit in the pixel circuit. The driving chip is configured to input a first clock signal to a clock signal end of the first gate driving circuit in a refresh frame stage; in the holding frame stage, a second clock signal is input to the clock signal end of the first gate drive circuit, and the frequency of the second clock signal is smaller than that of the first clock signal.

Provided are a display panel and a display device. The display panel includes a first driver circuit and a pixel circuit. The first driver circuit is configured to provide a first drive signal for the pixel circuit, where the first drive signal includes a first sub-drive signal and a second sub-drive signal. The first driver circuit includes a first driving portion and a second driving portion. The first driving portion includes the K-th stage to the L-th stage of shift registers and is configured to output the first sub-drive signal, and the second driving portion includes the M-th stage to the N-th stage of shift registers and is configured to output the second sub-drive signal. The pulse change frequency of the first sub-drive signal is F1, and the pulse change frequency of the second sub-drive signal is F2, where F1≠F2.

The invention relates to a digital mutual inductor signal decoding method and device based on an FPGA, and the method comprises the steps: receiving a serial Manchester data signal at a rising edge of each clock period through a receiving module according to a reference clock which is 16 times higher than the Manchester signal frequency, detecting a correct rising edge, starting a synchronous clock, and carrying out the decoding of the Manchester data signal. The method comprises the following steps of: generating a central sample to extract effective data according to 1 / 4 and 3 / 4 positions of each bit period of a data cell, converting the extracted effective data into an NRZ code according to a Manchester encoding rule, and storing the decoded NRZ code into a shift register. According to the invention, high efficiency of a decoding process and flexibility of system operation can be realized. According to the design, the parallel processing capacity of the FPGA and the control advantages of the processor are fully combined, and it is ensured that information of the system flows rapidly and reliably.

The invention relates to the technical field of intelligent control, and discloses an intelligent control method for an etching process of a PCB (Printed Circuit Board), which comprises the following steps of: acquiring an image of an object to be processed, generating a discretized virtual load sequence, establishing a virtual shift register synchronized with a feedback pulse trigger clock of a transmission device encoder, driving the virtual load sequence to execute logic displacement of physical displacement phase locking; comparing the theoretical torque with the actual torque to obtain a torque residual error; a dynamic gain correction coefficient is calculated based on the torque residual error, the basic feed-forward gain is weighted and modulated in real time, and a control instruction is generated, and a time sequence error caused by transmission speed fluctuation is avoided by constructing a rigid space-time synchronization architecture based on a virtual shift register; a torque residual error is used as a non-intrusive observation variable, and a gain scheduling mechanism is combined, so that self-adaptive compensation for impedance drift of a controlled medium under the condition of no physical sensor is realized.

The present disclosure relates to the technical field of display. Provided are a shift register unit, a gate driving circuit, a display panel and a driving method therefor. The shift register unit is applied to a gate driving circuit in a display panel, the gate driving circuit comprising a plurality of cascaded shift register units, and the display panel comprising a pixel driving circuit. The shift register unit comprises: a first output circuit and a second output circuit, the first output circuit being used for providing in a first driving state a gate driving signal to the pixel driving circuit and used for providing in a second driving state an invalid level signal to the pixel driving circuit, and the second output circuit being used for providing an input signal to a lower-level shift register unit. The display panel using the shift register unit can realize adjustment of the local refresh rate. (figure 2)

An apparatus that includes a shift register unit, a gate driving circuit, and a display apparatus. The shift register unit includes: an input circuit, a reset circuit, a node control circuit, a cascade output circuit and a drive output circuit, where the drive output circuit is configured to provide the signal of the clock signal end to a drive output end in response to the signals of the first node.

The invention discloses a flow-based local message classification method and device, and relates to the field of message classification, and the method comprises the steps: carrying out the parallel comparison of a keyword of a to-be-classified message with a keyword temporarily stored in a shift register, obtaining a comparison result, and generating an index matching result through an arbiter according to the comparison result; according to the locality principle of a message flow, historically queried table item information is cached into a dynamic cache table, an arbiter arbitrates a comparison result of a shift register, calculates an offset address of the dynamic cache table and obtains a matching result, and whether an original rule table needs to be queried and whether a dynamic cache table memory needs to be updated are determined according to a search result. Under the condition that the matching is unsuccessful, the dynamic cache table memory can guide the same message to directly use the offset address to obtain the table item information in the next search without searching from an original rule table, so that the hit rate is increased, the matching efficiency is improved, and the storage resources are saved.

The invention discloses a display panel and a display device, and the display panel comprises a first region which comprises a plurality of rows of pixel circuits; the second area comprises a first start control line, a first driving circuit and a plurality of clock signal lines, the first start control line is electrically connected with the first driving circuit, and the first driving circuit comprises multiple stages of shift register units; in the shift register unit, a plurality of clock ends are electrically connected with a plurality of clock signal lines respectively, and N shift output ends are electrically connected with adjacent N rows of pixel circuits respectively; in a first working mode, a plurality of clock ends in the shift register unit receive different clock signals, so that N shift output ends output gate driving signals in a time-sharing manner; and in the second working mode, two clock ends in the shift register unit receive the same clock signal, so that the N shift output ends simultaneously output gate driving signals. In the invention, the display panel adopts the second working mode, so that the charging time of each row of pixel circuits can be prolonged, or the refresh rate can be improved.

A shift register unit includes a driving control module configured to receive an input signal and control a signal of a first output node and a signal of a second output node, a stage transfer module configured to receive a signal of a first output node and a signal of a second output node and control a stage transfer signal, a transmission control module configured to receive a stage transfer signal and a transmission control signal and control a signal of a third output node, an auxiliary control module configured to receive a signal of a second output node, a signal of a third output node and an auxiliary control signal and control a signal of a fourth output node, and a scanning module configured to receive at least a signal of a third output node and a signal of a fourth output node and control a scanning signal.

The invention discloses a scanning driving circuit and a display panel. The scanning driving circuit comprises a plurality of cascaded shifting registers, each shifting register comprises a gating module and a shifting module, the first input end of each gating module is used for accessing a first trigger signal, the first input end of the gating module in the first-stage shifting register is electrically connected with a first trigger signal line, and the second input end of the gating module in the second-stage shifting register is electrically connected with a second trigger signal line; the first input end of the gating module in the (i + 1) th stage of shifting register is electrically connected with the output end of the shifting module in the ith stage of shifting register, i is an integer greater than 0, the second input end of the gating module is electrically connected with a second trigger signal line, and the second trigger signal line is used for transmitting a second trigger signal; the gating module is used for outputting an enabling level of at least one of the first trigger signal and the second trigger signal to the shifting module; the shifting module is used for outputting a signal including an enable level in response to the enable signal output by the gating module. According to the embodiment of the invention, the scanning driving circuit can output scanning signals with different refresh frequencies.

The present disclosure relates to the technical field of display, and provides a shift register, a gate drive circuit, a display panel, and a display device. In the shift register, a first display input circuit is configured to write a signal of a first signal end into a first pull-up node under the control of a signal of a first display input end; a first display shift circuit is configured to write a signal of a first shift signal end into a first shift output end under the control of a signal of the first pull-up node; a black frame insertion input circuit is configured to write a signal of a second voltage end into the first pull-up node under the control of signals of a first black frame insertion input end, a first control end, and a second control end; a first black frame insertion shift circuit is configured to write a signal of a second shift signal end into a second shift output end under the control of the signal of the first pull-up node; and a first output circuit is configured to write the signal of the first signal end into a first output end under the control of the signal of the first pull-up node.

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

The embodiment of the invention provides a display panel and a display device. The display panel comprises a plurality of cascaded shift register units, and each shift register unit comprises an input module, a level transfer module, an output module and a control module. The level transmission module comprises a first control end and is configured to output a low-level signal based on a signal of the first control end and a first clock signal; the output module comprises a second control end, the output module is configured to output a high-level signal based on a signal of the second control end and a second clock signal, and the first clock signal and the second clock signal are phase inversion signals; one control end of the control module and one output end of the input module are connected to a first node, one of the first control end and the second control end is connected with the output end of the control module, and the other one is connected with the first node. According to the shift driving circuit, the mutual influence between the first clock signal and the second clock signal can be isolated, so that the stage transmission module outputs a stable waveform, and the performance reliability of the shift driving circuit is improved.

A capacitance measurement circuit includes an analog front-end (AFE) circuit with current mirror circuits, a parasitic capacitor, an AD converter, an output shift register, and a controller. The controller disconnects a capacitor to be measured and connects one current mirror circuit to record an AFE output voltage VN collected at an inverting input terminal of the AD converter, then connects the capacitor to be measured to collect an AFE output voltage VP at a non-inverting input terminal of the AD converter, and converts a value of (VP−VN) into a first digital signal; determines, based on the value of the first digital signal, a connection number m of the current mirror circuits, controls the analog front-end circuit to connect m current mirror circuits, and repeat the steps to obtain a second digital signal; and shift the second digital signal based on the connection number m to obtain a capacitance measurement value.

A shift register is provided to include a voltage control circuit coupled to an output control node; at least one driving output circuit, each including an output transistor and a capacitor structure sequentially arranged along a first direction; a first conductive line therebetween and extending along a second direction and coupled to a signal output line configured for the driving output circuit; the output transistor includes a gate electrode coupled to the output control node and a first voltage writing electrode of the capacitor structure, a first electrode coupled to a clock signal line configured for the driving output circuit and a second electrode coupled to the first conductive line; a second conductive line is disposed between the first conductive line and the capacitor structure, and the first conductive line is coupled to a second voltage writing electrode of the capacitor structure through the second conductive line.

The invention provides a shift register, a driving circuit, a display device and a driving method, and relates to the technical field of display. The shift register comprises a shift circuit configured to shift a first clock signal from a first clock end, a second clock signal from a second clock end, a first power supply voltage of a first power supply, a second power supply voltage of a second power supply and a first input signal from a first input end under the control of the first clock signal from the first clock end, the second clock signal from the second clock end, the first power supply voltage and the second power supply voltage; controlling the potentials of the first node and the second node; the gating circuit is configured to provide a first gating signal from a first gating end to a third node under the control of a gating input signal from a gating input end; the control circuit is configured to provide the potential of the first node to a fourth node under the control of the potential of the third node; and the output circuit is configured to provide the first power supply voltage or the second power supply voltage to the first output end as a first output signal under the control of the potential of the fourth node and the potential of the second node.

The invention provides a shift register, a gate drive circuit and a display device, relates to the technical field of display, and is used for narrowing the frame width of a display product better. The shift register comprises an output circuit, the output circuit comprises a first output transistor, the first output transistor comprises a double-gate transistor, a top gate of the first output transistor is coupled with a cascade signal output end, a bottom gate of the first output transistor is coupled with a regulation and control end, and the double-gate transistor comprises a double-gate transistor. A first electrode of the first output transistor is coupled with a first level signal input end, and a second electrode of the first output transistor is coupled with a gate driving signal output end; the cascade signal output end is used for controlling the first output transistor to be switched on or switched off, and the regulation and control end is used for controlling characteristic parameters of the first output transistor.

The present application discloses a display driving circuit and a display device. The display driving circuit includes: a first scan driving circuit, including: a plurality of first shift registers arranged in cascade, and at least one first cascade control module. The first shift register includes a first register input terminal and a first register output terminal. The first cascade control module includes a first cascade control unit and a signal transfer unit, where the first cascade control unit is configured to control a connection state between a current-stage first register output terminal and a next-stage first register input terminal. An output terminal of the signal transfer unit is electrically connected to a next-stage first register input terminal; and the signal transfer unit is configured to transmit a start control signal to the next-stage first register input terminal in response to a transfer control signal.

According to the display panel, one end of a connecting wire is electrically connected with a shifting register, the other end of the connecting wire is electrically connected with a connecting terminal, and an electrostatic discharge wire is electrically connected with a constant-voltage signal wire; the film layer where the electrostatic discharge wires are located is located below the film layer where the connecting wires are located. In a top view of the display panel, at least part of the electrostatic discharge wire is overlapped with part of the connecting wire; on one hand, the electrostatic discharge wires can form a barrier electric field on the back side of the display panel to prevent static electricity from entering from the back side of the display panel, and on the other hand, the electrostatic discharge wires can guide away the static electricity introduced from the back side of the display panel, so that the static electricity is prevented from exploding and damaging the connecting wires, and the display performance of the display panel is prevented from being reduced.