1579 results about "Shift register" patented technology

The invention provides a mixed data precision matrix multiplication and addition unit and a calculation method, the matrix multiplication and addition unit comprises a calculation unit, and the calculation unit comprises a format division module, a multiplication array module, an addition tree module, an accumulator module, a normalization module and a shift register module. The calculation unit converts the first input matrix and the second input matrix into input data in a middle floating point format; executing parallel multiplication operation on the input data to generate an intermediate product result; performing index alignment and accumulation on the intermediate product result to generate an intermediate accumulated value; accumulating the intermediate product result and the value of the third input matrix in a form of accumulating an intermediate accumulated value, and outputting an accumulated result; and converting an accumulation result into a normalized result and outputting the normalized result. The format division module supports various precisions and converts data with different widths into an intermediate floating point format, so that other hardware units can be reused, and the problems that hardware resources are complex and different model reasoning scenes are difficult to meet are solved.

A display driver circuit and a control method therefor, and a display device are disclosed. The display driver circuit includes: at least one first scan driving circuit, the at least one first scan driving circuit including: a plurality of first shift registers arranged in cascade, the first shift register including a register input terminal and a register output terminal, and the first shift registers are configured to output a plurality of scan signals; and at least one cascade control module, the at least one cascade control module being connected between a current-stage register output terminal and a next-stage register input terminal, and the at least one cascade control module being connected to a cascade control signal.

A gate driving circuit includes a first gate driving circuit and a second gate driving circuit. The first driving circuit includes 1st to Nth first shift registers that are configured to output 1st to Nth first scan signals to N number of scan lines, respectively. The second driving circuit includes 1st to Nth second shift registers that are configured to output 1st to Nth second scan signals to the other N number of scan lines, respectively. The number of transistors in each of the 1st to Nth second shift registers is less than the number of transistors in each of the 1st to Nth first shift registers.

The present disclosure provides a gate driving circuit and a display panel. by the control of one of the fourth node, the output end of the second output module, and the first node of the shift register of the next stage, the voltage regulating module may utilize a low voltage signal to stabilize or reduce the gate voltage of the second transistor, so that the second transistor is stable or preferably in the cut-off state to reduce the leakage current. In this way, voltage level of the second gate driving signal can be maintained at a high voltage level or a pulse amplitude.

The invention relates to the technical field of intelligent control, and discloses an intelligent control method for an etching process of a PCB (Printed Circuit Board), which comprises the following steps of: acquiring an image of an object to be processed, generating a discretized virtual load sequence, establishing a virtual shift register synchronized with a feedback pulse trigger clock of a transmission device encoder, driving the virtual load sequence to execute logic displacement of physical displacement phase locking; comparing the theoretical torque with the actual torque to obtain a torque residual error; a dynamic gain correction coefficient is calculated based on the torque residual error, the basic feed-forward gain is weighted and modulated in real time, and a control instruction is generated, and a time sequence error caused by transmission speed fluctuation is avoided by constructing a rigid space-time synchronization architecture based on a virtual shift register; a torque residual error is used as a non-intrusive observation variable, and a gain scheduling mechanism is combined, so that self-adaptive compensation for impedance drift of a controlled medium under the condition of no physical sensor is realized.

The present disclosure relates to the technical field of display. Provided are a shift register unit, a gate driving circuit, a display panel and a driving method therefor. The shift register unit is applied to a gate driving circuit in a display panel, the gate driving circuit comprising a plurality of cascaded shift register units, and the display panel comprising a pixel driving circuit. The shift register unit comprises: a first output circuit and a second output circuit, the first output circuit being used for providing in a first driving state a gate driving signal to the pixel driving circuit and used for providing in a second driving state an invalid level signal to the pixel driving circuit, and the second output circuit being used for providing an input signal to a lower-level shift register unit. The display panel using the shift register unit can realize adjustment of the local refresh rate. (figure 2)

An apparatus that includes a shift register unit, a gate driving circuit, and a display apparatus. The shift register unit includes: an input circuit, a reset circuit, a node control circuit, a cascade output circuit and a drive output circuit, where the drive output circuit is configured to provide the signal of the clock signal end to a drive output end in response to the signals of the first node.

A shift register unit includes a driving control module configured to receive an input signal and control a signal of a first output node and a signal of a second output node, a stage transfer module configured to receive a signal of a first output node and a signal of a second output node and control a stage transfer signal, a transmission control module configured to receive a stage transfer signal and a transmission control signal and control a signal of a third output node, an auxiliary control module configured to receive a signal of a second output node, a signal of a third output node and an auxiliary control signal and control a signal of a fourth output node, and a scanning module configured to receive at least a signal of a third output node and a signal of a fourth output node and control a scanning signal.

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

A capacitance measurement circuit includes an analog front-end (AFE) circuit with current mirror circuits, a parasitic capacitor, an AD converter, an output shift register, and a controller. The controller disconnects a capacitor to be measured and connects one current mirror circuit to record an AFE output voltage VN collected at an inverting input terminal of the AD converter, then connects the capacitor to be measured to collect an AFE output voltage VP at a non-inverting input terminal of the AD converter, and converts a value of (VP−VN) into a first digital signal; determines, based on the value of the first digital signal, a connection number m of the current mirror circuits, controls the analog front-end circuit to connect m current mirror circuits, and repeat the steps to obtain a second digital signal; and shift the second digital signal based on the connection number m to obtain a capacitance measurement value.

The present application discloses a display driving circuit and a display device. The display driving circuit includes: a first scan driving circuit, including: a plurality of first shift registers arranged in cascade, and at least one first cascade control module. The first shift register includes a first register input terminal and a first register output terminal. The first cascade control module includes a first cascade control unit and a signal transfer unit, where the first cascade control unit is configured to control a connection state between a current-stage first register output terminal and a next-stage first register input terminal. An output terminal of the signal transfer unit is electrically connected to a next-stage first register input terminal; and the signal transfer unit is configured to transmit a start control signal to the next-stage first register input terminal in response to a transfer control signal.

According to the display panel, one end of a connecting wire is electrically connected with a shifting register, the other end of the connecting wire is electrically connected with a connecting terminal, and an electrostatic discharge wire is electrically connected with a constant-voltage signal wire; the film layer where the electrostatic discharge wires are located is located below the film layer where the connecting wires are located. In a top view of the display panel, at least part of the electrostatic discharge wire is overlapped with part of the connecting wire; on one hand, the electrostatic discharge wires can form a barrier electric field on the back side of the display panel to prevent static electricity from entering from the back side of the display panel, and on the other hand, the electrostatic discharge wires can guide away the static electricity introduced from the back side of the display panel, so that the static electricity is prevented from exploding and damaging the connecting wires, and the display performance of the display panel is prevented from being reduced.

A gate driving circuit and a method for driving a gate driving circuit, a display panel, and a display device are provided. The gate driving circuit includes M groups of shift register units, and each group includes one first shift register unit and N−1 second shift register units. The first noise reduction of the first shift register unit performs noise reduction under control of the second node. The second noise reduction circuit of the second shift register units performs noise reduction under control of the second node. In a same group of shift register units, the first shift register unit and the second shift register units share a same second node. A first input signal and a second input signal received by a Kth group of shift register units are a shift signal of a first shift register unit in a (K−2)th group of shift register units.

A shift register comprises: an input circuit (1) configured to write a signal provided by a signal input terminal (INPUT) to a third node (N3) in response to a signal provided by a first clock signal terminal (CK); a first control circuit (2) configured to write a voltage provided by a first power supply terminal to a first node (N1) in response to a signal provided by a preset control signal terminal (CS) and a signal provided by a preset clock signal terminal; a second control circuit (3) configured to write a voltage provided by a second power supply terminal to the first node (N1) in response to a signal provided by the signal input terminal (INPUT); and an output circuit (4) configured to write the voltage provided by the second power supply terminal to a signal output terminal (OUT) in response to a voltage at the first node (N1) and write the voltage provided by the first power supply terminal to the signal output terminal (OUT) in response to a voltage at a fourth node (N4), the third node (N3) being coupled to the fourth node (N4). The disclosure also provides a gate drive circuit (DC) and a display device.

The invention discloses a successive approximation type analog-to-digital converter and a conversion method. The analog-to-digital converter comprises a digital-to-analog converter, a comparator and a shift register, the digital-to-analog converter comprises a normal-phase capacitor array connected with the normal-phase end of the comparator and an inverted-phase capacitor array connected with the inverted-phase end of the comparator. The other end of each first capacitor in the high array is connected with one of a sampling signal, a reference voltage, a common-mode voltage and a reference ground through a switch; the other end of each second capacitor in the low array is connected with one of reference voltage, common-mode voltage and reference ground through the switch; capacitors in the high array and the low array are binary weighted capacitors from a low bit to a high bit; and the shift register is used for receiving a comparison result output by the comparator after the switch in the normal-phase capacitor array or the reverse-phase capacitor array is switched. The invention is beneficial to saving area, increasing input range and reducing power consumption, and can be widely applied to the technical field of electronics.

Embodiments of the present application provide a display panel and a display device. The display panel comprises a shift register, the shift register comprising a plurality of shift register units; the shift register unit comprising an input module, an output module and a voltage stabilizing module; the input module is configured to write voltages to a first node and a second node based on at least an input signal and a first clock signal; the output module is connected to the first node and the second node respectively; the output module is configured to output a high level signal based on the voltage of the first node, and is also configured to output a low level signal based on the voltage of the second node; the voltage stabilizing module is connected to the first node; during at least part of the period when the first node is at a high potential, the voltage stabilizing module is configured to pull up the potential of the first node based on the voltage of the first node and a first voltage signal. The present application can ensure that the shift register unit stably outputs a high level enable signal, thereby improving the product performance reliability.

An array substrate (001), a display panel (PNL), a display device and a driving method. The array substrate (001) comprises a base substrate (101). The base substrate (101) comprises a display area (AA) and a non-display area (BB) located on at least one side of the display area (AA). The non-display area (BB) comprises a shift register area (GOA); and a sensor circuit (103), the sensor circuit (103) being configured to monitor at least one of the temperature of the display area (AA), the temperature of the shift register area (GOA), and the ambient temperature.

The invention discloses a zero-dead-time single photon counting system based on time division multiplexing, and belongs to the technical field of laser radars. The system comprises an optical multiplexer, N detection channels, N delay modules, a shift register and a counting circuit, according to a time division multiplexing mechanism, a time axis is divided into a plurality of independent time slots, and in different time slots, incident signal light is input into different detection channels according to a preset sequence, so that zero-dead-time single photon counting is realized. According to the invention, the dead time problem of a traditional single-photon detector is solved, the photon counting pulse and the dark current pulse are effectively distinguished through a multi-parameter pulse discrimination technology, the signal-to-noise ratio of the system is significantly improved, and a reliable solution is provided for application scenes requiring high-sensitivity detection, such as laser radar and quantum communication.

Provided are a gate driving circuit, a display panel, and a display device. The gate driving circuit includes multiple cascaded shift registers. A shift register includes a first input unit, a second input unit, a first output unit, a second output unit, a first reset unit and a turn-off unit. The first reset unit is configured to write a turn-off voltage into a first node; the gate of the first reset transistor is connected to a first clock signal terminal or a third clock signal terminal; a first electrode of the first reset transistor is connected to a first node; and a first terminal of the turn-off unit is connected to a second electrode of the first reset transistor and is configured to write a turn-on voltage into the second electrode of the first reset transistor when the first node controls the turn-off unit to turn on.

The invention relates to the technical field of laser control, in particular to a laser compatible control system based on an STM32 microcontroller platform, which comprises a core control unit, a digital signal processing module, an analog signal processing module and a heat dissipation management module. The core control unit adopts an STM32 series microcontroller and interacts with all the modules through an SPI bus, the digital signal processing module adopts a shift register cascade architecture, the analog signal processing module shares the SPI bus through a plurality of digital-to-analog conversion chips, and the heat dissipation management module achieves temperature collection, fan driving and rotating speed feedback. The system supports RS232, RS485 and differential signal communication, and is adapted to various lasers. According to the invention, IO resource occupation can be reduced, data transmission efficiency and response speed can be improved, accurate temperature control and intelligent speed regulation can be realized, system compatibility can be enhanced, and complex industrial scene requirements of multi-wavelength microscopic imaging and the like can be satisfied.

The utility model provides a display substrate and a display device. The display substrate comprises a substrate body, the substrate body comprises a display area and a non-display area, and the non-display area is located on at least one side of the display area; the driving circuit layer is located on one side of the substrate, the driving circuit layer comprises a shifting register located in the non-display area, the shifting register comprises a plurality of cascaded shifting register units, and each shifting register unit comprises a first sub-circuit configured to provide a light-emitting control signal, a second sub-circuit configured to provide a light-emitting control signal, and a third sub-circuit configured to provide a light-emitting control signal; and a second sub-circuit configured to provide a second reset control signal; the driving circuit layer further comprises a first power line, the first power line is configured to provide a low-level signal for the shifting register unit, the first power line comprises a first power supply first sub-line and a first power supply second sub-line, the first sub-circuit is electrically connected with the first power supply first sub-line, and the second sub-circuit is electrically connected with the first power supply second sub-line. And the first power supply first sub-line and the first power supply second sub-line are independently arranged.

The application discloses a scanning driving circuit and a display device. The scanning driving circuit comprises a plurality of shift registers. The shift register comprises a driving control module, an output control module and a scanning output module. The driving control module is used for controlling the potential of the first output end and the second output end of the driving control module according to an input signal; the input end of the output control module is connected with the first output end or the second output end, and the control end of the output control module inputs a frequency switching control signal; and the scanning output module is used for responding to the potential of the output end of the output control module, and controlling the output of a scanning signal to the output end of the shift register. The embodiment of the application can make the display device have a partition frequency display function.

Embodiments of the present application provide a driving circuit and a driving method thereof, a display panel and a display device. The driving circuit is used for driving a pixel circuit. The pixel circuit comprises a driving transistor, a gate reset transistor, a data write transistor and a threshold value capture transistor which are electrically connected with the driving transistor. The driving circuit comprises a plurality of cascaded shift register units. The shift register unit comprises a first type signal output module and a second type signal output module. The output end of the first type signal output module is electrically connected with the gate of the gate reset transistor and / or the threshold value capture transistor. The output end of the second type signal output module is electrically connected with the gate of the data write transistor. The present application can reduce the number of peripheral driving circuits required by the pixel circuit, which is conducive to realizing narrow frame and low power consumption of the display panel.

A gate driver can include a level shifter configured to output first-mode gate clocks in a normal scan rate mode and output second-mode gate clocks in a high scan rate mode, and a gate shift register configured to output normal scan rate scan signals synchronized with the first-mode gate clocks in the normal scan rate mode and output high scan rate scan signals synchronized with the second-mode gate clocks in the high scan rate mode. Adjacent gate clocks of the first-mode gate clocks have a phase difference equal to 1 horizontal period, and adjacent gate clock pairs of the second-mode gate clocks have a phase difference equal to 1 horizontal period and two gate clocks configuring the same gate clock pair are synchronized with each other. The first-mode gate clocks are implemented as a 16-phase clock and the second-mode gate clocks are implemented as a 16-phase clock.

There is provided a gate driving circuit, a display panel and a driving method of the gate driving circuit. The gate driving circuit includes multiple stages of shift registers. The multiple stages of shift registers comprise N first shift registers arranged alternately with N second shift registers. The N first shift registers are cascaded-coupled as N stages of first shift registers, and are configured to generate N first output signals under control of K first clock signals. The N second shift registers are cascaded-coupled as N stages of second shift registers, and are configured to generate N second output signals under a control of K second clock signals. K and N are both integers greater than 1, and K≤N.

The utility model provides a shift register, a driving circuit and a display device, and relates to the technical field of display. The shift register includes: a shift circuit configured to control potentials of a first node and a second node and supply a first power supply voltage or a second power supply voltage to a first output terminal as a first output signal; the gating circuit is configured to provide a gating signal from a gating end to a third node under the control of a first input signal, a second input signal from a second input end and a first output signal; the control circuit is configured to provide the potential of the first node to the fourth node and provide the potential of the second node to the fifth node under the control of the potential of the third node; and the output circuit is configured to provide the first power supply voltage or the second power supply voltage to the second output end as a second output signal under the control of the potential of the fourth node and the potential of the fifth node.

A display substrate includes a substrate and a gate driving circuit provided on the substrate; the gate driving circuit includes: a frame start signal line, a clock signal line, an inverted clock signal line, a first level signal line, a second level signal line, and a plurality of shift register units. The plurality of transistors at least include a first transistor, a second transistor, and a third transistor, active layers of the first, second and third transistors are formed by a continuous first semiconductor layer, the first semiconductor layer extends along a first direction; the first semiconductor layer includes at least three channel portions corresponding to the first transistor, the second transistor and the third transistor, and a conductive portion provided between adjacent channel portions, transistors corresponding to the adjacent channel portions are coupled to each other through a corresponding conductive portion.

A display panel (10), a display device and a driving method, relating to the technical field of display. The display panel (10) comprises a plurality of pixel rows (101), a plurality of gating units (102), a gate driving circuit (103) and a control circuit (104). Each pixel row (101) comprises a plurality of pixel circuits (1011), and corresponds to a plurality of gating units (102). The gate driving circuit (103) comprises a plurality of row shift registers (1031). Each row shift register (1031) is electrically connected to the pixel circuits (1011) in the corresponding pixel row (101), respectively. Each gating unit (102) is electrically connected to one or more pixel circuits (1011) in the corresponding pixel row (101), is electrically connected to the row shift register (1031) corresponding to the pixel row (101), and is further electrically connected to the control circuit (104). Each gating unit (102) is used for sending a refreshing control signal to the corresponding pixel circuits (1011) on the basis of a scanning signal sent by the corresponding row shift register (1031), and a gating signal sent by the control circuit (104). Moreover, each pixel circuit (1011) is used for, when the refreshing control signal represents refreshing display, performing refreshing display in response to the scanning signal sent by the corresponding row shift register (1031).

A gate driver and a vehicle display are disclosed herein. The gate driver comprises a shift register module and a selection module. The shift register module includes first to fourth dummy shift register circuits and N shift register circuits. The first dummy shift register circuit is configured to output a first dummy signal. The second dummy shift register circuit is configured to output a second dummy signal. The third dummy shift register circuit is configured to output a third dummy signal. The fourth dummy shift register circuit is configured to output a fourth dummy signal. The selection module is configured to selectively output one of the first dummy signal and the third dummy signal and one of the second dummy signal and the fourth dummy signal according to the forward scan signal and the reverse scan signal.

The invention discloses a shift register and a display panel, the shift register comprises a first signal output module and a second signal output module, the control end of the first signal output module and the first control end of the second signal output module are connected to a first node, and the first node is used for accessing an initial signal; the second control end of the second signal output module and the output end of the first signal output module are connected to a second node, and the first signal output module is used for outputting a first gate drive signal to the second node according to the voltage of the first node. The second signal output module is used for outputting a second gate driving signal according to the voltage of the first node and the voltage of the second node; the short pulse width level of the first gate drive signal is opposite to the short pulse width level of the second gate drive signal. According to the scheme, through mutual borrowing and coordination of the first signal output module and the second signal output module, two different types of gate driving signals can be output, the circuit structure is simple, and narrow frame design is facilitated.