624 results about "Shift register" patented technology

The present disclosure provides a gate driving circuit and a display panel. by the control of one of the fourth node, the output end of the second output module, and the first node of the shift register of the next stage, the voltage regulating module may utilize a low voltage signal to stabilize or reduce the gate voltage of the second transistor, so that the second transistor is stable or preferably in the cut-off state to reduce the leakage current. In this way, voltage level of the second gate driving signal can be maintained at a high voltage level or a pulse amplitude.

The utility model provides a display substrate and a display device. The display substrate comprises a substrate body, the substrate body comprises a display area and a non-display area, and the non-display area is located on at least one side of the display area; the driving circuit layer is located on one side of the substrate, the driving circuit layer comprises a shifting register located in the non-display area, the shifting register comprises a plurality of cascaded shifting register units, and each shifting register unit comprises a first sub-circuit configured to provide a light-emitting control signal, a second sub-circuit configured to provide a light-emitting control signal, and a third sub-circuit configured to provide a light-emitting control signal; and a second sub-circuit configured to provide a second reset control signal; the driving circuit layer further comprises a first power line, the first power line is configured to provide a low-level signal for the shifting register unit, the first power line comprises a first power supply first sub-line and a first power supply second sub-line, the first sub-circuit is electrically connected with the first power supply first sub-line, and the second sub-circuit is electrically connected with the first power supply second sub-line. And the first power supply first sub-line and the first power supply second sub-line are independently arranged.

The application discloses a scanning driving circuit and a display device. The scanning driving circuit comprises a plurality of shift registers. The shift register comprises a driving control module, an output control module and a scanning output module. The driving control module is used for controlling the potential of the first output end and the second output end of the driving control module according to an input signal; the input end of the output control module is connected with the first output end or the second output end, and the control end of the output control module inputs a frequency switching control signal; and the scanning output module is used for responding to the potential of the output end of the output control module, and controlling the output of a scanning signal to the output end of the shift register. The embodiment of the application can make the display device have a partition frequency display function.

Embodiments of the present application provide a driving circuit and a driving method thereof, a display panel and a display device. The driving circuit is used for driving a pixel circuit. The pixel circuit comprises a driving transistor, a gate reset transistor, a data write transistor and a threshold value capture transistor which are electrically connected with the driving transistor. The driving circuit comprises a plurality of cascaded shift register units. The shift register unit comprises a first type signal output module and a second type signal output module. The output end of the first type signal output module is electrically connected with the gate of the gate reset transistor and / or the threshold value capture transistor. The output end of the second type signal output module is electrically connected with the gate of the data write transistor. The present application can reduce the number of peripheral driving circuits required by the pixel circuit, which is conducive to realizing narrow frame and low power consumption of the display panel.

The utility model provides a shift register, a driving circuit and a display device, and relates to the technical field of display. The shift register includes: a shift circuit configured to control potentials of a first node and a second node and supply a first power supply voltage or a second power supply voltage to a first output terminal as a first output signal; the gating circuit is configured to provide a gating signal from a gating end to a third node under the control of a first input signal, a second input signal from a second input end and a first output signal; the control circuit is configured to provide the potential of the first node to the fourth node and provide the potential of the second node to the fifth node under the control of the potential of the third node; and the output circuit is configured to provide the first power supply voltage or the second power supply voltage to the second output end as a second output signal under the control of the potential of the fourth node and the potential of the fifth node.

A gate driver and a vehicle display are disclosed herein. The gate driver comprises a shift register module and a selection module. The shift register module includes first to fourth dummy shift register circuits and N shift register circuits. The first dummy shift register circuit is configured to output a first dummy signal. The second dummy shift register circuit is configured to output a second dummy signal. The third dummy shift register circuit is configured to output a third dummy signal. The fourth dummy shift register circuit is configured to output a fourth dummy signal. The selection module is configured to selectively output one of the first dummy signal and the third dummy signal and one of the second dummy signal and the fourth dummy signal according to the forward scan signal and the reverse scan signal.

A display panel and a display device are provided. The display panel includes: a substrate, a driving layer, and an electrode layer. The driving layer and the electrode layer are located on a side of the substrate. The driving layer includes a shift register, and the shift register includes a plurality of cascaded shift register units. The electrode layer includes a plurality of electrode groups, and one of the plurality of electrode groups includes a first electrode and a second electrode. Along a direction perpendicular to a plane where the substrate is located, the plurality of shift register units at least partially overlaps with at least one of the plurality of electrode groups.

A random number generator comprises a ring generator and one or more inverter-based ring oscillators. The one or more inverter-based ring oscillators is configured to inject bits into the ring generator at a plurality of location. If there is more than one inverter-based ring oscillators, the inverter-based ring oscillators may have different numbers of inverting elements and may inject bits into the ring generator at different locations. At least one of the one or more inverterbased ring oscillators may be configured to inject bits into the ring generator at different locations from outputs of some or all its inverting elements. The random number generator may further comprise blocking circuitry configured to convert, based on a blocking signal, the ring generator into a circular shift register by blocking both the injection from the plurality of inverter-based ring oscillators and internal feedbacks in the ring generator.

A display substrate, and a display apparatus corresponding thereto and a manufacturing method therefor. The display substrate comprises: a display region and a non-display region, wherein the non-display region is provided with a gate driving circuit, which comprises a plurality of cascaded shift register units. Each shift register unit comprises: an input circuit (10), a first control circuit (11), a second control circuit (12) and an output circuit (15), wherein the first control circuit (11) is located between the input circuit (10) and the output circuit (15) in a first direction, and the first control circuit (11) is arranged in the first direction; and the second control circuit (12) is adjacent to the first control circuit (11) in a second direction; the first direction intersects with the second direction.

A shift register, includes a shift register unit and a first detection circuit electrically connected to the shift register unit. The shift register unit includes an input sub-circuit and an output sub-circuit. The input sub-circuit is configured to transmit a signal of an input signal terminal to a pull-up node under control of an input control terminal. The output sub-circuit is configured to receive a clock signal from a clock signal terminal, and provide an output signal to an output signal terminal based on the clock signal under control of a voltage at the pull-up node. The first detection circuit is electrically connected to the pull-up node and the clock signal terminal and is configured to obtain a voltage difference at the pull-up node within a first interval time, and perform compensation on a voltage of the clock signal based on the voltage difference at the pull-up node.

A shift register unit, a display panel, a display device, and a driving method. The shift register unit comprises: a shift register (001), a first driving sub-circuit (002), and a second driving sub-circuit (003). The shift register (001) is configured to control, on the basis of a signal of an input signal terminal (STV), a cascade output terminal (Scan_n) to output a cascade signal; the first driving sub-circuit (002) outputs a first driving signal by means of a first driving output terminal (Rout_n) in response to signals of a pull-up node (N9) and a downlink node (N10); and the second driving sub-circuit (003) outputs a second driving signal by means of a second driving output terminal (Nout_n) in response to signals of the pull-up node (N9), the downlink node (N10), and a local refresh signal control terminal (N11_N-n). The shift register unit can effectively reduce the width of a bezel while realizing line-by-line refreshing of the display panel.

Provided are a display panel and a display device. The display region of the display panel includes multiple shift register circuit groups. The shift register circuit group includes multiple shift register units disposed sequentially in a first direction. The multiple shift register circuit groups are arranged in a second direction. The first direction and the second direction intersect. The shift register circuit group is configured to output a first scan signal and includes at least a first shift register circuit group and a second shift register circuit group, which are respectively connected to first scan signals of different rows. The display region further includes multiple signal lines extending in the first direction. The signal line includes multiple signal line groups. The signal line group is electrically connected to a respective shift register circuit group, and different signal line groups are electrically connected to different shift register circuit groups.

A serial communication system (1) comprises: n slave devices (21-28) having the same address; a master device (10); n switch ICs (41-48); and shift registers (31-32) capable of individually controlling ON / OFF of the n switch ICs (41-48). One clock signal line and one data signal line connected to the master device (10) respectively branch into n clock signal lines and n data signal lines, and are respectively connected to the n slave devices (21-28) via the n switch ICs (41-48). Said one clock signal line and one data signal line connected to the master device (10) further branch into and are connected to shift registers (31-32).

A display panel includes pixels and a driver circuit. The driver circuit includes shift register units and switch modules. Each switch module includes N switch units turned on in a time-sharing manner. A signal input terminal of an M-th-stage shift register unit is electrically connected to a start control signal terminal through any one of an M-th switch unit to an N-th switch unit; and the signal input terminal of the M-th-stage shift register unit is electrically connected to a signal output terminal of at least one of a first-stage to an (M−1)-th-stage shift register unit through a first to an (M−1)-th switch unit. A signal input terminal of an (I+N)-th-stage shift register unit is electrically connected to a signal output terminal of at least one of an I-th-stage to an (I+N−1)-th-stage shift register unit through the N switch units.

A gate drive circuit (GM) and a display panel. The gate drive circuit comprises a shift register module (10), a self-stabilizing module (20) and at least two first output modules (30). A first transistor (T1) in the shift register module (10) and a second transistor (T2) in the self-stabilizing module (20) are controlled by a first clock signal to turn on in a time-division manner, and a semiconductor layer comprises different semiconductor materials. In a second time period, the frequency of the first clock signal is higher than the frequency of a second clock signal corresponding to the first output modules (30).

The application discloses a shift register and a display panel, and the shift register comprises an input module, a first potential control module, a second potential control module, a first output module and a second output module; the first potential control module is used for transmitting a first potential signal or a second potential signal to a second node in response to a potential of a first node; the second potential control module is used for transmitting the potential of the second node to a first control end of the second output module according to the first potential signal and a first clock signal; the first output module is used for outputting a second clock signal as a first scanning signal in response to the potential of the first node, or outputting the second potential signal as the first scanning signal in response to the potential of the second node; and the second output module is used for outputting the second potential signal as a second scanning signal in response to the potential of the first node, or outputting the first potential signal as the second scanning signal in response to the potential of the first control end of the second output module. The application can output two scanning signals through one shift register, so that the shift register is more integrated, and a narrow frame is realized.

This application discloses a display panel and a display device, comprising: a driving circuit including multiple cascaded shift register units; each shift register unit includes a driving control circuit, a cascading circuit, a refresh control circuit, an isolation circuit, and a reset circuit; the driving control circuit is electrically connected to an input terminal, a first clock terminal, a first driving node, and a second driving node; the cascading circuit is electrically connected to the first driving node, the second driving node, a first voltage terminal, a second voltage terminal, and a cascading terminal; the refresh control circuit is electrically connected to the cascading terminal, the refresh control terminal, a first auxiliary node, and a scanning terminal; the isolation circuit is electrically connected to the first driving node, the first auxiliary node, the second auxiliary node, and an auxiliary voltage terminal; and the reset circuit is electrically connected to the second auxiliary node, the reset voltage terminal, and the scanning terminal. By adopting the above technical solution, the performance of the driving circuit can be improved, and the display effect can be enhanced.

This invention relates to a fully automated conveyor distribution line device and method, belonging to the field of automated production line conveying and distribution technology. The invention provides a fully automated conveyor distribution line device, including a feeding conveyor component, a workstation conveyor component, workstation components, multiple sensors, and a control module. The control module has a built-in shift register, which is configured with physical storage bits corresponding to each sensor, workstation storage bits corresponding to each workstation component, and virtual intermediate storage bits arranged between adjacent physical storage bits. Relying on the shift register, the control module drives product attribute information to be temporarily stored in physical storage bits, then transferred and shifted step-by-step through virtual intermediate storage bits, synchronously flowing with the product conveying process and matching its position in real time. This eliminates information misalignment, resists human interference, adaptively adjusts the conveying cycle time, avoids material accumulation, and allows for the storage and traceability of processing information, significantly improving distribution accuracy and the level of production line automation.

Provided in the present disclosure are a display panel and a display device. The display panel comprises: a display area and a peripheral area located at the periphery of the display area. The display panel further comprises: a plurality of sub-pixels, a gate driving circuit, and a power signal transmission layer, wherein the plurality of sub-pixels are located in the display area; the gate driving circuit comprises a plurality of shift register units, and the shift register units are coupled to the corresponding sub-pixels; and the power signal transmission layer comprises a portion located in the display area and a portion located in the peripheral area, and the shift register units are coupled to the power signal transmission layer.

The application relates to a bit depth extension circuit capable of improving display effect, a display device and a driving method. The bit depth extension circuit comprises a bit extension control line used for transmitting a normal mode signal or an extension mode signal; a first shift register unit connected with the bit extension control line and used for sequentially outputting 2N first sampling signals when the extension mode signal is received from the bit extension control line; N storage units respectively connected with the shift register unit and a data line; each storage unit is used for corresponding to receive 2 first sampling signals, and obtaining and saving M-bit pixel data from the data line according to each received first sampling signal; N latches are connected with the N storage units one by one and are respectively connected with a latch signal line; each latch is used for combining M-bit pixel data twice saved by the storage unit corresponding to the latch into one 2M-bit pixel data and performing latching when a latch signal is received from the latch signal line.

The application provides a circuit based on a beamforming chip serial peripheral interface, a beamforming chip and a radio frequency front end, comprising a shift register and a data output unit; an input end of the shift register is connected with a first device, and an output end of the shift register is connected with the data output unit, which is used for receiving a command field and / or input data from the first device and performing data output; the shift register is controlled by a mode selection input signal to switch between a first mode and a second mode; in the first mode, the first device is a master device, and the shift register outputs the input data from the first device to a target static register corresponding to the command field; in the second mode, the first device is an upstream device, and the shift register outputs the input data from the first device to a downstream device. In the above-mentioned circuit, the shift register can be switched between the first mode and the second mode, and the flexibility is improved.

Provided in the embodiments of the present application are a display panel and a display apparatus. The display panel comprises a display region and a non-display region. The non-display region surrounds at least part of the display region, and the non-display region comprises a first non-display region, a rounded corner region and a second non-display region, wherein the rounded corner region is located between the first non-display region and the second non-display region, and both the first non-display region and the second non-display region are adjacent to the rounded corner region. The display panel comprises a scan driving circuit. The scan driving circuit comprises a plurality of shift register units, the plurality of shift register units including a plurality of first‑type shift register units and a plurality of second‑type shift register units, wherein the first‑type shift register units are located in the first non-display region, the second-type shift register units are located in the rounded corner region, and in the rounded corner region, at least some of the second-type shift register units have different step sizes. The present application can reduce the width of rounded corner regions, thereby helping to make the width of the rounded corner regions converge towards that of first non-display regions.

The present disclosure provides an array substrate and a display device. The array substrate includes a substrate layer and a gate drive circuit disposed at a peripheral region of the substrate layer. The gate drive circuit includes a plurality of cascaded shift registers. The shift register includes an input circuit, an output circuit, a pull-down node control circuit, and a noise reduction circuit. At least one transistor included in the input circuit, the output circuit, and the noise reduction circuit is a first type of transistor. The pull-down node control circuit includes a plurality of transistors connected between a first voltage terminal and a first reset voltage terminal, and at least one transistor of the plurality of transistors is a second type of transistor. The first type of transistor includes a first active layer, and the second type of transistor includes a second active layer. An electron mobility of the second active layer is less than an electron mobility of the first active layer.

An apparatus comprising: at least one processing element configured to process a data flow in at least one direction of a plurality of directions; a configuration register comprising at least one setting that determines the processing of the data flow with the at least one processing element; and a shift register configured to select data of the at least one processing element from the at least one direction, and to provide at least one shifted data sample to a plurality of slices configured to perform at least one arithmetic operation with the data flow; wherein at least one slice of the plurality of slices is configured with the at least one setting of the configuration register.

The present disclosure relates to a display panel, a display device, and a gate driver circuit. According to one embodiment of the present disclosure, a display panel includes a gate driver circuit in which a voltage of a Q node between an input and an output of a gate shift register in a gate driver circuit (GIP) does not rise but is maintained at a value below a specific voltage when a display device is operated at a low speed for a long period of time. To this end, a potential holding device is connected to a Q node, a Q2 node, or a weak node between an input unit and an output unit of a gate shift register. During a light emission operation for display, the potential holding device holds the potential of the Q node at a value below a predefined level. Accordingly, image quality defects caused by damage to the output voltage due to leakage and noise at the output node are prevented.

The application discloses a shift register unit, a driving method thereof, a display driving circuit and a display device, and belongs to the technical field of display. In the shift register unit, an input circuit (01) can transmit power signals with different potentials to a control node (PD) in different time periods in response to an input signal (In / ESTV) and a clock signal (CKN, CK), and two output circuits (02, 03) can transmit power signals with different potentials to connected output ends (Nout, Next) in different time periods in response to the potential of the control node (PD). Therefore, it can be determined that the shift register unit comprises P-type transistors and N-type transistors. Furthermore, the two output circuits (02, 03) can independently output signals to the connected output end (Nout). On this basis, the potential of the power signal can be flexibly adjusted, so that the driving output end (Nout, Next) of the connected pixel can reliably transmit the required driving signal with the potential to the pixel in different refresh frequency regions, to support the local refresh function. The shift register unit has simple structure and rich functions.

A gate drive circuit and a display panel. The gate drive circuit includes one or more shift register groups. Each of the shift register groups includes N shift adjacent registers that output in sequence, with N being an integer greater than or equal to 3. Each of the shift registers includes a first output stage and a frequency division control module. The first output stage is configured to output a gate drive signal. The frequency division control module is configured to control outputting of the gate drive signal based on a refresh frequency. A control end of each frequency division control module in each of the shift register groups receives a control signal with a different phase and a same frequency, respectively, to adjust a pulse width of the gate drive signal and maintain a same pulse width at different refresh frequencies.

Provided are a shift register unit and a driving method therefor, and a gate driving circuit and a display apparatus, which belong to the technical field of display. The shift register unit comprises a plurality of control circuits and an output circuit. Under the cooperation of the plurality of control circuits, the potentials of a pull-up node and a pull-down node can be stabilized by flexibly setting a clock signal, thereby ensuring that the output capability of the shift register unit is better. In addition, on the basis that the output circuit respectively outputs, in response to the potentials of the pull-up node and the pull-down node and via different output terminals, a cascade signal to cascaded shift register units in other stages and a driving signal to a pixel, a cascade load can be reduced, thereby preventing a cascade function from being affected by the load, and ensuring that the cascade function is better. In this way, by using the shift register unit, pixels can be driven to reliably emit light, thereby preventing poor display and ensuring a better display effect.

A display substrate and an electronic device are provided. The display substrate includes a base substrate, including a display region and a peripheral region on at least one side of the display region; and a shift register unit and a first clock signal line in the peripheral region of the base substrate, wherein the first clock signal line extends along a first direction on the base substrate, and is connected to a first clock signal terminal to be configured to provide a first clock signal to the shift register unit; the shift register unit includes an input circuit, an output circuit, a first control circuit, and an output control circuit; the output control circuit includes an output control transistor and a first capacitor, and the output circuit includes an output transistor and a second capacitor.

The application provides a repair circuit and a repair method of an analog signal. The repair circuit comprises a shift register, a plurality of patch units, a first input end of each of the plurality of patch units is connected to a signal line of an input signal, a second input end of each of the patch units is connected to the shift register, the shift register is used for inputting a negated signal into a corresponding patch unit according to a shift signal, a third input end of each of the patch units is used for inputting an enable signal, and the patch unit is used for controlling whether to negate the input signal according to the enable signal and the negated signal. Thus, the polarity correction of input and output signals between analog and digital in a digital-analog hybrid chip is realized.