1152 results about "Shift register" patented technology

The invention provides a mixed data precision matrix multiplication and addition unit and a calculation method, the matrix multiplication and addition unit comprises a calculation unit, and the calculation unit comprises a format division module, a multiplication array module, an addition tree module, an accumulator module, a normalization module and a shift register module. The calculation unit converts the first input matrix and the second input matrix into input data in a middle floating point format; executing parallel multiplication operation on the input data to generate an intermediate product result; performing index alignment and accumulation on the intermediate product result to generate an intermediate accumulated value; accumulating the intermediate product result and the value of the third input matrix in a form of accumulating an intermediate accumulated value, and outputting an accumulated result; and converting an accumulation result into a normalized result and outputting the normalized result. The format division module supports various precisions and converts data with different widths into an intermediate floating point format, so that other hardware units can be reused, and the problems that hardware resources are complex and different model reasoning scenes are difficult to meet are solved.

The present disclosure provides a gate driving circuit and a display panel. by the control of one of the fourth node, the output end of the second output module, and the first node of the shift register of the next stage, the voltage regulating module may utilize a low voltage signal to stabilize or reduce the gate voltage of the second transistor, so that the second transistor is stable or preferably in the cut-off state to reduce the leakage current. In this way, voltage level of the second gate driving signal can be maintained at a high voltage level or a pulse amplitude.

The invention relates to the technical field of intelligent control, and discloses an intelligent control method for an etching process of a PCB (Printed Circuit Board), which comprises the following steps of: acquiring an image of an object to be processed, generating a discretized virtual load sequence, establishing a virtual shift register synchronized with a feedback pulse trigger clock of a transmission device encoder, driving the virtual load sequence to execute logic displacement of physical displacement phase locking; comparing the theoretical torque with the actual torque to obtain a torque residual error; a dynamic gain correction coefficient is calculated based on the torque residual error, the basic feed-forward gain is weighted and modulated in real time, and a control instruction is generated, and a time sequence error caused by transmission speed fluctuation is avoided by constructing a rigid space-time synchronization architecture based on a virtual shift register; a torque residual error is used as a non-intrusive observation variable, and a gain scheduling mechanism is combined, so that self-adaptive compensation for impedance drift of a controlled medium under the condition of no physical sensor is realized.

The present disclosure relates to the technical field of display. Provided are a shift register unit, a gate driving circuit, a display panel and a driving method therefor. The shift register unit is applied to a gate driving circuit in a display panel, the gate driving circuit comprising a plurality of cascaded shift register units, and the display panel comprising a pixel driving circuit. The shift register unit comprises: a first output circuit and a second output circuit, the first output circuit being used for providing in a first driving state a gate driving signal to the pixel driving circuit and used for providing in a second driving state an invalid level signal to the pixel driving circuit, and the second output circuit being used for providing an input signal to a lower-level shift register unit. The display panel using the shift register unit can realize adjustment of the local refresh rate. (figure 2)

An apparatus that includes a shift register unit, a gate driving circuit, and a display apparatus. The shift register unit includes: an input circuit, a reset circuit, a node control circuit, a cascade output circuit and a drive output circuit, where the drive output circuit is configured to provide the signal of the clock signal end to a drive output end in response to the signals of the first node.

A shift register unit includes a driving control module configured to receive an input signal and control a signal of a first output node and a signal of a second output node, a stage transfer module configured to receive a signal of a first output node and a signal of a second output node and control a stage transfer signal, a transmission control module configured to receive a stage transfer signal and a transmission control signal and control a signal of a third output node, an auxiliary control module configured to receive a signal of a second output node, a signal of a third output node and an auxiliary control signal and control a signal of a fourth output node, and a scanning module configured to receive at least a signal of a third output node and a signal of a fourth output node and control a scanning signal.

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

A shift register comprises: an input circuit (1) configured to write a signal provided by a signal input terminal (INPUT) to a third node (N3) in response to a signal provided by a first clock signal terminal (CK); a first control circuit (2) configured to write a voltage provided by a first power supply terminal to a first node (N1) in response to a signal provided by a preset control signal terminal (CS) and a signal provided by a preset clock signal terminal; a second control circuit (3) configured to write a voltage provided by a second power supply terminal to the first node (N1) in response to a signal provided by the signal input terminal (INPUT); and an output circuit (4) configured to write the voltage provided by the second power supply terminal to a signal output terminal (OUT) in response to a voltage at the first node (N1) and write the voltage provided by the first power supply terminal to the signal output terminal (OUT) in response to a voltage at a fourth node (N4), the third node (N3) being coupled to the fourth node (N4). The disclosure also provides a gate drive circuit (DC) and a display device.

Embodiments of the present application provide a display panel and a display device. The display panel comprises a shift register, the shift register comprising a plurality of shift register units; the shift register unit comprising an input module, an output module and a voltage stabilizing module; the input module is configured to write voltages to a first node and a second node based on at least an input signal and a first clock signal; the output module is connected to the first node and the second node respectively; the output module is configured to output a high level signal based on the voltage of the first node, and is also configured to output a low level signal based on the voltage of the second node; the voltage stabilizing module is connected to the first node; during at least part of the period when the first node is at a high potential, the voltage stabilizing module is configured to pull up the potential of the first node based on the voltage of the first node and a first voltage signal. The present application can ensure that the shift register unit stably outputs a high level enable signal, thereby improving the product performance reliability.

The utility model provides a display substrate and a display device. The display substrate comprises a substrate body, the substrate body comprises a display area and a non-display area, and the non-display area is located on at least one side of the display area; the driving circuit layer is located on one side of the substrate, the driving circuit layer comprises a shifting register located in the non-display area, the shifting register comprises a plurality of cascaded shifting register units, and each shifting register unit comprises a first sub-circuit configured to provide a light-emitting control signal, a second sub-circuit configured to provide a light-emitting control signal, and a third sub-circuit configured to provide a light-emitting control signal; and a second sub-circuit configured to provide a second reset control signal; the driving circuit layer further comprises a first power line, the first power line is configured to provide a low-level signal for the shifting register unit, the first power line comprises a first power supply first sub-line and a first power supply second sub-line, the first sub-circuit is electrically connected with the first power supply first sub-line, and the second sub-circuit is electrically connected with the first power supply second sub-line. And the first power supply first sub-line and the first power supply second sub-line are independently arranged.

The application discloses a scanning driving circuit and a display device. The scanning driving circuit comprises a plurality of shift registers. The shift register comprises a driving control module, an output control module and a scanning output module. The driving control module is used for controlling the potential of the first output end and the second output end of the driving control module according to an input signal; the input end of the output control module is connected with the first output end or the second output end, and the control end of the output control module inputs a frequency switching control signal; and the scanning output module is used for responding to the potential of the output end of the output control module, and controlling the output of a scanning signal to the output end of the shift register. The embodiment of the application can make the display device have a partition frequency display function.

Embodiments of the present application provide a driving circuit and a driving method thereof, a display panel and a display device. The driving circuit is used for driving a pixel circuit. The pixel circuit comprises a driving transistor, a gate reset transistor, a data write transistor and a threshold value capture transistor which are electrically connected with the driving transistor. The driving circuit comprises a plurality of cascaded shift register units. The shift register unit comprises a first type signal output module and a second type signal output module. The output end of the first type signal output module is electrically connected with the gate of the gate reset transistor and / or the threshold value capture transistor. The output end of the second type signal output module is electrically connected with the gate of the data write transistor. The present application can reduce the number of peripheral driving circuits required by the pixel circuit, which is conducive to realizing narrow frame and low power consumption of the display panel.

There is provided a gate driving circuit, a display panel and a driving method of the gate driving circuit. The gate driving circuit includes multiple stages of shift registers. The multiple stages of shift registers comprise N first shift registers arranged alternately with N second shift registers. The N first shift registers are cascaded-coupled as N stages of first shift registers, and are configured to generate N first output signals under control of K first clock signals. The N second shift registers are cascaded-coupled as N stages of second shift registers, and are configured to generate N second output signals under a control of K second clock signals. K and N are both integers greater than 1, and K≤N.

The utility model provides a shift register, a driving circuit and a display device, and relates to the technical field of display. The shift register includes: a shift circuit configured to control potentials of a first node and a second node and supply a first power supply voltage or a second power supply voltage to a first output terminal as a first output signal; the gating circuit is configured to provide a gating signal from a gating end to a third node under the control of a first input signal, a second input signal from a second input end and a first output signal; the control circuit is configured to provide the potential of the first node to the fourth node and provide the potential of the second node to the fifth node under the control of the potential of the third node; and the output circuit is configured to provide the first power supply voltage or the second power supply voltage to the second output end as a second output signal under the control of the potential of the fourth node and the potential of the fifth node.

A display panel (10), a display device and a driving method, relating to the technical field of display. The display panel (10) comprises a plurality of pixel rows (101), a plurality of gating units (102), a gate driving circuit (103) and a control circuit (104). Each pixel row (101) comprises a plurality of pixel circuits (1011), and corresponds to a plurality of gating units (102). The gate driving circuit (103) comprises a plurality of row shift registers (1031). Each row shift register (1031) is electrically connected to the pixel circuits (1011) in the corresponding pixel row (101), respectively. Each gating unit (102) is electrically connected to one or more pixel circuits (1011) in the corresponding pixel row (101), is electrically connected to the row shift register (1031) corresponding to the pixel row (101), and is further electrically connected to the control circuit (104). Each gating unit (102) is used for sending a refreshing control signal to the corresponding pixel circuits (1011) on the basis of a scanning signal sent by the corresponding row shift register (1031), and a gating signal sent by the control circuit (104). Moreover, each pixel circuit (1011) is used for, when the refreshing control signal represents refreshing display, performing refreshing display in response to the scanning signal sent by the corresponding row shift register (1031).

A gate driver and a vehicle display are disclosed herein. The gate driver comprises a shift register module and a selection module. The shift register module includes first to fourth dummy shift register circuits and N shift register circuits. The first dummy shift register circuit is configured to output a first dummy signal. The second dummy shift register circuit is configured to output a second dummy signal. The third dummy shift register circuit is configured to output a third dummy signal. The fourth dummy shift register circuit is configured to output a fourth dummy signal. The selection module is configured to selectively output one of the first dummy signal and the third dummy signal and one of the second dummy signal and the fourth dummy signal according to the forward scan signal and the reverse scan signal.

The utility model provides a shift register, a driving circuit and a display substrate. The shift register comprises an input circuit, a control circuit and an output circuit. The input circuit is configured to provide a signal of a signal input end for a first node and provide a signal of a first power supply end for a second node under the control of a first clock signal end; the control circuit is configured to control the signals of the third node and the fourth node according to the signals of the first node and the second node; and the output circuit is configured to provide the signal of the second clock signal end to the signal output end under the control of the third node and the fourth node. The LTPO circuit can output a signal without a falling edge step, so that the problem that the LTPO circuit has the falling step can be solved.

A shift register unit and a driving method therefor, a gate drive circuit, and a display device, relating to the technical field of display. In the shift register unit, an input control circuit (01) can control the on-off of an input signal end (IN_n) and an input node (Q_n) under the control of a clock signal provided by a first clock end (CKn) and a clock signal provided by a second clock end (CB). An output control circuit (02) can output, by means of an output signal end (OUT_n) and on the basis of the potential of the input node (Q_n) and an enable control signal provided by an enable control end (GEN), a gate drive signal to pixels so as to drive the pixels to emit light. By flexibly setting the clock signals and the enable control signal, the shift register unit outputs the gate drive signal of a P-type transistor and / or an N-type transistor in the matched pixels to the output signal end (OUT_n), and in different time periods, the shift register unit is selectively controlled to output or not output, so that the pixels are locally refreshed, the gate drive signal is reliably reset, good driving flexibility is ensured, and the driving mode is rich.

A display panel and a display device are provided. The display panel includes: a substrate, a driving layer, and an electrode layer. The driving layer and the electrode layer are located on a side of the substrate. The driving layer includes a shift register, and the shift register includes a plurality of cascaded shift register units. The electrode layer includes a plurality of electrode groups, and one of the plurality of electrode groups includes a first electrode and a second electrode. Along a direction perpendicular to a plane where the substrate is located, the plurality of shift register units at least partially overlaps with at least one of the plurality of electrode groups.

A random number generator comprises a ring generator and one or more inverter-based ring oscillators. The one or more inverter-based ring oscillators is configured to inject bits into the ring generator at a plurality of location. If there is more than one inverter-based ring oscillators, the inverter-based ring oscillators may have different numbers of inverting elements and may inject bits into the ring generator at different locations. At least one of the one or more inverterbased ring oscillators may be configured to inject bits into the ring generator at different locations from outputs of some or all its inverting elements. The random number generator may further comprise blocking circuitry configured to convert, based on a blocking signal, the ring generator into a circular shift register by blocking both the injection from the plurality of inverter-based ring oscillators and internal feedbacks in the ring generator.

The invention provides a multi-protocol configurable interface circuit. The multi-protocol configurable interface circuit comprises a plurality of channel modules, a plurality of counter modules, an input / output module and a configuration register, the channel module comprises a state machine, a shift register and a cache module. The configuration register obtains configuration information through the system bus, and the configuration information comprises which protocol is selected. The counter module generates a shift signal required by a shift register in the channel module according to the configuration information; the input and output module selects the corresponding pins according to the configuration information and determines the function of each pin; and the channel module determines the mode of each channel and the required state of the state machine according to the configuration information to complete data transmission of the selected protocol. According to the invention, a hardware design which focuses on realizing clock and data transmission by matching a state machine state transition and a shift register with a cache module is adopted, so that software intervention and CPU occupation are reduced, and the overall efficiency is improved; hardware resources are reduced, and hardware flexibility is improved.

A display substrate, and a display apparatus corresponding thereto and a manufacturing method therefor. The display substrate comprises: a display region and a non-display region, wherein the non-display region is provided with a gate driving circuit, which comprises a plurality of cascaded shift register units. Each shift register unit comprises: an input circuit (10), a first control circuit (11), a second control circuit (12) and an output circuit (15), wherein the first control circuit (11) is located between the input circuit (10) and the output circuit (15) in a first direction, and the first control circuit (11) is arranged in the first direction; and the second control circuit (12) is adjacent to the first control circuit (11) in a second direction; the first direction intersects with the second direction.

The invention provides a shift register, a gate drive circuit, a display panel and a display device. A first node control module is configured to transmit a first voltage signal supplied by a first voltage end and a second voltage signal supplied by a second voltage end to a first node in a time-sharing manner according to a received starting signal and a first control signal; the second node control module is configured to transmit a first voltage signal and a second voltage signal to a second node in a time-sharing manner according to a first clock signal and a second control signal, and the signal of the second node and the signal of the first node are opposite in phase. Therefore, the output module can control a second clock signal and a second voltage signal supplied by a second voltage end to be output to the signal output end of the shift register in a time-sharing mode according to the signal of the first node and the signal of the second node, and then output of a grid control signal is achieved.

A system for scalable two-dimensional surface code comprises four sub-lattices of qubits, each selectively controlled by a set of analog lines. Eight sets of analog lines selectively control eight sets of inter-qubit couplers. The qubits and couplers have response homogenization devices comprising control structures to apply analog signals and DACs to apply static bias to qubits and couplers. A second surface code layer compensates for defective qubits. A quantum processor and a method of moving data within a quantum processor are described. The quantum processor has quantum logic units with a plurality of physical qubits and couplers. The logic unit has a plurality of logical qubit blocks making up 2-local interaction registers. A shift register block with one or more logical qubit blocks and merge blocks connecting adjacent logical qubit blocks are provided. The shift register block is selectively communicatively coupled to 2-local interaction registers by a merge block.

The invention relates to the technical field of infrared scanning, in particular to an infrared scanning device and a control method. The device comprises a shift register and a rapid charging and discharging circuit, the emitter is used for sequentially lighting according to a preset time interval and forming an overlapped emission sequence, each receiving lamp of the receiver is connected with one end of the rapid charging and discharging circuit through the shift register, and the other end of the rapid charging and discharging circuit is connected with the controller. The controller is used for generating a dynamic gating signal and carrying out signal acquisition on the receiver; and the shift register is used for controlling the dynamic combination selection of each receiving lamp based on the dynamic gating signal. Through deep cooperation of hardware circuit innovation and system-level time sequence optimization, a transmitting-receiving space-time matrix coupling mechanism is formed, a time sequence-space composite optimization scanning framework is constructed, the response speed bottleneck of a traditional scheme is ingeniously overcome, and the system-level time sequence optimization scanning framework is constructed. The technical breakthrough that the scanning frame rate is increased, the response delay is reduced, and the infrared scanning layout compatible with any topology is achieved.

A shift register, includes a shift register unit and a first detection circuit electrically connected to the shift register unit. The shift register unit includes an input sub-circuit and an output sub-circuit. The input sub-circuit is configured to transmit a signal of an input signal terminal to a pull-up node under control of an input control terminal. The output sub-circuit is configured to receive a clock signal from a clock signal terminal, and provide an output signal to an output signal terminal based on the clock signal under control of a voltage at the pull-up node. The first detection circuit is electrically connected to the pull-up node and the clock signal terminal and is configured to obtain a voltage difference at the pull-up node within a first interval time, and perform compensation on a voltage of the clock signal based on the voltage difference at the pull-up node.

Disclosed are a display panel and a display device. The display panel includes a display area, a plurality of light-emitting elements located in the display area, and at least one driver circuit located in the display area; the plurality of light-emitting elements includes a plurality of light-emitting element rows extend in a first direction and arranged in a second direction, where the first direction and the second direction intersect; the at least one driver circuit includes a plurality of shift register circuits disposed in cascade and a shift register circuit of the plurality of shift register circuits is located between adjacent light-emitting element rows of the plurality of light-emitting element rows.

The invention discloses a display panel and a display device, and relates to the technical field of display. The display panel comprises a shift register, a plurality of cascade transmission clock lines and a plurality of scanning clock lines, the shift register comprises a plurality of cascaded shift register units; the shift register unit comprises an input circuit, a stage transmission output circuit and a scanning output circuit. The input circuit is electrically connected with the input end and the first node. The stage transmission output circuit is electrically connected with the first node, the stage transmission clock end and the stage transmission output end respectively; wherein the stage transmission output end of the ith-stage shift register unit is electrically connected with the input end of the jth-stage shift register unit, i is not equal to j, and both i and j are positive integers; the scanning output circuit is electrically connected with the first node, the scanning clock end and the scanning output end. Wherein the cascade transmission clock end is electrically connected with the cascade transmission clock line, and the scanning clock end is electrically connected with the scanning clock line. By adopting the technical scheme, high-frequency or low-frequency refreshing of any row can be realized, and the power consumption of the display panel is reduced.

Disclosed are a display panel and a display device. The display panel includes a display area, a plurality of light-emitting elements located in the display area, and at least one driver circuit located in the display area; the plurality of light-emitting elements includes a plurality of light-emitting element rows extend in a first direction and arranged in a second direction, where the first direction and the second direction intersect; the at least one driver circuit includes a plurality of shift register circuits disposed in cascade and a shift register circuit of the plurality of shift register circuits is located between adjacent light-emitting element rows of the plurality of light-emitting element rows.

Provided are a shift register and a driving method therefor, and a display substrate. The shift register comprises a plurality of cascaded first shift register units configured to provide scanning control signals, and a plurality of cascaded second shift register units configured to provide light-emission control signals, wherein each first shift register unit comprises a first scanning signal output module and a second scanning signal output module; the second scanning signal output modules of adjacent stages are connected to pixels in different rows, and two second scanning signal output modules corresponding to two adjacent rows of pixels are symmetrically distributed, with respect to a display area, in a first area and a second area of a non-display area on opposite sides relative to the display area; each second shift register unit comprises a first light-emitting signal output module and a second light-emitting signal output module; and at least the first light-emitting signal output modules or the second light-emitting signal output modules are distributed at intervals in a second direction with the second scanning signal output modules and are aligned in a first direction.