2877 results about "Shift register" patented technology

Threshold voltage shifts of transistors which are constituents of a bidirectional shift register are reduced to prevent a malfunction in the shift register. A bidirectional unit shift register includes first and second pull-down circuits (41, 42) connected to the gate of a first transistor (Q1) that supplies a first clock signal (CLK) to an output terminal (OUT). The first pull-down circuit (41) includes a first inverter that uses the gate of the first transistor (Q1) as the input node and that is activated by the first clock signal (CLK), and a second transistor (Q5A) that discharges the gate of the first transistor (Q1) according to the output of the first inverter. The second pull-down circuit (42) includes a second inverter that uses the gate of the first transistor (Q1) as the input node and that is activated by a second clock signal (/CLK) having a different phase from the first clock signal (CLK), and a third transistor (Q5A) that discharges the gate of the first transistor according to the output of the second inverter.

A shift register includes stages to generate gate signals in sequence. Each of the stages includes a first pull up drive control section, a pull up drive section and a pull down drive section. The first pull up drive control section outputs a control signal based on the gate signal of an adjacent stage. The pull up drive section receives a first clock signal and outputs the first clock signal as the gate signal to a corresponding gate line in response to the control signal. The pull down drive section inactivates the corresponding gate line in response to a second clock signal.

A shift register includes a first transistor supplying an output terminal with a clock signal input to a first clock terminal and a second transistor discharging the output terminal. Defining the gate node of the first transistor as a first node, and the gate node of the second transistor as a second node, the shift register includes an inverter circuit in which the first node serves as its input node and a capacitive element serves as a load, and a buffer circuit receiving the output from the inverter circuit and outputting a signal to the second node.

A mechanism for executing requests in a system. More specifically, a technique for processing requests to a memory system is provided. A shift register may be used to store an index associated with requests, such as read and write requests, to a memory system. Each request is stored in a respective queue depending on the source of the request and the request type (e.g. read or write). Each request includes flags which may be set to determine the processing order of the requests, such that out-of-order processing is feasible. An index corresponding to each of the requests is stored in an index shifter to facilitate the out-of-order processing of the requests. Alternatively, a shift register may be used to store each of the requests. Rather than shifting the indices to facilitate the out-of-order processing of requests, depending on the state of the corresponding request flags, the entire entry may be shifted.

Malfunction caused by leakage current of the transistor and shift in threshold voltage is prevented in the shift register in which the signal can be shifted bi-directionally. The bi-directional unit shift register includes a first transistor Q1 for providing a first clock signal CLK to an output terminal OUT, a second transistor Q2 for discharging the output terminal OUT based on a second clock signal, third and fourth transistors Q3, Q4 for providing first and second voltage signals Vn, Vr complementary to each other to a first node, which is a gate node of the first transistor Q1, and a fifth transistor Q5 connected between the first node and the output terminal OUT. The fifth transistor Q5 is in an electrically conducted state based on the first clock signal CLK when the gate of the transistor Q1 is at L (Low) level.

In a shift register and LCD device having the shift register that may be employed in the liquid crystal display device having a large screen size and a large resolution, the shift register includes stages cascade-connected with each other and each of the stages have a carry buffer for generating a carry signal. The pull-down transistor of each of the stages of the shift register is divided into a first pull-down transistor and a second pull-down transistor. A power voltage Vona larger than the power voltage Von applied to a clock generator is applied to the shift register. A signal delay due to the RC delay of the gate lines may be minimized, the shift register is independent of the variation of the threshold voltage of the TFTs, and image display quality may not be deteriorated.

An integrated circuit to serialize local data and selectively merge it with serialized feed-through data into a serial data stream output that includes a parallel-in-serial-out (PISO) shift register, a multiplexer, and a transmitter. The PISO shift register serializes parallel data on a local data bus into serialized local data. The multiplexer selectively merges serialized local data and feed-through data into a serial data stream. The transmitter drives the serial data stream onto a serial data link. In another embodiment of the invention, a method for a memory module includes receiving an input serial data stream; merging local frames of data and feed-through frames of data together into an output serial data stream in response to a merge enable signal; and transmitting the output serial data stream on a northbound data output to a next memory module or a memory controller. Other embodiments of the invention are disclosed and claimed.

A drive circuit of a display device, which comprise only single conductive TFTs and in which amplitude of an output signal is normal, is provided. A pulse is inputted to TFTs 101 and 104 so that the TFTs would turn ON and then potential of a node á rises. When the potential of the node á reaches (VDD-VthN), the node á became in a floating state. Accordingly, a TFT 105 then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the TFT 105 further rises due to an operation of capacitance 107 as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the TFT 105. An output at the subsequent stage is then inputted to TFTs 102 and 103 to turn the TFTs 102 and 103 ON, while the potential of the node á drops down to turn the TFT 105 OFF. A TFT 106 turns ON at the same time so that the potential of the output node would reach the level L.

To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.

Methods and apparati for marking digital material and for detecting marks therein. For mark detection, the material is divided into a plurality of blocks, to which a non-collision resistant compression function is applied. Compression outputs are placed in a shift register, whose value is tested for predetermined values or patterns. Mark embedding may be performed by modifying the data (for example by altering low-order bits and other non-critical regions) such that the outputs of the compression operation, when used as an input to the shift register, yield a predetermined value or pattern. A Hamming Majority operation, computed as the most common bit in a block, may be used as the compression operation, enabling marking and mark detection with material of virtually all types and formats. Mark detection technology may be implemented in media writers and other devices to determine whether the digital material is copyrighted or otherwise protected. An override capability is provided to allow authorized parties to bypass the protection.

A magnetic shift register utilizes a data column comprising a thin wire of magnetic material. A writing element selectively changes the direction of the magnetic moment in the magnetic domains to write the data to the data column. Associated with each domain wall are large magnetic fringing fields concentrated in a very small space. These magnetic fringing fields write to and read from the magnetic shift register. When the domain wall is moved close to another magnetic material, the fringing fields change the direction of the magnetic moment in the magnetic material, effectively “writing” to the magnetic material. A reading element similar to a tunneling junction comprises a free layer and a pinned layer of magnetic material. Fringing fields change the direction of the magnetic moment in the free layer with respect to the pinned layer, changing electrical resistance of the reading element and “reading” data stored in the magnetic shift register.

An array of non-volatile memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry may include a write driver, a read driver, a sense amplifier, and circuitry to isolate the memory cells from the sense amplifier with extended refresh. In some embodiments, the circuitry may further include shift registers and one or more arithmetic logic units to provide a video memory.

The invention provides a semiconductor device and a shift register, in which low noise is caused in a non-selection period and a transistor is not always on. First to fourth transistors are provided. One of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain thereof is connected to a gate electrode of the second transistor, and a gate electrode thereof is connected to a fifth wire. One of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain thereof is connected to a sixth wire. One of a source and a drain of the third transistor is connected to a second wire, the other of the source and the drain thereof is connected to the gate electrode of the second transistor, and a gate electrode thereof is connected to a fourth wire. One of a source and a drain of the fourth transistor is connected to the second wire, the other of the source and the drain thereof is connected to the sixth wire, and a gate electrode thereof is connected to the fourth wire.

A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDD−V thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDD+V thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD. When SP becomes low level; CK3 becomes low level; and CK1 becomes high level, the potential at the signal output section (Out) becomes low level again.

The invention discloses a shifting register, a grid integration drive circuit and a display screen. The joint of a source of a first thin film transistor and a drain of a second thin film transistor is set as a first upward-pull node, the joint of a capacitor and a grid of a third thin film transistor is set as a second upward-pull node, and a electric leakage prevention module is added between the first upward-pull node and the second upward-pull node; the first upward-pull node and the second upward-pull node are connected in display time duration of a frame through the electric leakage prevention module under the control of a display control signal end so that a grid startup signal can be normally outputted by the shifting register; the first upward-pull node and the second upward-pull node are disconnected in the touch control time duration of the frame, that is, a resistor with large resistance is connected to a discharge path of the capacitor in series, and therefore time of the capacitor for discharge can be greatly shortened, the electric leakage speed of the capacitor is effectively decreased, and the problem that normal display may not be achieved when the capacitor is applied to a touch screen with high report rate is solved.

A writing device can change the direction of the magnetic moment in a magnetic shift register, thus writing information to the domains or bits in the magnetic shift register. Associated with each domain wall are large magnetic fringing fields. The domain wall concentrates the change in magnetism from one direction to another in a very small space. Depending on the nature of the domain wall, very large dipolar fringing fields can emanate from the domain wall. This characteristic of magnetic domains is used to write to the magnetic shift register. When the domain wall is moved close to another magnetic material, the large fields of the domain wall change the direction of the magnetic moment in the magnetic material, effectively “writing” to the magnetic material.

A shift register includes a plurality of stages connected to one another, wherein each of the plurality of stages receives a first driving voltage as an input and transmits the first driving voltage using an output signal of a previous stage according to a first scan start signal or a first driving order to control an output of a clock signal or an inverted clock signal, and wherein the first driving voltage is at a high state for a partial time of one frame and at a low state for the remaining time of the frame at the first driving order. By using the method, a partial driving can be performed, and accordingly power consumption of the shift register can be reduced.

A reading device reads the direction of the magnetic moment of domains in a magnetic shift register, thus reading information stored in the domains or bits in the magnetic shift register. Associated with each domain wall are large magnetic fringing fields. The domain wall concentrates the change in magnetism from one direction to another in a very small space. Depending on the nature of the domain wall, very large dipolar fringing fields can emanate from the domain wall. This characteristic of magnetic domains is used to read data stored on to the magnetic shift register. The reading device reads the direction of the magnetic moment in a magnetic shift register, thus reading information stored in the domains.

A dual-gate transistor formed of two transistors connected in series between a first power terminal and a first node is used as a charging circuit for charging a gate node (first node) of a transistor intended to pull up an output terminal of a unit shift register. The dual-gate transistor is configured such that the connection node (second node) between the two transistors constituting the dual-gate transistor is pulled down to the L level by the capacitive coupling between the gate and second node in accordance with the change of the gate from the H level to the L level.

Malfunction caused by leakage current of the transistor is prevented in the shift register in which the signal can be shifted bi-directionally. The bi-directional unit shift register includes a transistor Q1 between a clock terminal CK and an output terminal OUT, a transistor Q2 for discharging the output terminal OUT, and transistors Q3, Q4 for providing first and second voltage signals Vn, Vr, which are complementary to each other, to the first node or a gate node of the transistor Q1. Furthermore, a transistor Q5, having a gate connected to a second node or a gate node of the transistor Q2, for discharging the first node is arranged.

A DLL circuit includes a delay line having a configuration with delay stages receiving alternate complementary clock signals ECK and /ECK having an adjusted phase difference therebetween. A capacitor can be used to adjust the phase difference between signals ECK and /ECK to allow the delay line to provide an amount of delay varying minutely. Preferably, for a fast clock, delay adjustment starts with a shift register having an initial value providing an intermediate amount of delay, and for a slow clock, delay adjustment starts with the shift register having an initial value providing a minimal amount of delay. There can be provided a semiconductor device provided with a DLL circuit accommodating a fast clock with reduced jitter.

A shift register includes a plurality of scan stages to output scan pulses to a plurality of gate lines, a first dummy stage to output a first dummy scan pulse to a first of the plurality of scan stages, and a second dummy stage to output a second dummy scan pulse to a last of the plurality of scan stages.

The main circuit of each stage of the high-reliability shift register circuit is composed of transistors, and the turn-on time for the four transistors are only 1˜2 pulse time within one frame time. Transistors construct an inverter circuit which continuously offers a high-level supply voltage that controls activities of transistors so as to continuously offer a low-level supply voltage to the first node and the output terminal such that avoids the first node and the output terminal being in a floating state. Besides, one of the transistor acts as a charging circuit that extends the lifetime of another transistor. This circuit avoids the affection on the behavior of the shift register circuit that is caused by an a-Si (amorphous silicon) TFT under a sustained stress.

The invention provides a gate drive circuit and method and a display device and relates to the technical field of display. The method includes the steps that gate row drive scanning is performed on shifting register units located in a first area in the gate drive circuit; after gate row drive scanning of the shifting register units in the first area is finished, touch scanning is performed; after touch scanning is finished, the last-level shifting register unit located in the first area is scanned again so that the last-level shifting register unit located in the first area can be used for pre-charging a first-level shifting register unit located in a second area; gate row drive scanning is performed on shifting register units located in the second area in the gate drive circuit, and the last-level shifting register unit located in the first area is in cascade connection with the first-level shifting register located in the second area. The method can overcome the defect that the row pixel charging rate is insufficient and solve the problem of dark lines or poor bright lines.

A shift register includes first and second stages for sequentially outputting scan pulses to drive first and second gate lines. One of the first and second stages includes a pull-up switching device connected to an enabling node of the one of the first and second stages; a first pull-down switching device connected to a first disabling node of the one of the first and second stages; a second pull-down switching device connected to a second disabling node of the one of the first and second stages; and a node controller. The node controller of the first stage controls the logic state of each of the enabling node of the first stage, the first disabling node of the first stage and the first disabling node of the second stage. The node controller of the second stage controls the logic state of each of the enabling node of the second stage, the second disabling node of the second stage and the second disabling node of the first stage.

A security apparatus including a number input device (302), an address register (312) responsive to the number input device, an encryption schema memory (316) addressable by the address register to produce an output code and a relative address code, and address incrementing logic (310) responsive the relative address code and operative to increment the address register. The apparatus also preferably includes a PIN register (304) coupled to the number input device, a public code register (306) coupled to the number input device, and merging logic (308) merging outputs of the PIN register and the public code register to be input to the address register. The apparatus also preferably includes an output shift register operative to shift out the output code of the encryption schema memory. The encryption schema memory can be read only memory, writeable memory, or both.

A gate driving circuit includes a shift register in which the stages are connected to each other one after another. An m-th stage includes a pull-up section outputting a high voltage of a first clock signal as a gate signal in response to a voltage of a first node, a pull-down section pulling down the gate signal to an off voltage in response to the first clock signal or the second clock signal, a driving section turning on and turning off the pull-up section and a holding section maintaining a voltage of the first node at the off voltage in response to the first clock signal, and a voltage maintenance section blocking a leakage current through the pull-up driving section and the holding section during an output interval of the gate signal to delay a voltage drop of the first node.

A method for conducting a broad range of biochemical analyses or manipulations on a series of nano- to subnanoliter reaction volumes and an apparatus for carrying out the same are disclosed. The invention is implemented on a fluidic microchip to provide high serial throughput. In particular, the disclosed device is a microfabricated channel device that can manipulate nanoliter or subnanoliter reaction volumes in a controlled manner to produce results at rates of 1 to 10 Hz per channel. The reaction volumes are manipulated in serial fashion analogous to a digital shift register. The invention has application to such problems as screening molecular or cellular targets using single beads from split-synthesis combinatorial libraries, screening single cells for RNA or protein expression, genetic diagnostic screening at the single cell level, or performing single cell signal transduction studies.

A shift register is disclosed, which can prevent a multi-output caused by a coupling phenomenon, the shift register comprising at least two clock transmission lines which transmit at least two clock pulses provided with the phase difference; and a plurality of stages which are supplied with the clock pulses from the clock transmission lines, and output output-signals in sequence, wherein each of the stages comprises a pull-up switching unit which is supplied with the first clock pulse, and outputs the first clock pulse as the output-signal according to a signal state of an enable node; and a noise eliminating unit which responds to the second clock pulse of which phase is prior to that of the first clock pulse supplied to the pull-up switching unit, and supplies a start pulse externally provided or the output-signal provided from the preceding stage to the enable node.

A 3-D LADAR imaging system incorporating stacked microelectronic layers is provided. A light source such as a laser is imaged upon a target through beam shaping optics. Photons reflected from the target are collected and imaged upon a detector array though collection optics. The detector array signals are fed into a multilayer processing module wherein each layer includes detector signal processing circuitry. The detector array signals are amplified, compared to a user-defined threshold, digitized and fed into a high speed FIFO shift register range bin. Dependant on the value of the digit contained in the bins in the register, and the digit's bin location, the time of a photon reflection from a target surface can be determined. A T₀ trigger signal defines the reflection time represented at each bin location by resetting appropriate circuitry to begin processing.

A reference insert circuit inserts data into the FIFO registers at a preselected location to provide a reference point at which all FIFO shift register data may be aligned to accommodate for timing differences between layers and channels. The bin data representing the photon reflections from the various target surfaces are read out of the FIFO and processed using appropriate circuitry such as a field programmable gate array to create a synchronized 3-D point cloud for creating a 3-D target image.