15 results about "Bias stress" patented technology

The invention provides a gate drive circuit and a display panel, and the gate drive circuit enables a first control module to transmit one of a forward scanning control signal and a reverse scanning control signal to a first node according to a first control signal and a second control signal, so as to raise or lower the potential of the first node. A second control module transmits one of a first clock signal and a second clock signal to a second node according to a first control signal and a second control signal; and the switching control module controls the switching frequency of alternate working of two switching transistors in the potential maintaining module according to the signal of the second node and the received switching control signal, so that the duration of the bias stress action on each switching transistor is reduced, and the potential change of the first node caused by the threshold voltage offset of the switching transistors is improved. And the normal output of the output module and the working stability of the gate drive circuit are influenced.

A display device includes a display panel including at least one pixel, an EM driver configured to generate an emission control signal of a multi-pulse type multi-toggled in one frame and supply the emission control signal to the at least one pixel, and a scan driver configured to generate a scan signal turned on in at least one off period included in the emission control signal, and supply the scan signal to the at least one pixel, so as to apply an on-bias stress (OBS) voltage to one electrode of the driving transistor and reset the light emitting element.

The invention discloses a preparation method of a double-layer polymer / metal oxide hybrid channel for processing a flexible electrolyte gate transistor by using a low-temperature solution, which comprises the following steps of: preparing a flexible single-channel polymer EGT with a low-temperature process as a short-time memory reference, and preparing a mixed polymer / In2O3 EGT as a long-time memory candidate device; comprising solid electrolyte integration and electrode deposition; measuring electrical and synaptic characteristics, including transfer curve, hysteresis, EPSC response, and synaptic plasticity, as well as selectable bias stress and cryogenic measurements only for monitoring and archiving; processing the collected data, and extracting key parameters including memory retention time, EPSC amplitude, conductivity state modulation, enhancement / suppression linearity and durability under repeated circulation; comparing the short-time memory behavior with the long-time memory behavior, evaluating adjustable transformation between a single layer and a hybrid device, and evaluating a stability trend under multiple cycles; and generating a comparison report with the annotation chart.

The application provides a semiconductor device and an operating method of the semiconductor device, which comprises a bidirectional threshold switch device with a first end and a second end connected in power supply, and an internal switch circuit for connecting the first end and the second end, receiving an external signal and making the bidirectional threshold switch device receive an internal pulse signal with a shorter bias time than the external signal. The semiconductor device and the operating method of the semiconductor device provided by the application can convert the external pulse signal into the internal pulse signal, thereby greatly improving the pulse precision, reducing the bias stress, and accurately obtaining the intrinsic holding voltage of the device through the test of different currents, formula fitting and the like.

A surgical end effector for use with an electrosurgical instrument is disclosed. The end effector includes a first jaw having a first electrode and a second jaw having a second electrode. The end effector is transitionable from an open configuration to a closed configuration to grasp tissue. The second electrode is laterally offset from the first electrode. The first electrode and the second electrode are configured to cooperate to deliver bipolar energy to the tissue. The second jaw further includes a monopolar electrode configured to deliver monopolar energy to the tissue and a compliant substrate. The monopolar electrode and the second electrode are fixedly attached to the compliant substrate in a spaced apart arrangement. The compliant substrate is configured to apply a biasing force to the second electrode and the monopolar electrode toward the first jaw in the closed configuration.

The invention relates to a display device and a driving method thereof. The display device includes: a display panel including at least one pixel; a source driver configured to supply a data voltage to the pixels during a refresh frame; a scan driver configured to supply a scan signal to the pixels, the scan signal defining a timing of a first on bias stress (OBS) period and a timing of a second OBS period, the first OBS period being prior to a timing of supplying a data voltage to the pixels, the second OBS period being prior to a timing of supplying a data voltage to the pixels; the second OBS period is after the timing of supplying the data voltage to the pixel and before the light emission timing of the pixel; and an OBS control circuit configured to supply a first OBS voltage having a first level to the pixel during the first OBS period, and supply a second OBS voltage having a second level different from the first level to the pixel during the second OBS period.

A display apparatus includes a display panel including a pixel, a source driver outputting a data voltage supplied to the pixel, in a refresh frame and stop the output of the data voltage in at least one skip frame succeeding the refresh frame, and a bias controller configured to output a first on-bias stress voltage to the pixel, in the refresh frame and output a second on-bias stress voltage to the pixel, in the at least one skip frame. The first and second on-bias stress voltages are applied to one electrode of a driving transistor included in the pixel so as to improve a luminance difference caused by a leakage characteristic variation of the pixel, and the first and second on-bias stress voltages are different so that a threshold voltage characteristic of the driving transistor differs in the refresh frame and the at least one skip frame.

The invention is entitled "Electronic device with low refresh rate display pixels." A display is disclosed that can have an array of organic light emitting diode display pixels that operate at low refresh rates. Each display pixel can have six thin film transistors and a capacitor. One of the six transistors can be used as a drive transistor and the remaining five transistors and capacitor can be used for compensation. One or more bias stress operations can be applied prior to threshold voltage sampling to mitigate first frame dimming. Multiple anode reset and bias stress operations can be inserted during a vertical blanking period to reduce flicker and maintain balance and can also be inserted between successive data refreshes to improve first frame performance. Two different emission signals that control each pixel can be toggled back and forth using a pulse width modulation scheme to help provide a darker black level.

The invention relates to a high-mobility oxide semiconductor thin film transistor based on a double-channel structure and a preparation method thereof, the high-mobility oxide semiconductor thin film transistor comprises a bottom gate, a channel dielectric layer, the double-channel structure, a source electrode, a drain electrode and a passivation layer, the bottom gate, the channel dielectric layer and the double-channel structure grow in sequence from bottom to top, the source electrode, the drain electrode and the passivation layer are respectively formed on a channel, and the double-channel structure is formed by stacking an a-IGZO channel layer and an a-IZO channel layer. Based on the characteristic of extremely low interface state density between the a-IZO material and the gate dielectric layer, the a-IZO / IGZO heterojunction structure can realize carrier transport performance of high mobility and high carrier concentration; and meanwhile, through barrier modulation, the trapping effect of the gate dielectric layer on a-IGZO channel carriers is effectively inhibited, so that the threshold voltage stability and the reliability under bias stress of the device are remarkably improved.

A display device includes: a display panel including at least one pixel; an EM driver configured to generate a light emission control signal of a multi-pulse type that is multi-switched in one frame, and to supply the light emission control signal to at least one pixel; and a scan driver configured to generate a scan signal turned on in at least one turn-off period included in the light emission control signal, and supply the scan signal to the at least one pixel so as to apply an on bias stress (OBS) voltage to one electrode of the driving transistor and reset the light emitting element.

A display device includes a display panel including a one pixel, a source driver configured to supply a data voltage to the pixel during a refresh frame, a scan driver configured to supply the pixel with a scan signal that defines a timing of a first on-bias stress (OBS) period that precedes a timing at which the data voltage is supplied to the pixel and a timing of a second OBS period that succeeds the timing at which the data voltage is supplied to the pixel and precedes an emission timing of the pixel, and an OBS control circuit configured to supply a first OBS voltage having a first level to the pixel during the first OBS period and supply a second OBS voltage having a second level that is different from the first level to the pixel during the second OBS period.

The invention discloses a display panel, a driving method thereof and a display device. The display panel comprises a pixel driving circuit, and the pixel driving circuit comprises a driving transistor, a first reset transistor, a threshold compensation transistor and a data writing transistor. In the first reset stage, the first enable level of the first scanning signal controls the first reset transistor to be switched on, the second enable level of the second scanning signal controls the threshold compensation transistor to be switched on, and the duration of the first enable level is larger than that of the second enable level. According to the display panel, the driving method thereof and the display device provided by the embodiment of the invention, the enabling time of the first scanning signal is prolonged, so that the driving transistor can be subjected to sufficient and lasting composite action of conduction bias stress (OBS) and negative bias stress (NBS), the ghosting problem of the display panel is improved, and the display effect of the display panel is improved. Meanwhile, thorough resetting of the first node, the second node and the third node of the driving transistor is achieved, and the problem that the brightness of the first frame is abnormal during picture switching is solved.

The invention belongs to the technical field of power device testing, and particularly relates to a dynamic conduction threshold voltage testing circuit and method for a gallium nitride device. The problems of poor stress switching real-time performance, low parameter extraction precision, difficulty in covering various working conditions and the like in the dynamic threshold voltage representation of the existing GaN device are solved. The circuit comprises a high-voltage source circuit which is used for providing adjustable high-voltage bias and simulating high-voltage turn-off stress borne by a device in practical application; the stress control switch is used for accurately controlling the time and time sequence of stress application and realizing rapid switching between a stress state and a test state; the drain electrode load matching network is used for current limiting protection in an off-state drain electrode bias stress test and is used for providing adjustable working current for the device to be tested in a continuous switch stress test; and the threshold voltage test circuit is used for rapidly and accurately extracting the dynamic threshold voltage parameter of the device to be tested within the transient time after the stress is released.

The invention discloses a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device threshold voltage measuring circuit which comprises a SiC MOSFET device Q1, a SiC MOSFET device Q2, an operational amplifier A1, a diode D1, a resistor Rg, a sampling resistor Rref, a bias stress change-over switch S1 and a power supply VDC. According to the invention, the threshold voltage extraction of the SiC MOSFET device under the high drain-source voltage of 200ns is realized, and compared with the traditional semiconductor parameter analysis equipment with higher cost, the threshold voltage extraction of the SiC MOSFET device can be realized only by an operational amplifier without other equipment, so that the equipment cost is low. In addition, threshold voltage measurement can be completed only by providing one PWM single pulse, and the control requirement is simple.

The invention provides a twin self-calibration photoelectric probability bit circuit unit and a preparation and use method thereof, the circuit unit comprises a self-calibration photoelectric differential module, a voltage comparator and a reference voltage source, the self-calibration photoelectric differential module is a pair of photoelectric indium gallium zinc oxide (IGZO) thin film transistors which are tightly coupled in space; the device is patterned through an ultraviolet lithography process and a radio frequency magnetron sputtering process at the same time, atomic-scale matching of a reference tube and a photosensitive tube in geometric dimension, film thickness and interface state density is ensured, differences only exist in illumination conditions, common-mode interferences such as aging caused by temperature drift and bias stress are offset by effectively utilizing a difference principle, and the performance of the device is improved. The physical characteristic of highly consistent aging trend is utilized to construct a synchronous drifting series voltage division network, and high-precision and high-stability in-situ photoelectric probability calculation is realized; probability bits are generated through dual modulation of grid voltage and light intensity, and the method is suitable for Bayesian reasoning, restricted Boltzmann machines and other probabilistic neural network hardware.