4852 results about "Threshold voltage" patented technology

The invention relates to a manufacturing method of a high dielectric layer metal gate device, and relates to the field of integrated circuits. The manufacturing method comprises the steps that a substrate is provided, the substrate comprises active regions and isolation structures, and the isolation structures and the active regions are arranged at intervals; the substrate is provided with a first region and a second region, the active region protrudes out of the isolation structure to form a first fin part in the first region, and a second fin part is formed in the second region; forming a first work function layer to cover the first fin part and the second fin part; free radicals generated by exciting the first gas through the metastable state particles are in contact with the surface of the first work function layer, and free dangling bonds on the surface of the first work function layer are removed; forming a second work function layer on the first work function layer; etching to remove the second work function layer on the first fin part; and the surface of the first work function layer is treated by free radicals generated by exciting the second gas through the metastable state particles. The problem of material loss of the first work function layer when devices with different threshold voltages are formed on the same substrate is solved.

The invention relates to the technical field of ultra-low power consumption microcontrollers, and discloses an ultra-low power consumption microcontroller architecture design method and system, and the method comprises the steps: constructing a heterogeneous dual-core processor comprising a high-performance core and a low-power consumption core, and dividing the heterogeneous dual-core processor into a plurality of independent power domains; constructing a sub-threshold voltage operation system on a plurality of independent power supply domains, and configuring a multi-layer storage structure in the heterogeneous dual-core processor; recording task characteristic data by using a multi-level storage structure, executing task dynamic allocation between dual cores, and creating a dynamic task allocation mechanism; and performing static analysis and function block division on the application code based on a dynamic task allocation mechanism to obtain a plurality of function code blocks, and performing storage hierarchy and processor core allocation on the plurality of function code blocks to obtain a function code allocation result. According to the method, the dynamic migration of the workload and the optimal resource allocation are realized, and the energy consumption of the microcontroller in various working scenes is reduced.

The invention discloses an optimization method and device for reading performance of a flash memory in a controller and a storage medium, and belongs to the technical field of flash memories.The method comprises the steps that a preset characteristic quantity, the number of erasing and writing reading times and data retention time are input into a current prediction model to obtain a reading voltage offset interval; the method for predicting the threshold voltage distribution of the flash memory according to the use condition of the flash memory is more real-time; on the basis of reading the voltage offset interval, performing read retry operation; during read retry operation, only one offset value of read voltage is adjusted to change in each page, and other voltage offset values in the same page change along with the change of the offset value of the read voltage; through the correlation of different read voltage deviation values of the same page, the number of times of re-reading is greatly reduced, the re-reading time is shortened, the reading performance is improved, the current prediction model is further updated and stored by utilizing threshold voltage distribution data determined by the read re-try operation, and the updated prediction model is used for the next read operation, so that the prediction accuracy is improved.

The invention relates to the technical field of data processing of organic display panels, in particular to a dynamic compensation method for driving signals of an organic display panel, which comprises the following steps of: acquiring brightness data in parallel by a photoelectric sensor array in different regions, and synchronously acquiring threshold voltage offset and environment temperature parameters of a thin film transistor; and after noise filtering, inputting into an aging feature extraction module and storing in a historical database. In the feature extraction stage, convolution kernel aggregation threshold voltage data is utilized to generate a regional aging coefficient matrix, the weight of a convolution kernel is dynamically adjusted based on a lightweight neural network, and an aging feature model is optimized in combination with real-time temperature parameters. The real-time problem of pixel-level compensation in a high-resolution scene is solved, and the calculation load of an embedded system is reduced.

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NOR architecture in which vertical NOR strings are formed of multiple memory cells connected in parallel between a source line and a bit line. Weights of the neural network are encoded as threshold voltages of the memory cells and activations are encoded as word line voltages applied to the memory cells of the NOR strings. The memory cells are operated in the subthreshold region, where the word line voltages are below the threshold voltages. The NOR structure naturally sums the resultant subthreshold currents of the individual memory cells to generate the product of the activations and the weights of the neural network by concurrently applying input voltages to multiple memory cells of a NOR string.

An electric vehicle battery control system including a first electric motor configured to propel a vehicle in a drive mode in response to a drive current, a second electric motor operative to generate a back electromotive force voltage in a fault mode, a battery, having an open circuit battery discharge voltage, for generating the drive current for coupling to the first electric motor, and a vehicle controller for limiting the drive current in response to a difference between the back electromotive force voltage and the open circuit battery discharge voltage being less than a threshold voltage difference.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a VDMOSFET (vertical double-diffused metal oxide semiconductor field effect transistor) device with low threshold voltage, which comprises a drain electrode, a semiconductor epitaxial layer, a source electrode, a grid electrode and a grid oxide layer covering the surface of the grid electrode, and is characterized in that an N substrate layer, an N drift layer, an N well layer, a P well layer and a heavily doped P layer are formed in the semiconductor epitaxial layer through ion implantation, the grid electrode comprises a triangular grid electrode and a rectangular grid electrode, the grid oxide layer covering the surface of the triangular grid electrode is in contact with the N substrate layer, and the N drift layer is divided into a left part and a right part by the grid oxide layer. According to the invention, the grid electrode is designed to further comprise the triangular grid electrode, the electric field effect of the grid electrode between the tip part of the triangular grid electrode and the drain electrode is better, but the grid oxide layer wrapped by the triangular grid electrode at the tip part is thicker, so that charges flowing out of the drain electrode gather towards the inside of the heavily doped N layer more quickly along the grid oxide layer; at the moment, more charge flow can be provided in a smaller grid voltage environment.

The invention belongs to the technical field of display driving, and particularly relates to a noise reduction circuit and a gate driving circuit, and the noise reduction circuit comprises a first noise reduction module which is used for carrying out the noise reduction processing of the voltage of a driving control node, a driving output end and a stage transmission output end; the first noise reduction module is also used for enabling a noise reduction transistor in the first noise reduction module to be in a reverse bias state under the action of a second noise reduction control signal; the second noise reduction module is used for carrying out noise reduction processing on voltage on the driving control node, the driving output end and the stage transmission output end; the second noise reduction module is also used for enabling a noise reduction transistor in the second noise reduction module to be in a reverse bias state under the action of the first noise reduction control signal; according to the noise reduction circuit, the noise reduction transistors in the two groups of noise reduction modules are in the reverse bias state when not working, so that the forward bias state of the noise reduction transistors in alternate working is counteracted, the problem that the threshold voltage of the noise reduction transistors drifts is solved, and the noise reduction stability of the noise reduction circuit is improved.

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NAND architecture. Multi-bit weight values are stored encoded as sets of threshold voltages for sets of memory cells. A weight value is stored in multiple memory cells on the same word line and connected between a bit line and a source line, each of the memory cells programmed to one of multiple threshold voltages. When multiplying an input value with the weight value, the word line is biased so that, for at least one of the threshold voltages, the memory cell will be in the linear operation region. Input values are encoded as a set of one or more voltage levels applied to a corresponding set of bit lines, each bit line connected memory cells also storing the weight value, connected to the word line, and connected to the source line.

Proposed is a device for receiving a four-level pulse amplitude modulation (PAM-4) signal, which includes a first comparator for comparing a received PAM-4 signal with a predetermined threshold voltage to output a most significant bit (MSB) signal; and a second comparator for comparing the differential signal difference between the positive signal and negative signal of the received PAM-4 signal with a reference voltage to output a least significant bit (LSB) signal.

A pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, a storage sub-circuit, and a first control sub-circuit. The data writing sub-circuit is configured to write a data signal provided by a data line into a second node under control of a first scan line. The compensation sub-circuit is configured to write a threshold voltage of the driving sub-circuit into the first node under control of a second scan line. The first control sub-circuit is configured to provide a reference voltage signal provided by a reference voltage line to the second node under control of the first control line after the data writing sub-circuit writes the data signal into the second node, so that the data signal written into the second node is coupled to the first node through the storage sub-circuit.

To provide a memory system and a memory device with high reliability.SOLUTION: A memory system of the embodiment includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to determine a first voltage based on information regarding a gradient of a distribution of threshold voltages of each of the plurality of memory cells, and to perform tracking operations. The memory controller causes the memory device to perform a plurality of read operations using a plurality of read levels for the plurality of memory cells in the tracking operation. The memory controller acquires the number of ON cells in each of the plurality of read operations. The memory controller sets a first potential difference of the plurality of read levels in a voltage range lower than the first voltage and a second potential difference of the plurality of read levels in a voltage range higher than the first voltage to be different from each other.SELECTED DRAWING: Figure 12

The invention belongs to the technical field of display driving, and particularly relates to a noise reduction circuit, a gate driving circuit and a display panel, and the noise reduction circuit comprises a noise reduction control unit, a threshold compensation unit and a noise reduction execution unit. The noise reduction control unit is used for outputting a noise reduction signal at the non-scanning time of the scanning stage of the current-stage gate driving module under the action of the noise reduction control signal output by the noise reduction control end and the voltage on the driving control node; the threshold compensation unit is used for compensating the noise reduction signal according to the threshold voltage of a transistor in the noise reduction execution unit to obtain a noise reduction compensation signal; the noise reduction control signal is compensated through the threshold compensation unit according to the threshold voltage of the transistor in the noise reduction execution unit, the problem of unstable noise reduction caused by threshold voltage drift of the noise reduction transistor is solved, and the noise reduction stability of the noise reduction circuit is improved.

The invention discloses an enhanced HEMT (High Electron Mobility Transistor) device, a preparation method, a chip and electronic equipment. The device structurally comprises a substrate layer, a buffer layer, a channel layer, a barrier layer and a cap layer, wherein the buffer layer, the channel layer, the barrier layer and the cap layer are sequentially positioned on the substrate layer; the passivation layer is located on the side wall of the cap layer and located on the upper surface of the barrier layer; the isolation structure is located on the side wall of the HEMT device, and the isolation structure penetrates through the barrier layer and the channel layer and is located on the buffer layer; the drain electrode and the source electrode respectively penetrate through the passivation layer and are positioned on the upper surface of the barrier layer; the grid electrode is located on the upper surface of the cap layer, and the contact interface of the grid electrode and the cap layer at least comprises ohmic contact and Schottky contact. Compared with the prior art, the hybrid gate HEMT device is formed by replacing a part of Schottky gate metal with ohmic gate metal in the gate structure of the HEMT device, so that the reliability and the stability of the threshold voltage of the gate of the p-GaN gate HEMT device can be effectively improved.

The dual inverter system includes a first inverter connected to one end of a stator coil of the motor and a second inverter connected to the other end. The controller can execute a dual mode in which the motor is driven by two inverters and a single mode in which the motor is driven by only one inverter. The controller closes the upper SW elements of all of the first and second inverters, opens all the lower SW elements, and closes the connection switch when the voltage at the DC end of the first inverter exceeds the threshold voltage. Alternatively, the controllers close all the lower SW elements of the first and second inverters to open all the upper SW elements and close the connection switches.

The invention discloses a flash memory data decoding method and device, electronic equipment and a readable storage medium, and relates to the technical field of data decoding, and the method comprises the following steps: obtaining a current data reading result of a storage unit through a current left offset reference voltage, a non-offset reference voltage and a right offset reference voltage in current reading voltages; if decoding of the current data reading result fails, the current left offset reference voltage is immediately and dynamically adjusted based on a preset offset, so that the adjusted first left offset reference voltage is smaller than the current right offset reference voltage to generate a first reading voltage; therefore, when the characteristic changes such as threshold voltage drift occur in the long-term use of the flash memory storage unit, the fixed reference voltage is not continuously used, the read voltage is flexibly adjusted, the decoding failure caused by insufficient voltage adaptation is avoided, and the decoding success probability is improved.

The invention relates to a display panel, a driving method thereof and a display device. The method comprises the following steps: acquiring a refreshing mode of a display panel at the current moment, resetting a driving transistor of the display panel by adopting a first reset voltage under the condition that the refreshing mode at the current moment is non-partitioned frequency division, and resetting the driving transistor of the display panel by adopting a second reset voltage under the condition that the refreshing mode at the current moment is partitioned frequency division. The second reset voltage is adopted to reset the driving transistor of the display panel, and the second reset voltage is different from the first reset voltage, so that the different reset voltages are adopted to reset the driving transistor of the display panel in different refresh modes of the display panel, namely, non-partitioned frequency division or partitioned frequency division; therefore, flicker caused by threshold voltage offset of the driving transistor when different refresh modes are switched is improved, and the display effect is improved.

In one embodiment, a method includes receiving DC bus voltage conditions of multiple AC to DC converters of an Input-Series-Output-Parallel power converter during a rectification stage; detecting a peak voltage of each of the DC bus of the multiple AC to DC converters has reached a first threshold voltage, and a Phase Loop Lock locked signal; upon detecting that the PLL locked signal, enabling a first voltage regulation to charge an AC to DC output of each of the multiple AC to DC converters to reach a first reference voltage; determining operating conditions including a load condition and an output voltage condition of multiple Dual Active Bridge (DAB) converters, and a monitored voltage of each of the multiple AC to DC converters; enabling a second voltage regulation of each of the multiple DAB converters to charge a DAB output to reach a second reference voltage based on the operating condition.

The invention provides a control method of storage equipment, the storage equipment and a computer storage medium. The method comprises the following steps: taking data read under initial threshold voltage as original data; symmetrically shifting the initial threshold voltage by taking the initial threshold voltage as a center, and reading data again as bias data; the mutually symmetrical bias data are logically processed, and judgment data are obtained; the original data and the judgment data are combined, a partition array is obtained, the credibility of the partition array is obtained through a lookup table, and the credibility and the accuracy of the judgment data are in positive correlation; the judgment data with high confidence reliability are preferentially judged, and the judgment data are decoded and processed; when decoding processing is started, the number of times of symmetrical offset initial threshold voltage is increased, and data are read again to serve as bias voltage data of the next round; and the step of obtaining the judgment data, the step of obtaining the credibility and the decoding process are cycled until decoding succeeds or the number of symmetric offset times reaches an offset time threshold value.

A controller, of a solid state drive (SSD), may perform, on one or more blocks of a non-volatile memory device of the SSD, read operations using pre-determined threshold voltages associated with two overlapped charge states. The read operations may be performed after a power-on condition following a power-off condition on the non-volatile memory device. The controller may determine, using a machine learning model, a change in threshold voltages associated with the two overlapped charge states, after the power-off condition. The machine learning model may determine the change in threshold voltages using bit error rates associated with the read operations. The machine learning model may be trained to determine changes in threshold voltages for the two overlapped charge states, after power-off conditions. The controller may determine adjusted threshold voltages associated with the two overlapped charge states based on the change in threshold voltages.

Disclosed are a chalcogenide-based memory material, and a memory device and an electronic device including the same. The chalcogenide-based memory material may include a ternary semiconductor compound having a composition represented by XaY 'bSec, where the chalcogenide-based memory material may have bidirectional threshold switching (OTS) characteristics, and a threshold voltage of the chalcogenide-based memory material may vary according to polarity and intensity of an applied voltage. In XaY 'bSec, X is not equal to Y, a + b + c = 1, egt, 0.12, bgt, 0.18, c > = 0.4, and X and Y' may independently be different ones of In, Sb, Ga, Sn, Al, Ge, Si, and P. The memory device may include the chalcogenide-based memory material, and the electronic device may include the memory device.

A LED circuit with a sequence function includes a load component, a capacitive component, a current load, and a voltage processor. The load component provides a resistance value. The capacitive component is connected to the load component in series at anode. The capacitive component provides a capacitance value, and generates an inner voltage at the node. The current load is connected in parallel to the load component and the capacitive component to provide a current path. The voltage processor receives the inner voltage and a threshold voltage, and compares the inner voltage with the threshold voltage to generate a comparison signal. The LED circuit counts time to acquire a time value from a starting time when the voltage processor starts to generate the comparison signal to a time when a level of the comparison signal changes, and uses the time value for sequencing.

The invention discloses a flash memory threshold distribution offset optimization method and device and a storage medium, and relates to the technical field of memorizers, and the method comprises the following steps: obtaining working environment information of a storage unit of a flash memory device; inputting the working environment information into a preset target threshold offset prediction model to obtain a first threshold offset of the storage unit; and adjusting the initial threshold voltage range of the storage unit according to the first threshold offset to obtain a target threshold voltage range. The reliability and integrity of data can be improved, and the overall service life of the flash memory device is prolonged.

The invention discloses a charge control method and a digital control system based on a dual-active bridge resonant converter, and belongs to the technical field of dual-active bridge resonant converter control. According to the method, a resettable integrating circuit is used for sampling resonance current and converting the resonance current into integrating voltage which is in a linear relation with charge injection quantity, and an integrating capacitor is discharged and reset before each time of injection; superposing the integral voltage and the ramp voltage; comparing the superposed signal with a threshold voltage output by a current loop through a comparator, and when the superposed signal reaches a threshold value, triggering to generate a PWM signal and switching the working mode of the converter; a switching tube is controlled to act according to a PWM signal, a switching time sequence is dynamically adjusted, effective control over transmission power is achieved, and a digital control system for achieving the method is established. According to the method, rapid dynamic response, efficient power transmission and stable operation of the dual-active bridge resonant converter are realized by controlling resonance current integration and a switching time sequence, and the energy conversion efficiency and the system reliability are effectively improved.

The invention belongs to the technical field of power semiconductor device life prediction, and particularly relates to a SiC MOSFET life prediction method based on gate oxide layer aging. The method comprises the following steps: firstly, acquiring a real threshold voltage sequence under different working conditions through a SiC MOSFET accelerated aging test, and preprocessing the real threshold voltage sequence; then, a life prediction model is constructed based on the conditional generative adversarial network, and the life prediction model comprises a generator, a common discriminator, a conditional discriminator, a coding network and a reverse recovery network; enabling the working condition as a condition label and the preprocessed real threshold voltage sequence to sequentially pass through a coding network and a reverse recovery network to obtain a real threshold voltage sequence embedded with the working condition; using the working condition as a condition label and a randomly generated Gaussian noise sequence to pass through a generator to obtain an analog threshold voltage sequence embedded with the working condition; inputting the real threshold voltage sequence and the simulation threshold voltage sequence with the embedded working conditions into a common discriminator and a condition discriminator at the same time for discrimination; and finally, training the life prediction model, and generating a threshold voltage sequence under an expected working condition by using a trained generator. According to the method, the service life of the SiC MOSFET under different working conditions can be predicted offline, and the method is more applicable.

The invention relates to the technical field of electronic circuits, in particular to a threshold voltage control system and control equipment of a field effect transistor. Comprising a main feedback loop used for obtaining an actual value of a threshold voltage of a field effect transistor, comparing the actual value of the threshold voltage with a set value to obtain a deviation signal, and sending the deviation signal to a control module; the auxiliary feedback loop is used for collecting the current change rate of the field effect transistor and sending the current change rate to the control module; the control module is used for generating a control signal according to the deviation signal and the current change rate and adjusting the grid voltage of the field effect transistor according to the control signal so as to control the threshold voltage of the field effect transistor. According to the invention, the main feedback loop and the auxiliary feedback loop cooperatively collect the voltage deviation signal and the current change rate of the field effect transistor so as to dynamically adjust the grid voltage of the field effect transistor, thereby improving the control precision.

The utility model relates to a power semiconductor device, in particular to a power semiconductor device, an upper P-type cover layer and a lower P-type cover layer are designed, the high doping concentration of the first P-type cover layer at the lower layer ensures that the threshold voltage of the device can reach a higher value, and the opportunity that an enhanced device is mistakenly opened is reduced; the doping concentration of the upper second P-type cover layer decreases progressively from bottom to top in the vertical direction and decreases progressively from the middle to the left edge and the right edge in the horizontal direction, the doping concentration of the surface corner position is low, when the grid electrode is pressed in the forward direction, the depletion region of the surface corner is deep, the formed peak electric field is low, the design reduces the leakage current of the grid electrode, and the reliability of the grid electrode is improved. And the breakdown voltage and the reliability of the gate are improved.

A memory apparatus includes memory cells configured to store a threshold voltage and disposed in memory holes each defining a channel. The memory apparatus also includes a control means configured to apply a first erase voltage to the channel of each of the memory holes including the memory cells in a first loop of an erase operation. The control means verifies the threshold voltage of the memory cells being erased using a target erase verify level voltage and at least one high erase verify level voltage higher than the target erase verify level voltage. The control means slows erasing of ones of the memory cells in a second loop of the erase operation in response to the threshold voltage of the ones of the memory cells being erased being greater than the target erase verify level voltage and less than the at least one high erase verify level voltage.

Gate dielectric materials and related methods for stacked device structures such as a complementary field-effect transistor (CFET) are disclosed herein. An exemplary method includes forming a two-dimensional (2D) dielectric material over a semiconductor channel layer. In some embodiments, the method further includes depositing a gate dielectric layer over the 2D dielectric material. In some examples, the method further includes forming a metal gate electrode over the gate dielectric layer. In various embodiments, a dipole is formed substantially within the 2D dielectric material, where the dipole is configured to modulate a threshold voltage (Vt) of the semiconductor device.

A squelch detection device is provided. The squelch detection device receives first and second input signals and first and second threshold voltages. The squelch detection device determines a first common mode of the first and second input signals and a second common mode of the first and second threshold voltages. The squelch detection device averages the first common mode with the second common mode to produce an average common mode and sets the first common mode of the first and second input signals to the average common mode. The squelch detection device sets the second common mode of the first and second threshold voltages to the average common mode and determines a state of a squelch signal, indicative of whether the first and second input signals are attributable to noise, based on the first and second input signals and the first and second threshold voltages.