3089 results about "Threshold voltage" patented technology

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NAND architecture. Multi-bit weight values are stored encoded as sets of threshold voltages for sets of memory cells. A weight value is stored in multiple memory cells on the same word line and connected between a bit line and a source line, each of the memory cells programmed to one of multiple threshold voltages. When multiplying an input value with the weight value, the word line is biased so that, for at least one of the threshold voltages, the memory cell will be in the linear operation region. Input values are encoded as a set of one or more voltage levels applied to a corresponding set of bit lines, each bit line connected memory cells also storing the weight value, connected to the word line, and connected to the source line.

A LED circuit with a sequence function includes a load component, a capacitive component, a current load, and a voltage processor. The load component provides a resistance value. The capacitive component is connected to the load component in series at anode. The capacitive component provides a capacitance value, and generates an inner voltage at the node. The current load is connected in parallel to the load component and the capacitive component to provide a current path. The voltage processor receives the inner voltage and a threshold voltage, and compares the inner voltage with the threshold voltage to generate a comparison signal. The LED circuit counts time to acquire a time value from a starting time when the voltage processor starts to generate the comparison signal to a time when a level of the comparison signal changes, and uses the time value for sequencing.

The invention relates to the technical field of MOS transistors, and discloses a low-power-consumption operation control method, device and equipment of an MOS transistor and a storage medium, and the method comprises the steps: collecting the working state feature data of the MOS transistor; performing change trend analysis on the working state characteristic data to obtain a current power consumption state and a power consumption fluctuation range; executing optimal threshold voltage adjustment parameter calculation based on the current power consumption state and the power consumption fluctuation range to obtain a target threshold voltage value; executing body bias control and grid voltage compensation according to the target threshold voltage value to obtain a body bias voltage control signal and a grid voltage control signal; and the power supply voltage and the working frequency of the MOS transistor are dynamically adjusted according to the body bias voltage and the grid voltage control signal, a voltage frequency working point is obtained, the sudden load change is rapidly responded, meanwhile, all control parameters are accurately adjusted, and the global optimal operation state of the MOS transistor is achieved.

The invention discloses a dynamic self-adaptive NAND Flash reading method and system based on artificial intelligence, a medium and equipment, and relates to the technical field of solid-state storage, the method comprises the following steps: S1, initiating a reading request, reading page data by using default voltage, decoding the page data through an LDPC algorithm, constructing a feature vector and performing preprocessing, inputting the voltage into a pre-trained neural network model, and carrying out voltage prediction; s2, carrying out fine sampling on the predicted voltage, reconstructing accurate threshold voltage distribution, and calculating a log-likelihood ratio; s3, designing a shared bottom layer backbone network, enabling a neural network model to have independent output branches, predicting the voltage, and evaluating the long-term health state of the block; and S4, designing an online transfer learning mechanism, and enabling the neural network model to quickly adapt to a new environment by using a small amount of new data. According to the method, the delay is greatly reduced, the power consumption is remarkably saved, data loss is prevented through early warning of bad blocks, and the write amplification factor is reduced to 1.26 through dynamic read interference suppression.

The invention discloses a security storage chip energy consumption optimization method based on multi-objective optimization, and relates to the technical field of energy consumption optimization, and the method comprises the steps: inputting the threshold voltage distribution characteristics of a security storage chip of a candidate parameter set into an aging model, fitting the rule of the threshold voltage distribution characteristics along with the time under an accelerated aging condition, and obtaining an aging model; aging model parameters are obtained; calculating the data retention failure rate of the security storage chip in the target life cycle by using the aging model parameters, and obtaining an extended feasible region of the instant erasure security constraint and the long-term retention security constraint in combination with a data retention judgment standard; and establishing a multi-objective optimization function with reduction of operation energy consumption and maintenance energy consumption as optimization objectives in the extended feasible region, and obtaining a candidate solution set through a multi-objective optimization algorithm. According to the method, data retention prediction in the life cycle is realized, and energy consumption optimization and long-term reliability constraint are combined.

The embodiments of the present disclosure disclose a memory and system, a programming method, the method comprising: applying an Nth pulse to a selected memory cell with a target state of an i-th state; after applying the Nth pulse, performing a first sub-verification and an Nth second sub-verification on the selected memory cell, obtaining a first sub-result and an Nth second sub-result; the first sub-result indicating whether the threshold voltage of the selected memory cell is less than a preset voltage, and the Nth second sub-result indicating whether the threshold voltage of the selected memory cell is less than a target threshold voltage of the i-th state; determining, according to the Nth second sub-result, a memory cell that needs to be applied with an N+1th pulse among the memory cells with the target state of the i-th state; the difference between the N+1th pulse and the Nth pulse being greater than or equal to the difference between the target threshold voltage and the preset voltage; applying the N+1th pulse to the memory cell that needs to be applied with the N+1th pulse; after applying the N+1th pulse, when the first sub-result indicates that the number of failed bits of the first sub-verification is less than a first preset value, determining that the programming of the i-th state is passed.

A method of encoding and decoding downlink instructions based on mud flow rate includes an encoding method and a decoding method. The encoding method and the decoding method are configured to transmit and receive instructions by controlling the mud flow rate during drilling process. The method of encoding and decoding downlink instructions based on mud flow rate does not require a fixed threshold of voltage as a judgement standard for “0” and “1” symbols, but uses voltage change rate as a standard for judging the level transition, avoiding decoding failure caused by the inability of voltage sampling values to reach the fixed threshold after well depth is increased.

The invention relates to the technical field of integrated circuits, in particular to a simulation test method and device for a semiconductor device. The method comprises the following steps: acquiring simulation parameter information of a first target device, wherein the simulation parameter information of the first target device comprises a first nuclear blocking correction parameter value; performing a simulation test based on the simulation parameter information of the first target device, and obtaining simulation transverse ion doping concentration distribution and a simulation threshold voltage value of the preset region; updating simulation parameter information of the first target device; performing a simulation test based on the updated simulation parameter information of the first target device, and obtaining another simulation transverse ion doping concentration distribution and another simulation threshold voltage value of the preset area; and taking the simulation threshold voltage value with the highest matching degree with the actual threshold voltage value of the first target device in all the simulation threshold voltage values as a target threshold voltage value, and determining the simulation transverse ion doping concentration distribution corresponding to the target threshold voltage value as target transverse ion doping concentration distribution.

A 3D semiconductor device including: a first level with first transistors, a single-crystal layer and at least one metal layer which includes interconnects between the first transistors forming first control circuits with a plurality of sense amplifiers; the first metal layer(s) overlaid by a second metal layer which is overlaid by a second level which includes first memory-cells which include second transistors with a metal-gate, overlaid by a third level which includes second memory cells which include third transistors which control the data written to second memory cells; a fourth metal layer overlaying a third metal layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within greater than 0.2 nm error, the first transistors or the second transistors comprise at least two FinFet transistors, and two of the FinFet transistors each have different threshold voltages.

A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: determining whether a workload change associated with a segment of the memory device satisfies a first threshold criterion for triggering an offset bin update; responsive to determining that the workload change satisfies the first threshold criterion, performing a calibration measurement of a center of a voltage valley for each state of each cell in the segment of the memory device; repeating the calibration measurement until a result of the calibration measurement is less than or equal to a threshold value; and updating a threshold voltage offset bin associated with the segment of the memory device based on the result of the calibration measurement.

The invention provides an enhanced HEMT (High Electron Mobility Transistor) device based on a P-type GaN grid electrode and a manufacturing method, a superlattice pair insertion layer is formed in a P-type GaN layer, the superlattice pair insertion layer comprises a first sub-layer and a second sub-layer which are alternately stacked, one of the first sub-layer and the second sub-layer adopts a GaN layer, and the forbidden bandwidth of the other layer is greater than 3.4 eV; by arranging the superlattice pair insertion layer, an electron barrier can be formed in the P-type GaN layer, and electrons can be prevented from moving in the gate structure, so that gate electric leakage is reduced, meanwhile, the electrons are prevented from crossing the gate structure to bombard the metal gate, and the gate reliability is improved; meanwhile, due to the fact that the ultra-thin superlattice material and the material with the forbidden bandwidth larger than 3.4 eV are AlN, BN, AlGaN, InAlN or BGaN, the dielectric constant of the material is very close to that of a GaN-based material, and therefore the gate capacitance and the threshold voltage of the device cannot be increased.

According to the junction field effect transistor device, the preparation method thereof and the electronic equipment provided by the invention, the threshold voltage of the device can be controlled through the low-voltage JFET channel region (namely the first horizontal part) formed by the first P-type ion implantation. Meanwhile, the size of the vertical channel (namely the first vertical part) is determined through first P-type ion implantation, groove etching is carried out in an implantation region, the size of the etched vertical channel and the size of the P-type gate (namely the second P-type region) are decoupled, and the influence of vertical channel etching on threshold voltage and drain breakdown voltage is avoided. Moreover, the gate ohmic contact layer is formed in the trench region (namely above the second horizontal part) to be connected to the gate of the device, so that the gate-drain capacitance CGD of the device can be reduced, the input capacitance and gate charge of the device are reduced, the switching speed of the device can be improved, the switching loss of the device is reduced, and the switching performance of the device is improved. The method is very suitable for the common direct drive type application of the high-voltage normally-open JFET.

The invention relates to a p-type niobium oxide dipole-based metal-oxide-semiconductor device and a manufacturing method thereof, and belongs to the technical field of semiconductor device manufacturing. According to the technical scheme, the MOS device is provided. A gate dielectric stack of the MOS device sequentially comprises an interface layer, a high-k dielectric layer and a p-type electric dipole layer containing niobium oxide from bottom to top. According to the preparation method, the dipole layer is deposited by adopting an atomic layer deposition process, and then atoms in the dipole layer are driven to be diffused to the interface of the high-k dielectric layer and the interface layer through high-temperature rapid annealing treatment so as to form effective electric dipoles. Compared with the prior art, the high dielectric constant characteristic is utilized, the threshold voltage can be positively regulated and controlled to a larger extent, meanwhile, the increase of EOT is remarkably inhibited, and good interface quality is kept.

The invention belongs to the technical field of display driving, and particularly relates to a gate driving unit, a gate driving circuit, a compensation method and a display panel, and the gate driving unit comprises a detection module which is used for detecting actual electrical parameters on a driving control node in a detection stage, the external control device outputs a compensation signal according to a comparison result of the actual electrical parameter and a preset reference range; or / and a compensation module which is configured to be connected with the external control device, the output end of the pre-charging module and the driving control node, and is used for responding to a compensation signal output by the external control device, compensating the pre-charging voltage output by the pre-charging module and then outputting the pre-charging voltage to the driving control node; through real-time comprehensive detection and dynamic cooperative compensation, the influence of threshold voltage drift of the pre-charge transistor and the output transistor on the driving control node is actively counteracted, and the output stability of the gate driving unit is improved.

The invention relates to the technical field of storage, and discloses a threshold voltage processing method of a solid state disk, a data reading method and related equipment. The threshold voltage processing method comprises the following steps: selecting a crystal grain in a frequent rereading state in a solid state disk as a target crystal grain; obtaining the optimal threshold voltage of the target crystal grain; and setting the optimal threshold voltage as the threshold voltage of all the blocks in the closed state in the target crystal grain. According to the method, the threshold voltage deviation problem of the solid state disk can be compensated, the read-write performance of the solid state disk under the scenes of data retention, read interference, cross temperature and the like is effectively stabilized, performance reduction and stability fluctuation caused by repeated rereading are reduced, the data reading efficiency is remarkably improved, the maintenance cost is reduced, and the service life of the solid state disk is prolonged. Reliability of the solid state disk is further improved, and service life of the disk is prolonged.

The invention relates to the technical field of electronic circuits, in particular to a field effect transistor dynamic threshold voltage measuring method and system. The method comprises the following steps: generating a high-speed pulse signal with preset rise time through a pulse signal generator; applying the high-speed pulse signal to the grid electrode of the field-effect tube to be tested, and collecting the voltage waveform of the grid electrode of the field-effect tube through an oscilloscope, and recording the voltage waveform as a grid electrode voltage waveform; the current probe monitors the current response of the drain electrode of the field effect transistor in real time, the current response is recorded as drain electrode current response, and the sampling rate of the drain electrode current response is synchronous with the sampling rate of the grid voltage waveform. According to the invention, the channel establishment delay is quantified in situ on the electrical characteristic, so that the threshold voltage is redefined by the potential at the completion moment of the channel formation, and the concealment of the transient characteristic caused by direct current slow scanning is eliminated.

Disclosed are methods and systems for suppressing extreme voltage surges due to transient electromagnetic energy disturbance such as a detonation of a nuclear weapon at high altitude generating an EMP (HEMP) comprising E1, E2, and E3 component pulses. Surge protection assemblies form a surge protection device (SPD) mounted directly on AC and DC power line conductors with embedded overcurrent protection. The inline mounted SPD eliminates connecting wire leads, propagation time delay response, and voltage drops due to wire inductance, providing accurate clamping level responses. The protecting assemblies are selected and coordinated to achieve a predefined response to react at protection threshold voltage levels and with current capacity to mitigate complex components of HEMP. The tertiary protection assembly disconnects an electrical load after a prolonged overvoltage is present associated with a Geomagnetic disturbance and reconnects the electrical load when an overvoltage condition is not present.

The invention provides a liquid leakage detection circuit, a mainboard and a liquid cooling server, and relates to the technical field of liquid cooling server design. The circuit comprises a differential signal generation module, a signal comparison module and a logic judgment module, the differential signal generation module comprises two liquid leakage detection cables, one liquid leakage detection cable is connected to a power supply voltage through a pull-up resistor, the other liquid leakage detection cable is grounded through a pull-down resistor, the two detection cables form a differential wiring pair in a PCB layout, and the signal comparison module is connected with the logic judgment module. The signal generator is used for generating differential detection signal pairs; the input end of the signal comparison module is connected with the detection cables, and the signal comparison module is used for outputting a differential voltage signal corresponding to the impedance change between the two detection cables based on the signal pair; and the logic judgment module is connected with the output end of the signal comparison module and is used for judging whether liquid leakage occurs or not based on the differential voltage signal and a preset threshold voltage signal. By adopting the differential signal design, noise interference can be reduced, and the problem of liquid leakage false alarm caused by noise interference is remarkably improved.

The invention discloses a display panel and a display device. The display panel comprises a substrate and a plurality of pixel circuits located on the substrate. Each pixel circuit comprises a first capacitor and a second capacitor; the first capacitor comprises a first capacitor electrode and a second capacitor electrode, the second capacitor comprises a third capacitor electrode and a fourth capacitor electrode, the third capacitor electrode is electrically connected with the second capacitor electrode, and the fourth capacitor electrode is configured to receive a constant voltage signal. The overlapping area of the first capacitor electrode and the second capacitor electrode is different from the overlapping area of the third capacitor electrode and the fourth capacitor electrode. According to the overall layout design of the pixel circuit, the compensation effect of the threshold voltage is better, and meanwhile the size and the pixel resolution of the display panel are comprehensively considered.

A method includes charging a battery of a vehicle to a charge threshold voltage. The method also includes discharging the battery from the charge threshold voltage to a post-task voltage by performing a travel task using the vehicle. The method additionally includes determining that a battery calibration condition has been met. The method further includes, based on determining that the battery calibration condition has been met, discharging the battery from the post-task voltage to a discharge threshold voltage by performing a battery discharge task. The method yet further includes determining a capacity of the battery based on a first electrical output of the battery during the travel task and a second electrical output of the battery during the battery discharge task.

Wireless circuitry may include a transmission line that carries a signal and a power detector that measures the signal. The detector may include a rectifier coupled to a comparator over a differential path. An offset calibrating digital-to-analog converter (OSDAC), a reference generator, and a multiplexer may be disposed on a negative line of the differential path. The OSDAC may produce an offset-compensated voltage by adding different offset voltages to a voltage on the second line over time. The reference generator may generate a set of threshold voltages by adding different reference voltages to the offset-compensated voltage. A temperature sensor may adjust the reference voltages used to generate the threshold voltages based on a temperature of the power detector. The multiplexer may route different threshold voltages to a negative input of the comparator.

Control logic in a memory device executes a programming operation to program a memory cell of a set of memory cells to a programming level. A first erase sub-operation is executed to erase the memory cell to a first threshold voltage level, the first erase sub-operation including applying, to the memory cell, a first erase pulse having a first erase voltage level. A second erase sub-operation is executed to erase the memory cell to a second threshold voltage level, the second erase sub-operation including applying, to the memory cell, a second erase pulse having a second erase voltage level, where the first erase voltage level of the first erase pulse is lower than the second erase voltage level of the second erase pulse.

This disclosure is directed to column driver circuitry of a memory device. A memory bank of the memory device may include multiple memory cells arranged along multiple column select lines and row select lines. The column driver circuitry may include column drivers coupled to the column select lines. A column driver may generate a column select signal with multiple voltage steps for accessing a target memory cell coupled to a respective column select line. The column decoder may include circuitry to adjust a voltage level and / or duration of each voltage step of the column select signal to provide a desired voltage level to a target memory cell based on a disposition of the target memory cell along a column select line. For example, the column decoder may output a higher voltage level followed by a lower voltage level to access the target memory cell. The higher voltage level and the lower voltage level may be above a threshold voltage level for accessing the target memory cell.

A method for verifying a low-density parity-check (LDPC) unit capable of being applied in a memory system can include receiving original data corresponding to a memory device, encoding the original data by the LDPC unit to be verified, injecting errors into the encoded original data by a data pattern for generating verifying data, and verifying a soft decode capability of the LDPC unit by utilizing the verifying data. The data pattern can include the errors generated by threshold voltage (Vth) distributions interlaced between two neighboring logic states of 2n logic states of the memory device. The method and system can provide an error injection to accurately and efficiently verify a LDPC soft decode capability of the LDPC unit, decrease errors, increase error correction accuracy and efficiency, more accurately model actual threshold voltage (Vth) distributions, increase flexibility, increase speed, increase performance, and reduce firmware overhead.

An AC-AC converter is provided. The AC-AC converter includes a primary circuit, a secondary circuit, a transformer, a resonant tank, and a controller. The primary circuit includes four bidirectional switches, each including upper and lower switches connected back-to-back and capable of operating in four quadrants in a voltage-current plane. The first and fourth bidirectional switches operate synchronously, and the second and third bidirectional switches operate synchronously. When the input voltage is greater than a predefined threshold voltage, the first and second lower switches are maintained in an on state, and the first and second upper switches operate with PWM signals and are complementary to each other. When the input voltage is smaller than an additive inverse of the predefined threshold voltage, the first and second upper switches are maintained in the on state, and the first and second lower switches operate with PWM signals and are complementary to each other.

The invention provides a charging activation device, an energy storage system and an activation method thereof, and belongs to the technical field of energy storage systems. The charging activation device comprises a standby battery pack, a boost inverter circuit, a voltage acquisition circuit and a microcontroller unit. Wherein the standby battery pack is used for providing a power supply for the boost inverter circuit and the microcontroller unit; the boost inverter circuit is used for boosting the input voltage to an activation voltage threshold of a battery management system of the energy storage system; the voltage acquisition circuit is used for acquiring the output voltage of an energy storage battery of the energy storage system; when the microcontroller unit detects that the energy storage system is in a locked state, the microcontroller unit can control to open the boost inverter circuit so as to boost an input voltage of the boost inverter circuit to an activation voltage threshold of a battery management system of the energy storage system and output the input voltage, so that the battery management system recovers a charging and discharging loop, and the energy storage system is activated. Automatic wakeup of the energy storage battery in the dormant state can be achieved, manual intervention is not needed, and dependence on manpower or external equipment is eliminated.

This invention discloses a pixel circuit, its driving method, and a display panel. The pixel circuit includes a driving module, a data writing module, a first initialization module, a storage module, a compensation control module, and a light-emitting module. The driving module includes a dual-gate transistor, and the dual-gate transistor and the light-emitting module are connected via a first power line and a second power line. The data writing module is connected between the first gate of the dual-gate transistor and a data line. The storage module is connected to the first gate, second gate, and second terminal of the dual-gate transistor, respectively. The compensation control module is connected between the first terminal and the second gate of the dual-gate transistor. The first initialization module is used to transmit a first initialization voltage on a first initialization signal line to the first gate of the dual-gate transistor and the first terminal of the light-emitting module. The technical solution provided by this invention can compensate for threshold voltage fluctuations over a large range, which is beneficial for improving display performance.

The invention discloses a selector unit for dynamic switching of a standard unit, a ring oscillator and a test structure. Wherein the selector unit is connected in parallel with standard units with different threshold voltages, driving capabilities and logic functions, and is matched with the first switch control circuit, so that flexible switching of the differentiated standard units is realized, and the static architecture limitation of a traditional test circuit is broken through; according to the ring oscillator, a selector unit is embedded into a closed oscillation loop of a standard unit chain, a time sequence path of multiple unit combinations is formed through dynamic configuration, and the delay superposition effect between mixing units in an actual circuit is effectively simulated; the test structure is based on the configurable characteristic of the ring oscillator, combines a pin sharing mechanism of the first control signal multiplexing module, realizes parallel test of multiple unit combinations in a single chip, and eliminates multi-chip separate test requirements, so that a high-efficiency and high-coverage standard unit delay detection system is realized under the constraint of hardware resources, and the test efficiency is improved. And a verification basis is provided for deviation analysis of the process simulation model.

An integrated circuit is provided for driving the gate of a GaN power switch transistor in a switching power converter. During a first portion of an on-time period for the GaN power switch transistor, the integrated circuit charges the gate through a relatively high pull-up resistance. During a second portion of the on-time period, the integrated circuit charges the gate through a relatively low pull-up resistance. During a first portion of an off-time period for the GaN power switch transistor, the integrated circuit discharges the gate through a relatively low pull-down resistance and then discharges the gate through a relatively high pull-down resistance in response a voltage of the gate falling below a threshold voltage.

A circuit includes a supply node receiving a supply voltage; an output node providing a regulated voltage; startup circuitry coupled to the supply node; current generator circuitry coupled to the startup circuitry and producing a current; a bandgap node coupled to bandgap circuitry to receive a bandgap voltage; multiplier circuitry coupled to the bandgap node and the current generator circuitry to receive and apply scaling to the current; a first transistor providing a threshold voltage drop across the first and second transistor nodes; a first resistive element interposed between the first transistor and the bandgap node; a second resistive element coupled between ground and the second node of the first transistor; and an operational amplifier receiving a pre-regulated voltage as a function of the bandgap voltage, the threshold voltage across the first transistor, and a voltage drop across the first and second resistive elements.