1675 results about "Memory array" patented technology

Apparatuses, systems, and methods for bounded fault compliant metadata storage. Memory devices include a first data terminal and a second data terminal. As part of an access operation a first set of data and a first set of metadata may be sent / received across the first terminal and a second set of data and a second set of metadata may be sent / received across the second terminal. The first set of metadata may be stored in a first location and the second set of metadata may be stored in a second location in the memory array, such as a first and second column plane. The two locations may be remote from each other.

Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.

Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Apparatuses, systems, and methods for per row error correct and scrub (pRECS) information. There may be pRECS information associated with each row, and it may reflect a number of codewords stored along that row which were determined to include an error during error correct and scrub (ECS) operations. The memory may store the pRECS information in the memory array, for example, each row may store the pRECS information associated with that row.

Apparatuses, systems, and methods for adjustable write timing. Memory devices include a first data terminal and a second data terminal. As part of an access operation a first set of data and a first set of metadata may be sent / received across the first terminal and a second set of data and a second set of metadata may be sent / received across the second terminal. When a first setting is enabled, the first set of metadata may be stored in a first location and the second set of metadata may be stored in a second location in the memory array, such as a first and second column plane. The two locations may be remote from each other. When disabled, the metadata may be stored in a single location. A second setting may be used to adjust a write delay to account for different timing when the first setting is enabled vs disabled.

Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

To accelerate search speeds for approximate nearest neighbor searches of vector databases, compute-in-memory techniques using NAND memory structures are introduced. For each element of the database, a kernel of its M nearest neighbors is determined. For each vector of the database, both the vector and its kernel are programmed in the arrays of a NAND memory based accelerator card, so that the vectors will be written into the memory arrays both as themselves and also in kernels of vectors for which they are a nearest neighbor. Metadata, associating the locations of the kernel members with the correspond vector is also stored in the memory system. After determining the input's nearest neighbor at one level of search, the metadata is then used to locate that nearest neighbor's nearest neighbors and their distances to the input vector are then computed in parallel in a compute-in-memory vector-vector dot product multiplication.

The invention belongs to the technical field of storage and calculation integration, and particularly relates to a low-bit-width and high-energy-efficiency floating point storage and calculation integrated circuit based on a partial pre-alignment framework. The circuit comprises a memory array, a pre-calculation unit, an adder tree, a configurable arithmetic unit and a normalization unit, and supports mixed precision operation of FP8MACFP4 and FP8MACFP8. The method is characterized in that a partial pre-alignment strategy dominated by an activation value is adopted, the maximum index of the activation value is dynamically counted, the mantissa of the maximum index is aligned, and multiple partial pre-alignment intermediate results are pre-calculated and latched for reuse; in combination with a customized lookup table and a multiplexer, a pre-calculation result is directly selected to replace real-time multiplication and displacement; and through the reconfigurable hardware, the FP8MACFP8 high-precision operation is realized by utilizing the FP8MACFP4 unit combination. According to the method, complete online floating point multiplication and addition operation is realized, and excellent energy efficiency ratio and operation speed are obtained while high precision is kept.

The invention belongs to the technical field of chip design, and discloses a three-dimensional stacked heterogeneous in-memory computing system and a data interaction processing method thereof.The three-dimensional stacked heterogeneous in-memory computing system comprises a storage chip layer and an AI processing chip layer located below the storage chip layer, the storage chip layer is electrically connected with the AI processing chip layer, and the AI processing chip layer is electrically connected with the storage chip layer. The AI processing chip layer is of a heterogeneous storage and calculation integrated structure integrating an RRAM storage and calculation array and an SRAM storage and calculation array, and the RRAM storage and calculation array is used for storing system configuration data; and the SRAM memory array is used for writing read-write data of the memory chip layer and completing data processing in the array. According to the three-dimensional stacking heterogeneous storage and calculation integrated device, through heterogeneous cooperation of the RRAM and the SRAM storage and calculation integrated array, key problems existing in the prior art are fully balanced and considered, finally, the optimal design of a system architecture level is achieved, and core obstacles are cleared away for large-scale application of the three-dimensional stacking technology in the field of AI chips.

The invention provides a memory, an operation method of the memory and a memory system, and relates to the technical field of semiconductor chips. The memory comprises a memory array and a peripheral circuit coupled to the memory array, the memory array comprises memory blocks, and the memory blocks are coupled to the peripheral circuit through word lines. Wherein the storage block comprises a programmed storage unit and an unprogrammed storage unit, and the programmed storage unit comprises a first storage unit and a second storage unit. The peripheral circuit is configured to: perform a program operation on a third memory cell in the memory block, and apply a first voltage to a first word line coupled to the first memory cell at a first stage of a channel preparation stage of the program operation; and applying a second voltage to a second word line coupled to the second memory cell. Wherein the first word line is located between a third word line coupled with the third storage unit and the second word line, and the first voltage is larger than the second voltage.

A memory device includes a memory array including compressed zones including a first compressed zone including slots of a first slot size and a second compressed zone including slots of a second slot size; and a controller configured to compress a first data element received from a processing block and store the compressed first data element in a first slot of the slots of the first compressed zone based on a data size of the compressed first data element.

A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lower-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-second-tiers or a lower of the upper-second-tiers comprises non-stoichiometric silicon dioxide that has a silicon-to-oxygen atomic ratio greater than 0.5. A higher of the upper-second-tiers that is above said lower upper-second-tier comprises silicon dioxide that has a silicon-to-oxygen atomic ratio less than or equal to 0.5. Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-second-tier or said lower upper-second-tier. After the stop, the sacrificial material is removed from the lower channel openings and channel-material strings are formed in the upper and lower channel openings. Other embodiments, including structure independent of method, are disclosed.

The invention relates to the technical field of semiconductors, and provides a memory and an operation method thereof, which are used for relieving harm caused by line hammering. The memory comprises a memory array and a control circuit. The control circuit is configured to enter a first mode in response to a command address signal and a mode control signal when a preset condition is met, execute an updating operation on a counting storage unit corresponding to an activated word line at a first moment, execute a pre-charging operation on the activated word line at a second moment, and take counting data as a counting value of row hammer refreshing; or, responding to the command address signal and the mode control signal when the preset condition is not met, entering a second mode, not executing the updating operation on the counting storage unit corresponding to the activated word line, and starting to execute the pre-charging operation on the activated word line at a second moment, and taking an activation count value of an activation word line in the dynamic lookup table as a count value of row hammer refreshing. In this way, balance is achieved between flexible configuration and reliability guarantee, and harm caused by hammering is relieved.

A compute-in-memory array is provided that implements a filter for a layer in a neural network. The filter multiplies a plurality of activation bits by a plurality of filter weight bits for each channel in a plurality of channels through a charge accumulation from a plurality of capacitors. The accumulated charge is digitized to provide the output of the filter.

A system includes a memory array, a temperature sensor including a temperature-dependent circuit, a ramp voltage source producing a ramp voltage that increases from a predefined starting value, and at least one processing device, operatively coupled with the memory array, the temperature sensor, and the ramp voltage source. The at least one processing device is to perform operations including determining a reference phase value reflecting a first amount of time for the ramp voltage starting at the predefined starting value to reach a reference voltage value, determining a sampling phase value reflecting a second amount of time for the ramp voltage starting at the predefined starting value to reach a temperature-dependent voltage value produced by the temperature-dependent circuit, and causing, based on the reference phase value and the sampling phase value, a temperature within the memory device to be determined.

Methods, systems, and devices for extended storage for zone metadata with user data in a memory system with a cache are described. The described techniques provide for a memory system to write data and a zone descriptor extension (ZDE) for a zone to a cache before flushing the data and the ZDE to a memory array, which may support re-writable ZDE information. The cache may be addressable using a logical-to-physical (L2P) table, and entries of the L2P table that map the ZDE in the cache may be included after entries of the L2P table that map user data in the cache, and the memory system may identify the current ZDE according to the L2P table region. When the zone is closed, the memory system may flush the data to the zone of the memory array and may migrate the last written ZDE information to a fixed location within the zone.

A tailored interactive language learning system that teaches an individualized set of vocabulary words to users through interactive avatars and stories. The interaction is modeled through probabilistic rules in a semantic network and neural network having objects and relations. Dialog and narration is generated dynamically based on the state of the interactive story model using phrasal rewrite rules and neural network implementiung a four-valued logic system in which truth values of the objects and relations are encoded as true, false, defined, and undefined in a single memory array.

The disclosure describes a read-only memory array and a read-only memory thereof. The read-only memory array includes common-source lines, word bit lines perpendicular to the common-source lines, and sub-memory arrays. The common-source lines include a first common-source line and a second common-source line. The word bit lines include a first word bit line and a second word bit line. Each sub-memory array includes four memory cells. Each memory cell has a control terminal coupled to the corresponding word bit line and a data terminal coupled to the corresponding common-source line and the corresponding word bit line. The read-only memory includes a field-effect transistor and a capacitor formed in a semiconductor region. The field-effect transistor and the capacitor commonly include a doped well. The doped well, overlapping the common-source line, is coupled to the common-source line.

A microelectronic device includes a first memory array structure including a first array region including first memory cells within a horizontal area of the first array region, each of the first memory cells having a first access device and a first storage node device vertically underlying and coupled to the first access device, a first control circuitry structure vertically overlying and attached to the first memory array structure at a boundary of the first memory array structure vertically closer to the first access devices of the first memory cells than the first storage node devices of the first memory cells, and a first shield structure vertically interposed between the first memory cells of the first memory array structure and the first control circuitry structure.

A 3D semiconductor device including: a first level including a single crystal layer, a memory control circuit, a first metal layer, a second metal layer, and a third metal layer; connection of the first transistors comprises the first, and / or the second, and / or the third metal layer; a fourth metal layer disposed atop third transistors disposed atop second transistors disposed atop said first level; a memory array including word-lines and at least four memory mini arrays which include at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors (at least one with a metal gate) or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array; the memory control circuit includes first transistors and voltage regulators.

Methods of forming a microelectronic device include forming a memory array structure including an array region having volatile memory cells within a horizontal area of the array region, the volatile memory cells respectively comprising a vertical channel access device and a storage node device vertically underlying and coupled to the vertical channel access device, forming a control circuitry structure comprising control logic devices, and bonding the control circuitry structure to a surface of the memory array structure vertically closer to the vertical channel access devices of the volatile memory cells than the storage node devices of the volatile memory cells.

A semiconductor device according to the present disclosure includes a logic cell and a memory array including a plurality of memory cells. The memory cells and the logic cell are arranged in a row, and a first plurality of the memory cells are positioned closer to the logic cell than a second plurality of the memory cells. A frontside interconnect structure is disposed over the memory cells and includes a frontside bit line. The frontside bit line is coupled to each of the memory cells arranged in the row. A backside interconnect structure is disposed under the memory cells and includes a backside bit line. The backside bit line is coupled to at least the first plurality of the memory cells. The frontside bit line is coupled to the backside bit line through a source / drain feature of a pass-gate transistor of one of the first plurality of the memory cells.

Per-row recent and / or baseline error information for word lines may be stored along the word lines in some examples. In some examples, baseline error information may be stored in a fuse array. In some examples, the baseline error information may be loaded from the fuse array to a memory array. In some examples, based on the recent and / or baseline error information, the memory device may provide a post-package repair recommendation.

A memory device has a memory array including a memory segment to store weight data, a weight buffer coupled to the memory segment and configured to hold new weight data to be updated in the memory segment, a logic circuit, and a computation circuit coupled to an output of the logic circuit. The logic circuit further has a first input coupled to the memory segment by a bit line, and a second input configured to receive input data. The logic circuit is configured to generate, at the output, intermediate data corresponding to the input data and the weight data read from the memory segment through the bit line. The computation circuit is configured to, based on the intermediate data, generate output data corresponding to a computation performed on the input data and the weight data read from the at least one memory segment.

Apparatuses, systems, and methods for bounded fault compliance may include data packet definitions that cause metadata to be provided on a single DQ terminal in some examples. Metadata stored in different regions of a memory array are provided on different DQs in the data packet definition in some examples. The data packet definition may include empty or undefined portions in some examples. The data packet definition may cause the metadata to be output at a midpoint of a data burst in some examples.

The present disclosure is generally directed to broadcasting bank option information to one or more memory banks in a memory device. In some instances, bank option information can be associated with a trimming operation for a memory bank. Each memory bank in a memory array can receive bank option information on a per bank basis. The bank option information may be broadcast before, during, or after the broadcast of a line repair information (e.g., column repair information). The bank option information enables the operation of each memory bank to be uniquely improved or optimized.

A neural network accelerator can perform energy-efficient multiply-and-accumulate operations of a neural network by Booth encoding a stationary operand, such as weights, before a compute phase. The Booth-encoding circuitry generates and stores Booth encoded multipliers in a Booth encoded multiplier storage and a precomputed compensation value representing a sum of the compensation bits of the Booth encoded multipliers in a Booth compensation storage. Per-cycle Booth encoding and compute of the sum of the compensation bits are avoided during multiply-accumulate operations because Booth encoding is applied to stationary operands. The Booth encoder can be located at the periphery where the multiplicands are loaded onto the accelerator shared across multiple compute columns and / or tiles to amortize the Booth encoder area overhead. The Booth encoder supports reconfigurable operand bit widths (e.g., 16-, 8-, 4-, and 2-bit). The approach is applicable to single-instruction-multiple data (SIMD) arrays, systolic arrays, and analog / digital compute-in-memory arrays.

An apparatus is provided that includes a memory array including non-volatile memory cells configured to store weights of an artificial neural network, a bit line coupled to a plurality of the non-volatile memory cells, and an interface circuit coupled to the bit line, the interface circuit configured to amplify an output impedance of the memory array.