263 results about "Memory array" patented technology

Devices and methods are disclosed, including receiving, by a memory controller of a memory device, a memory request from a host device; collecting packet trace data from the memory request; including the packet trace data in a log stored in a memory array of the memory device; and returning the log to the host device.

A memory device, a memory system, and a fabrication method are provided. The memory device includes a first semiconductor structure including a memory cell array in a memory array region of the first semiconductor structure. The memory cell array includes an array of transistors and an array of storage units which connect to corresponding transistors. The first semiconductor structure further includes an isolation structure surrounding the memory array region and isolating the array of storage units in the memory array region from a contact region of the first semiconductor structure.

The application discloses a continuous resonator network computing method based on a resistive memory array, and belongs to the fields of semiconductors, analog computing and integrated circuits. The application sequentially decomposes resonator network computing into three parts of logic computing, matrix-matrix-vector multiplication operation and sign taking computing, and sequentially connects a feedback loop formed by a logic element, a resistive memory array and an operational amplifier to realize hardware, takes a voltage corresponding to a to-be-decomposed hyper vector as input, and obtains a voltage of a corresponding decomposition signal at an output end after the circuit is stable, so that self-convergent resonator network computing in a continuous time domain is realized. Compared with existing resonator network computing implementation schemes, the application can fully exert the performance advantages of analog computing, does not need discrete iteration and data transfer, thereby reducing hardware overhead and operation complexity, and greatly improving speed, energy efficiency and area efficiency.

A memory device includes a plurality of memory units and a global responder (RSP) unit. Each memory unit includes a memory array of memory cells arranged in rows and columns, and an RSP unit. The memory array receives horizontal input data rotated for storage as data candidates in columns of the array. At least one of the rows is a calculation row receiving per-bit-line Boolean AND operations between bits of a marker row and bits of a row of data of the data candidates. The RSP unit includes wired-OR circuitry operative on the calculation row to generate a responder signal indicating whether there is one cell in the calculation row having a predefined value identifying a data candidate in the memory array. The global RSP unit receives multiple responder signals, one from at least two of the RSP units, and performs Boolean OR operations on the multiple responder signals.

A defect detection method for a memory device is provided. The memory device includes a memory array. The memory array performs an access operation according to a reference voltage. The defect detection method includes: dividing the memory array into multiple memory blocks; adjusting a voltage value of the reference voltage to sequentially perform the access operation on the memory blocks, and receiving multiple defect counts of the memory blocks after the access operation; and judging a defect type of the memory blocks according to the defect counts.

This application relates to a method, apparatus, and memory for detecting memory failures. The memory failure detection method performs error detection on read data from the memory array to identify failed cells. When repair triggering conditions are met, a repair operation is performed on the failed cell. The success of the repair is verified. If successful, the failed cell is marked as a normal memory cell and continues to be used. If not, redundant cells are used to replace the failed cell. Performing repair operations on failed cells can repair soft-failure cells, avoiding the replacement of a large number of normal cells by redundant cells, thus consuming redundant resources. This allows limited redundant cells to replace unrepairable hard-failure cells, improving the effective utilization rate of redundant cells and preventing redundant resources from being prematurely consumed by repairable soft-failure cells, thus delaying the depletion rate of redundant resources and extending the working life of the memory.

A memory control unit of a memory device includes at least one hardware processor; and memory storing instructions that cause the at least one hardware processor to perform operations comprising: generating a scrambler seed and a logical block address (LBA) for a block of write data received by the memory control unit from a host device; generating a flash translation layer (FTL) to map the LBA to a physical address (PA); scrambling the block of data using the scrambler seed; encrypting the scrambler seed, the LBA, and the PA in the FTL using an encryption key; initiating writing a scrambled block of data and encrypted LBA and scrambler seed to a memory array; and decrypting the FTL using an incorrect encryption key in response to an erase command received by the memory control unit from the host device.

The present disclosure relates to the field of semiconductor, and provides a memory for reducing power consumption of the memory without increasing memory area. The memory comprises a memory array, a data transmission circuit and a peripheral circuit; the data transmission circuit is arranged between the memory array and the peripheral circuit for data transmission between the memory array and the peripheral circuit; wherein the data transmission circuit comprises a first data path and a second data path in a data transmission direction; a power supply end of the first data path is electrically connected to a first transmission line, and a ground end is electrically connected to a second transmission line; a power supply end of the second data path is electrically connected to the second transmission line, and a ground end is electrically connected to a third transmission line; wherein the first transmission line transmits a first power supply voltage, the second transmission line transmits a second power supply voltage, the third transmission line is electrically connected to a common ground end, and the voltage value of the first power supply voltage is greater than the voltage value of the second power supply voltage.

The present disclosure relates to a memory device having a leakage current verification circuit for minimizing leakage current. In one aspect, the memory device includes, but is not limited to, a memory array, a leakage current verification circuit, and a controller. The controller is configured to perform an erase operation for a first column of memory cells connected to a first word line; set a verification condition including a leakage current threshold; perform a leakage current verification operation for the first column of memory cells by comparing a leakage current of a cell in the first column of memory cells to the leakage current threshold; detect a failure of the first column in response to the cell having a leakage current higher than the leakage current threshold; and perform a post-write operation to repair the failure of the first column of memory cells.

Systems, devices, and methods for reducing Vpass disturb are provided. In one aspect, a semiconductor device includes a first deck and a second deck, each including memory cells coupled to corresponding word lines; and a peripheral circuit coupled to the memory array structure. For programming a first memory cell of the first deck, the peripheral circuit configured to: apply a first voltage to a first word line coupled to the first memory cell; apply a second voltage to a second word line of the first deck; apply a third voltage to a third word line between the first word line and a fourth word line of the second deck; and apply a fourth voltage to the fourth word line. The first voltage is greater than the second voltage, the second voltage is greater than the fourth voltage, and the fourth voltage is greater than the third voltage.

According to one embodiment, a processing apparatus for accelerating convolution operations comprises a memory array in which a plurality of elementary processing unit are arranged in an array structure, and an operation unit configured to temporarily store feature-map data, divide the feature-map data into predetermined units along a channel-axis direction according to a pixel-first mapping method, and deliver the divided data to the memory array in a manner of shifting the data according to a position of a kernel.

The application is a QUBO problem solving method based on analog computing circuit, belonging to the field of analog computing and integrated circuit.The method combines the mathematical mapping of QUBO problem with the physical evolution process of analog computing circuit, maps the quadratic term matrix in QUBO problem into the product of resistance value in programmable resistance memory array and output current of current source module, maps the linear coefficient vector into threshold voltage of each row comparator, and takes the output voltage of each row comparator on feedback loop as the output of corresponding logic of state variable to be solved in QUBO problem, and relies on the natural evolution process of voltage in the circuit to realize the solution of QUBO problem in one step.The application does not depend on external digital circuit to provide clock, but updates in continuous time, has the advantages of fast speed, less peripheral circuit and low power consumption, and is suitable for the application scene of QUBO problem which is sensitive to power consumption and requires high solving speed.

We provide peripheral circuit systems for memory devices and memory devices themselves. [Solution] In a memory device 10 including a memory and peripheral circuit system, the peripheral circuit system includes a first peripheral circuit 103 electrically connected to the memory array of the memory device and a second peripheral circuit 105 electrically connected to the memory array. The first peripheral circuit and the second peripheral circuit are arranged along the longitudinal direction Z.

Control logic in a memory device receives a request to perform a read operation to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored, and performs a first coarse valley tracking calibration operation on the segment of the memory array. The control logic further configures a read voltage level and one or more parameters associated with the read operation based on a result of the first coarse valley tracking calibration operation and performs a second fine valley tracking calibration operation on the segment of the memory array using the configured read voltage level and the configured one or more parameters.

The present application provides a semiconductor memory device. The security of data stored in the semiconductor memory device is improved. The semiconductor memory device includes a control circuit, a first word line, and a memory array including a first memory cell capable of storing n bits, the control circuit configured to perform first and second write operations in response to first and second write instructions from a memory controller external to the semiconductor memory device, to perform first and second read operations in response to first and second read instructions, and to control a threshold voltage of the first memory cell to be either one of two distributions including a first distribution and a second distribution arranged in order from low to high in voltage or two distributions including a third distribution and a fourth distribution, at least a portion of the third distribution being between the first distribution and the second distribution, by performing the first or second write operation. n n ​​

A computer implemented method for automated generation and verification of a technology specific logic model and a technology independent logic model of a memory array, the method at least comprising: having a first set of parameters; having a set of constraints, creating a second set of parameters; generating the technology independent model of the memory array wherein the second set of parameters and the set of constraints are used; generating the technology specific model of the memory array wherein the first set of parameters and the set of constraints are used; verifying the technology independent model and the technology specific model for equivalence on a sequential logic basis.

Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, an analog neural memory system includes an array of non-volatile memory cells arranged in rows and columns, with the columns arranged in physically adjacent column pairs. Within each adjacent pair, one column includes a cell storing a W+ value, and another column includes a cell storing a W- value. The adjacent cells in the adjacent pair store a differential weight W obtained according to the formula W = (W+) – (W-). In another embodiment, an analog neural memory system includes a first array of non-volatile memory cells storing W+ values ​​and a second array of non-volatile memory cells storing W- values.

Systems, devices, methods, and circuits for managing status output are provided. In one aspect, a semiconductor device includes: a memory array configured to store data and a circuitry coupled to the memory array and configured to execute a read operation in the memory array and output a read packet based on a result of the execution of the read operation. The read packet includes readout data and error information associated with the readout data. The error information is indicated by at least one of an error code or one or more secure codes in the read packet.

An apparatus can comprise a memory array comprising a plurality of strings of memory cells each comprising: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is configured to determine a cumulative amount of read disturb stress experienced by the first erase block by monitoring read disturb stress experienced by the first erase block due to: read operations performed on the first erase block; read operations performed on the second erase block; and program verify operations performed on the second erase block. The controller can perform an action on the first erase block responsive to the cumulative amount of read disturb stress experienced by the first erase block meeting a criteria.

A memory and its access method, and an electronic device, are disclosed. The memory includes at least one memory array, multiple bit lines extending along a third direction perpendicular to a substrate, and multiple common bit lines extending along a second direction parallel to the substrate. The memory array includes multiple memory cells arrayed along the first and second directions parallel to the substrate, and multiple word lines extending along the first direction. Bit lines in the same column distributed along the second direction are connected to the same common bit line, bit lines in different columns are connected to different common bit lines, and each bit line is connected to the common bit line through a first gating sub-circuit. The first gating sub-circuit is also connected to a first gating control line, and the first gating sub-circuit is configured to connect or disconnect the bit lines and the common bit lines according to the control of the first gating control line. The solution provided in this embodiment, where multiple bit lines are connected to a single common bit line, can reduce the number of sense amplifiers used in the memory.

This application is directed to reduced resistivity of access lines in a memory array. A first metal layer can be formed over a via configured to couple an access line of a memory array with a corresponding driver. The first metal layer can be oxidized, and subsequently a second metal layer can be formed over the oxidized first metal layer. One or more access lines of the memory device can be formed from the second metal layer, the oxidized first metal layer, or both.

The system may include a controller including a processor configured to execute program instructions, the program instructions causing the processor to execute a measurement recipe as follows: generate a conversion model for converting full-loop optical measurement data to short-loop optical measurement data, the short-loop optical measurement data including optical measurement data of a periodic memory array structure, the full-loop optical measurement data including optical measurement data of a complementary metal oxide semiconductor (CMOS) under-array (CuA) device, the CuA device including a CMOS structure under a replica of the periodic memory array structure, generate a measurement model for determining measurements of the CuA device, receive full-loop optical measurement data of the CuA device on a test sample, convert the full-loop optical measurement data to short-loop optical measurement data using the conversion model, and determine the values ​​of measurements of the periodic memory array structure on a test sample using the measurement model.

The present application relates to the technical field of electronics. Provided are a memory array and a manufacturing method therefor, and a memory and an electronic device, which are used for solving the problem of a capacitor structure in a memory having a low density of integration. The memory array comprises: a substrate, and a capacitor unit arranged on the substrate. The capacitor unit comprises a first electrode, a second electrode and a third electrode, wherein the first electrode, the second electrode and the third electrode all extend in the thickness direction of the substrate, the first electrode is arranged around the second electrode, and the second electrode is arranged around the third electrode. The capacitor unit further comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is arranged between the first electrode and the second electrode, and the second dielectric layer is arranged between the second electrode and the third electrode. The memory array is used for improving the density of integration of a capacitor structure.

A memory device including a memory array comprising a plurality of decks, a respective deck comprising a plurality of memory cells, a respective memory cell comprising a storage element comprising a chalcogenide material; wherein a first deck of the plurality of decks comprises first memory cells with storage elements deposited at a first initial composition of a plurality of elements; and a second deck of the plurality of decks comprises second memory cells with storage elements deposited at a second initial composition of the plurality of elements.

The application discloses a dynamic random memory unit and array, and belongs to the technical field of semiconductor memory. The application forms a memory unit by using a vertical ring gate write transistor based on an oxide semiconductor and a silicon-based read transistor, and integrates the memory unit into a memory array in a mode of sharing a source area of the read transistor, and the area overhead of the application is about 6F 2 , which effectively reduces the unit area overhead and improves the integration density of the memory array.

The present disclosure provides a memory integrated circuit and a manufacturing method thereof. The memory integrated circuit includes a plurality of memory arrays located in a plurality of chip regions of a semiconductor chip and a plurality of test structures located in a scribe lane region of the semiconductor chip. The plurality of memory arrays and the plurality of test structures each include a plurality of word lines and a plurality of insulating structures extending in a same direction. The plurality of insulating structures in each memory array are configured to define a plurality of capacitor contact structures. The plurality of insulating structures in each memory array are arranged at a first pitch, and the plurality of insulating structures in each test structure are arranged at a second pitch greater than the first pitch.

Systems, methods, and devices provide error correction in such nonvolatile memories. Methods include identifying a read operation associated with a nonvolatile memory array, performing a plurality of sensing operations on the nonvolatile memory array, the plurality of sensing operations comprising a plurality of comparisons between sensed values and reference values, and generating a plurality of data outputs based on the plurality of sensing operations. Methods further include generating a plurality of results based on the plurality of data outputs, wherein each of the plurality of results identifies a number of errors associated with at least one of the plurality of data outputs, and selecting a data output of the plurality of data outputs based, at least in part, on the identified number of errors.

A memory device can include one or more core dies and an interface die. A read clock signal having a first frequency may be generated on the interface die and provided to circuitry on the interface die. The read clock signal is provided from the interface die to the core die(s). Access operations (e.g., read operations) are performed on a memory array on at least one core die based on the read clock signal. The data read from the memory array(s) is provided to the interface die. A data clock signal having a second frequency is generated on the interface die based on the read clock signal. The read data is output from the interface die based on the data clock signal. In some instances, pulses in the data clock signal are aligned with rising and falling edges of the pulses in the read clock signal.

Various embodiments of this disclosure relate to low-power and fast memory reset. One memory reset method includes: pre-charging bit lines of a memory array; asserting a signal at a reset node to remove the pre-charge voltage; and selecting write drivers associated with bit lines, the bit lines being associated with columns of the memory array including memory cells to be reset; wherein the assertion signal at the reset node further causes a desired logic state to be applied to the input of the selected write drivers, causing those selected write drivers to change the logic state of the bit lines associated with those write drivers. The method continues to assert each word line associated with a row of memory containing the memory cells to be reset, to write the desired logic state to all memory cells to be reset in the column and row of memory during a single clock cycle, and then deasserting those word lines.

An apparatus comprising a memory array comprising word lines, bit lines, and memory cells, one or more of the memory cells coupled to an associated word line and an associated bit line and comprising active areas and shallow trench isolation (STI) structures adjacent to a base material. The word lines are in the active areas and STI structures and bit line structures are adjacent to the active areas and the STI structures and oriented perpendicular to the word lines. The bit line structures comprise bit lines and bit contacts. Cell contact structures are laterally adjacent to the bit line structures and comprise cell contacts comprising an epitaxial semiconductive material. One or more of the bit contacts and the epitaxial semiconductive material comprise a doped epitaxial silicon material, the doped epitaxial silicon material exhibiting a relatively greater dopant concentration in a [110] crystal orientation than in a [100] or [111] crystal orientation. Methods of forming the apparatus are also disclosed.