3018 results about "Memory array" patented technology

Apparatuses, systems, and methods for managing access to metadata stored at a memory. To manage access to metadata, a mode register is configured to receive a metadata enable setting and to provide a metadata enable signal based on the metadata enable setting. A metadata access control circuit configured to receive a column address identifying a particular column to be accessed within a memory array. The metadata access control circuit blocks access to a column corresponding to the column address when the column address matches one of a plurality of particular column addresses designated for storage of metadata and the metadata enable signal has a first value, and permits access to a column corresponding to the column address when the column address is different than every one of the a plurality of particular column addresses designated for storage of metadata or the metadata enable signal has a second value.

Apparatuses, systems, and methods for scalable 1-pass error correction code operations. A memory device includes an error correction code (ECC) circuit which generates a number of parity bits based on a plurality of data bits during a write operation. The number of parity bits may be selected based on a setting in a mode register. The data and parity are written to the memory array as part of a single access pass. The data may be written to a selected portion of the data column planes, while the parity is written to one or more column planes of the extra column plane or a non-selected portion of the data column planes.

Apparatuses, systems, and methods for bounded fault compliant metadata storage. Memory devices include a first data terminal and a second data terminal. As part of an access operation a first set of data and a first set of metadata may be sent / received across the first terminal and a second set of data and a second set of metadata may be sent / received across the second terminal. The first set of metadata may be stored in a first location and the second set of metadata may be stored in a second location in the memory array, such as a first and second column plane. The two locations may be remote from each other.

Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.

Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

A 3D semiconductor device including: a first level including a single crystal layer and a memory control circuit including first transistors and a redundancy control circuit; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors disposed atop the third metal layer with at least one including a metal gate; third transistors disposed atop the second transistors; a fourth metal layer atop the third transistors; a memory array including word-lines and at least four memory mini arrays, each including at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array.

Apparatuses, systems, and methods for per row error correct and scrub (pRECS) information. There may be pRECS information associated with each row, and it may reflect a number of codewords stored along that row which were determined to include an error during error correct and scrub (ECS) operations. The memory may store the pRECS information in the memory array, for example, each row may store the pRECS information associated with that row.

The invention discloses a memory test method and device based on an AI technology and a medium, and the method comprises the following steps: 1) obtaining structure analysis data and memory type description information of a to-be-tested memory, and generating a test intention vector used for expressing a test target; 2) taking the test intention vector as an input to generate a test excitation sequence; 3) executing the test excitation sequence, and performing multi-cycle test on the storage array to form a multi-modal response feature set; 4) inputting the multi-modal response feature set into a graph neural network, performing fault type identification and causal path reasoning, and generating a fault tag sequence and a reasoning path graph; 5) based on the characteristic difference between the inference path diagram and the test excitation sequence, weight parameter updating of the depth generation model is carried out; and 6) generating a test excitation sequence based on the updated depth generation model to test the memory. The intelligent level and the test coverage rate of the memory test can be effectively improved.

Apparatuses, systems, and methods for adjustable write timing. Memory devices include a first data terminal and a second data terminal. As part of an access operation a first set of data and a first set of metadata may be sent / received across the first terminal and a second set of data and a second set of metadata may be sent / received across the second terminal. When a first setting is enabled, the first set of metadata may be stored in a first location and the second set of metadata may be stored in a second location in the memory array, such as a first and second column plane. The two locations may be remote from each other. When disabled, the metadata may be stored in a single location. A second setting may be used to adjust a write delay to account for different timing when the first setting is enabled vs disabled.

Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

A microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure vertically overlying the first microelectronic device structure. The first microelectronic device structure comprises a first memory array region and a first control logic device region configured to effectuate control operations for memory cells of the first memory array region. The second microelectronic device structure comprises a second memory array region and a second control logic device region configured to effectuate control operations for memory cells of the second memory array region. Related memory devices, electronic systems, and methods are also described.

Embodiments of the disclosure are drawn to apparatuses, systems, and methods for activation counter initialization (ACI). A memory may be placed in an ACI mode. During the ACI mode, an ACI control circuit initializes the access count values of the memory array to an initialization value. For example, the ACI mode may work through the array on a row-by-row basis initializing the access count values along each of the rows. By controlling the initial state of the access count values, it is less likely to have a false aggressor alert because none of the access count values start at a randomly high number, simulating an aggressor even after a small number of accesses.

The invention relates to the technical field of monolithic integration, in particular to a monolithic three-dimensional integration implementation method and device for a hybrid precision in-memory computing architecture, and the method comprises the steps: obtaining a silicon-based CMOS technology and a subsequent integration technology in a monolithic three-dimensional integration technology; manufacturing a control logic circuit on the computing architecture in the mixed precision memory by adopting a silicon-based CMOS (Complementary Metal Oxide Semiconductor) process; a plurality of functional layers are vertically stacked on a logic circuit by adopting a back-end integration process, communication among the functional layers is realized through interlayer dielectric via holes in the vertical direction, an analog in-memory array, a digital in-memory array and a cache are arranged on the functional layers, the analog in-memory array realizes matrix and vector multiplication with fixed weight, and the digital in-memory array realizes matrix and vector multiplication with fixed weight. And the array in the digital memory realizes matrix multiplication of refresh weight. Therefore, the problems that an in-memory computing architecture usually needs to occupy a relatively large part of chip area, the computing efficiency is relatively low and the like in related technologies are solved.

To accelerate search speeds for approximate nearest neighbor searches of vector databases, compute-in-memory techniques using NAND memory structures are introduced. For each element of the database, a kernel of its M nearest neighbors is determined. For each vector of the database, both the vector and its kernel are programmed in the arrays of a NAND memory based accelerator card, so that the vectors will be written into the memory arrays both as themselves and also in kernels of vectors for which they are a nearest neighbor. Metadata, associating the locations of the kernel members with the correspond vector is also stored in the memory system. After determining the input's nearest neighbor at one level of search, the metadata is then used to locate that nearest neighbor's nearest neighbors and their distances to the input vector are then computed in parallel in a compute-in-memory vector-vector dot product multiplication.

The invention discloses a rapid aging test method and device for a memory array, and relates to the technical field of memory array test. Comprising the following steps: in a read-write operation process, capturing an instantaneous current waveform of each storage unit in a memory array, extracting current characteristics from the instantaneous current waveform, constructing a difference matrix by utilizing the extracted current characteristics, and dynamically marking the storage units exceeding a threshold value. According to the invention, by analyzing the difference of the stored data volume before and after the instantaneous current waveform capture of the storage unit, the capacity recession condition of the storage unit is evaluated, and the capacity recession data is used as an auxiliary evaluation index and combined with the aging rate of the storage unit. According to the invention, comprehensive evaluation of the aging degree of the memory units is completed without applying external influence conditions to the memory array, so that the accuracy of the aging test is improved, the aging difference between the memory units can be effectively identified, and the key memory units are ensured to be processed and maintained in time.

The invention belongs to the technical field of storage and calculation integration, and particularly relates to a low-bit-width and high-energy-efficiency floating point storage and calculation integrated circuit based on a partial pre-alignment framework. The circuit comprises a memory array, a pre-calculation unit, an adder tree, a configurable arithmetic unit and a normalization unit, and supports mixed precision operation of FP8MACFP4 and FP8MACFP8. The method is characterized in that a partial pre-alignment strategy dominated by an activation value is adopted, the maximum index of the activation value is dynamically counted, the mantissa of the maximum index is aligned, and multiple partial pre-alignment intermediate results are pre-calculated and latched for reuse; in combination with a customized lookup table and a multiplexer, a pre-calculation result is directly selected to replace real-time multiplication and displacement; and through the reconfigurable hardware, the FP8MACFP8 high-precision operation is realized by utilizing the FP8MACFP4 unit combination. According to the method, complete online floating point multiplication and addition operation is realized, and excellent energy efficiency ratio and operation speed are obtained while high precision is kept.

The invention discloses a memory operation method, a memory, electronic equipment and a storage medium. The memory operation method comprises the following steps: in response to an error detected in a memory array of the memory in a working state of the memory, determining an error position of the error in the memory array; after the memory enters the idle state, the memory is controlled to start a post-package repair process, and according to the error position, a target memory unit at the error position is replaced with a replacement memory unit used for the post-package repair process in the memory array; and after the post-package repair process, the memory is switched back to the working state, and the replacement memory unit is used for replacing the target memory unit for operation. The memory operation method can improve the reliability of the memory.

The invention belongs to the technical field of semiconductor devices, and discloses a novel semiconductor nonvolatile memory and a preparation method and application thereof. The memory comprises a substrate, a bottom electrode, an amorphous oxide interface layer, a ferroelectric dielectric layer and a top electrode which are sequentially arranged from bottom to top, the preparation method comprises the steps of (1) cleaning the substrate, (2) depositing the bottom electrode, (3) forming the amorphous oxide interface layer, (4) depositing the ferroelectric medium layer, and forming the ultrathin ferroelectric medium layer with uniform composition and good ferroelectricity on the amorphous MoO3 interface layer, (5) patterning and depositing the top electrode, and (6) performing rapid thermal annealing treatment. The memory is applied to a three-dimensional stacked nonvolatile memory array or construction of a back gate type ferroelectric transistor structure. According to the invention, the formation of a non-ferroelectric phase is effectively inhibited, the preferred orientation arrangement of the ferroelectric phase is promoted, the polarization intensity is enhanced, and the ferroelectric performance of the device is improved. The material has the advantages of low thermal budget, high process compatibility and excellent ferroelectric performance.

The invention relates to a memory and an operating method thereof. The memory comprises a memory array and an access interface for externally accessing the memory array, and the access interface comprises at least one data / address multiplexing line for transmitting data and addresses. The method comprises the steps that a specified random column access mode is started, in the mode, continuous read / write operation can be conducted on a storage array in response to a plurality of received access addresses, and the access addresses have the same row address and random column address; receiving a common row address and at least one column address via the data / address multiplexing line; an output unit configured to output data read in response to the received access address via the data / address multiplexing line in a case where the mode indicates a read operation, or receive data written in response to the received access address via the data / address multiplexing line in a case where the mode indicates a write operation; and ending the random column access mode by receiving an invalid chip enable signal. The scheme can improve the access speed of the memory.

The invention relates to a memory and an operating method thereof. The memory comprises a memory array and an access interface for externally accessing the memory array comprising at least one data / address multiplexing line for transmitting data and addresses. The method comprises the following steps: starting a specified fixed-number random access mode, and performing continuous read / write operation on a storage array in response to a plurality of received fixed-number random access addresses in the mode; sequentially and continuously receiving a preset fixed number of access addresses through the data / address multiplexing line; a control unit configured to sequentially and continuously output data read in response to the received access addresses via the data / address multiplexing line when the mode indicates a read operation, or sequentially and continuously receive data written in response to the received access addresses via the data / address multiplexing line when the mode indicates a write operation; and ending the mode by receiving an invalid chip enable signal. According to the scheme, the access speed of the memory can be increased.

The present disclosure provides a memory, a bit line control method and an electronic device, in a first chip of the memory, each memory array chip includes a plurality of memory layer groups stacked in sequence along a third direction, in the memory layer groups of odd numbers, each local bit line is coupled to a respective first common bit line via a respective bit line selector, and in the memory layer groups of odd numbers, each local bit line is coupled to a respective second common bit line via a respective bit line selector. Each local bit line is coupled to a respective second common bit line through a respective pre-charge switch; in the even-numbered storage layer group, each local bit line is coupled to a respective first common bit line through a respective pre-charge switch, and each local bit line is coupled to a respective second common bit line through a respective bit line selector.

The invention provides a memory, in the memory, for a memory array sheet at a non-head-and-tail position, each bit line is coupled to a corresponding pressure test power supply, and the pressure test power supply corresponding to a first bit line is different from the pressure test power supply corresponding to an adjacent second bit line; for the storage array sheets at the head and tail positions, the first bit lines are coupled to the corresponding pressure test power supplies, and the pressure test power supplies corresponding to the first bit lines with odd numbers are different from the pressure test power supplies corresponding to the first bit lines with even numbers.

A discrete three-dimensional (3-D) processor comprises vertically stacked and communicatively coupled first and second dice. The first die comprises memory arrays, while the second die comprises non-memory circuits and off-die peripheral-circuit components of the memory arrays. The total-number difference of the BEOL layers between the memory arrays and the off-die peripheral-circuit components is substantially larger than the total-number difference of the BEOL layers between the non-memory circuits and the off-die peripheral-circuit components.

Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

The present disclosure relates integrated chip structure. The integrated chip structure includes a memory array having a plurality of memory devices arranged in a plurality of rows and a plurality of columns. A word-line is coupled to a first set of the plurality of memory devices disposed within a first row of the plurality of rows. A bit-line is coupled to a second set of the plurality of memory devices disposed within a first column of the plurality of columns. A local interconnect extends in parallel to the bit-line and is coupled to the bit-line and two or more of the second set of the plurality of memory devices. The local interconnect is coupled to the bit-line by a plurality of interconnect vias that are between the local interconnect and the bit-line.

A memory device includes a memory array having a plurality of wordlines coupled with respective memory cells of the memory array. Control logic is operatively coupled with the memory array, the control logic to perform operations including: determining, prior to performing a read operation at one or more strings of the respective memory cells, a number of wordlines that are associated with memory cells that have been programmed; adjusting, based on the number of wordlines, a read level voltage for a selected wordline of the one or more strings that is to be read during the read operation; and causing, during the read operation, the adjusted read level voltage to be applied to the selected wordline.

Inrush current in a memory such as SRAM cache may be managed by using one or more integrated delay elements such as inverters, RC delay lines, and the like to significantly slow down power down signal propagation between memory instances in a memory array. The delay in some examples may be between memory instances, while in other examples the delay is also introduced between bitcell arrays within a memory instance. By staggering the power up times of interconnected or chained memory instances, inrush current when powering the memory instances on or resuming from an inactive state may be reduced.

A 3D memory array including multiple memory cells and a method of manufacturing the same are provided. Each memory cell includes a first isolation structure, source and drain electrodes, a gate layer, a channel layer and a memory layer. The source and drain electrodes are disposed on opposite sides of the first isolation structure, and the source and drain electrodes comprise kink portions. The gate layer is disposed beside the source and drain electrodes and the first isolation structure. The channel layer is disposed between the gate layer and the source electrode, the first isolation structure and the drain electrode, and the channel layer extends between the source and drain electrodes and covers the kink portions of the source and drain electrodes. The memory layer is disposed between the gate layer and the channel layer and extends beside the gate layer and extends beyond the channel layer.