110 results about "Write current" patented technology

According to one embodiment, a magnetic memory includes: a magnet configured to store data and shift the data from a first area to a second area by domain wall movement caused by a shift operation; an interconnect spaced apart from the magnet and configured to apply a write field to the magnet at a time of a write operation; and a control circuit configured to cause a shift current for shifting the data to flow in the magnet and to cause a write current for generating the write field to flow in the interconnect, wherein the write current includes a first pulse supplied to the interconnect and a second pulse supplied to the interconnect after the first pulse, and a pulse width of the second pulse is smaller than a pulse width of the first pulse.

The invention relates to the technical field of nonvolatile memories, in particular to a 2T1FC ferroelectric memory cell with a memory gate line and a preparation method of the 2T1FC ferroelectric memory cell. The 2T1FC ferroelectric storage unit with the storage gate line comprises a ferroelectric capacitor and a storage transistor which realizes read-write operation of data through polarization modulation of the ferroelectric capacitor; the control transistor is used for enabling a bit line to perform gating access; and the storage gate line is used for controlling the gate of the storage transistor and improving the holding capability of the written data. According to the invention, the special storage gate line is used, so that self-charge dissipation after writing is prevented, and the non-volatility is enhanced; separation of the storage path and the control path minimizes accidental flipping in the read / write cycle; the service life of the device is prolonged by lower write-in current stress and an isolated gate structure; low-voltage writing with high retentivity can be realized, and the method is suitable for energy-limited edge AI equipment.

A memory device includes a memory cell connected between first and second signal lines, a first wiring connected to the first signal line, a second wiring connected to the second signal line, and a precharging circuit connected to the first wiring. During a write sequence, the precharging circuit charges the first signal line and the first wiring, the memory cell is activated according to a voltage difference between the first signal line and the second signal line, and a write current generated from parasitic capacitances of both the charged first signal line and the charged first wiring flows from the first wiring to the second wiring via the activated memory cell.

The invention provides a magnetic storage element and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for solving the problem of low overturning efficiency of a free layer in the prior art. The magnetic storage element comprises a substrate, a spacing layer, a spin orbit moment layer and a magnetic tunnel junction which are sequentially stacked from bottom to top, and a first ferromagnetic structure and a second ferromagnetic structure which are independently arranged on two side walls of the spacing layer, the first ferromagnetic layer in the first ferromagnetic structure and the second ferromagnetic layer in the second ferromagnetic structure are opposite in magnetic moment direction, so that stray fields in opposite directions can be generated; the top surfaces of the first ferromagnetic structure and the second ferromagnetic structure are not higher than the top surface of the spin orbit moment layer and are electrically connected with the spin orbit moment layer to form a write-in path, and when write-in current flows through the first ferromagnetic structure or the second ferromagnetic structure, a stray field generated by the ferromagnetic structure through which the write-in current flows is weakened; a stray field generated by the ferromagnetic structure through which the write-in current does not flow assists the free layer in overturning, and the overturning efficiency of the free layer can be improved.

Provided is a semiconductor storage device for STT-MRAM in which the circuit area is reduced to achieve high density. A semiconductor storage device 1000 comprises a memory cell array 10 in which a plurality of memory cells 100 are arranged in rows and columns. Each memory cell 100 includes: a magnetic tunnel junction element capable of data writing by spin transfer torque due to write current; a first electrode of a topological antiferromagnetic material provided so as to supply the write current to the magnetic tunnel junction element; and a switch element SW00 for opening and closing a supply path of the write current to the magnetic tunnel junction element. The semiconductor storage device 1000 further comprises a plurality of first wires WL0, WL1 provided in the row direction of the memory cell array to control the opening / closing of the switch element SW00. The switch element SW00 is a transistor, and an active layer continuously provided in memory cells adjacent to each other in the column direction includes a channel region of each of a plurality of transistors.

The present embodiments can generally provide a magnetic write head structure with optimized gap current distribution to maximize the current-assisted areal density capacity (ADC) gain in hard-disk-drive storage devices. In a first example embodiment, a non-dual-write-shield (nDWS) write head can include a main pole (MP), a trailing shield (TS), and a write gap (WG) disposed between the MP and the TS. The write head can also include a side shield (SS), a leading shield (LS), and a write shield (WS). The write head can include a side gap (SG) between the MP and the SS on both sides of the MP tip, and a leading gap (LG) between the MP and the LS. The write head can also include a coil wrapped around the MP through a PP3 shield that is configured to direct a time-dependent write current to saturate magnetization of the MP.

A magnetoresistive effect element includes a reference layer, a barrier layer, a recording layer, and a channel layer that are disposed on top of one another, and a first terminal connected to the reference layer, and a second terminal and a third terminal connected to the channel layer. The channel layer includes a first channel layer and a second channel layer, the first channel layer has electrical resistance larger than electrical resistance of the second channel layer, the second terminal is connected to the first channel layer, and the third terminal is connected to the second channel layer, a write current flows between the second terminal and the third terminal via the first channel layer and the second channel layer, and a read current flows between the first terminal and the third terminal.

The application provides a SOT-MRAM and a manufacturing method thereof, the SOT-MRAM comprising a substrate, a plurality of memory cells arranged on the substrate. Each memory cell comprises a SOT layer deposited on the substrate, a magnetic tunnel junction arranged on the SOT layer. Further comprising an antiferromagnetic insulating layer at least wrapping around the side surface of the free layer in each magnetic tunnel junction, and the magnetic moment direction of the antiferromagnetic insulating layer is parallel to the direction of the write current in the SOT layer. By adding the antiferromagnetic insulating layer at least wrapping around the side surface of the free layer in each magnetic tunnel junction, and further making the magnetic moment direction of the antiferromagnetic insulating layer parallel to the direction of the write current, an in-plane magnetic field can be provided for the free layer, for the field-free switching of the SOT-MRAM, solving the problem that the SOT-MRAM cannot be mass integrated due to the need to apply an external magnetic field during the writing process. And the added antiferromagnetic insulating layer is arranged around the magnetic tunnel junction, thereby also having the effect of protecting the magnetic tunnel junction from the surrounding environment.

The present application provides a magnetic memory and a preparation method thereof, which relates to the field of semiconductor technology and is used to solve the technical problem of poor flexibility in data writing. The magnetic memory at least includes a first antiferromagnetic layer, a magnetic tunnel junction arranged on the first antiferromagnetic layer, and a second antiferromagnetic layer arranged on the magnetic tunnel junction; the magnetic tunnel junction includes a first magnetic layer, a barrier layer, and a second magnetic layer stacked in sequence from bottom to top; wherein, by applying a write current to at least one of the first antiferromagnetic layer and the second antiferromagnetic layer, the magnetization direction of at least one of the first magnetic layer and the second magnetic layer is flipped. The present application is used to improve the flexibility of data writing.

A data storage device comprises a magnetic medium and a head configured to be actuated over the magnetic medium. The head comprises a write element and a write driver configured to generate a write current to be applied to the write element. The write driver comprises a data switch section configured to switchably output low-level signals and high-level signals, and a stationary cascode section configured to receive the low-level signals and high-level signals from the data switch section and to generate a cascode pass through current. The data switch section comprises low voltage CMOS devices and the stationary cascode section comprises high voltage CMOS devices.

A magnetic domain wall movement element according to the present embodiment includes a magnetoresistance effect element that has a reference layer, a nonmagnetic layer, and a magnetic domain wall movement layer in order from a side closer to a substrate; and a first magnetization fixed layer and a second magnetization fixed layer which are each in contact with the magnetic domain wall movement layer and are separated from each other, wherein the magnetic domain wall movement layer includes a plurality of ferromagnetic layers and a plurality of insertion layers sandwiched between the plurality of ferromagnetic layers, wherein the ferromagnetic layer contains Co and Fe and has perpendicular magnetic anisotropy, and wherein, when writing is performed, a write current is allowed to flow between the first magnetization fixed layer and the second magnetization fixed layer along the magnetic domain wall movement layer.

The application provides a magnetic tunnel junction free layer and a magnetic tunnel junction structure with the same. The magnetic tunnel junction free layer comprises a first magnetic composite layer, an antiferromagnetic spacer structure and a second magnetic composite layer which are sequentially stacked along a first direction. The first magnetic composite layer and the second magnetic composite layer are in antiferromagnetic coupling under the action of the antiferromagnetic spacer structure, and the magnetization directions thereof are opposite. Since the above structure adopts a plurality of magnetic composite layers, the overall thickness of the magnetic layer is increased while the magnetization direction is controlled to be perpendicular to the film interface, thereby increasing the data retention capability of the device. In addition, in order to reduce the write current, the above structure makes the magnetization directions of different magnetic composite layers opposite, reduces the total magnetic moment of the overall structure, thereby reducing the write current and realizing high device erasing resistance. In addition, the structure can obtain a higher TMR, thereby improving the data reading speed.

A device includes a memristive element; and a write circuit to write the memristive element into a memristive state of a plurality of memristive states by a write operation, wherein the memristive state has a characteristic flux and / or a characteristic charge; wherein the characteristic flux corresponds to a characteristic voltage drop over the memristive element applied for a saturation time and wherein the characteristic charge corresponds to a characteristic current through the memristive element applied for a saturation time; wherein the write operation includes: causing a write voltage drop over the memristive element that is greater than the characteristic voltage drop associated with the memristive state or causing a write current through the memristive element that is higher than the characteristic write current associated with the memristive state, each for a total write time that is shorter than the saturation time.

The present specification relates to a writing and reading apparatus and method for spin-transfer torque magnetic RAM (STT-MRAM). An STT-MRAM writing apparatus using a dual reference and step-wise current increases, according to one embodiment, comprises: an array including a plurality of STT-MRAM cells; a reference voltage generation unit for generating reference data to be compared with data to be determined for STT-MRAM cells of a selected address from among the plurality of STT-MRAM cells; and a control unit that transmits a designation signal for obtaining the data to be determined for the STT-MRAM cells of the selected address, wherein the control unit can obtain, from the reference voltage generation unit, a first reference voltage, which is the largest value from among voltage values generated on the basis of a current flowing through an Rp resistor in a low state, and a second reference voltage, which is the smallest value from among voltage values generated on the basis of a current flowing through an Rap resistor in a high state, and generate, on the basis of the first reference voltage and the second reference voltage, a first write current from Rp to Rap, which is to be applied to designated STT-MRAM, or the first write current from Rap to Rp, which is to be applied to the designated STT-MRAM.

The application provides a serial transceiver-based data transmission method, a transceiver, a medium and equipment, and the method comprises the following steps: a serial transceiver switches clock frequency in the process of transmitting frame data, sends clock frequency switching information to a sending end parallel-serial conversion unit, and repeatedly writes current frame data into a sending data buffer; the sending end parallel-serial conversion unit reads parallel valid data of a preset bit number in the current frame data, counts the read bit number through a counter, and after receiving the clock frequency switching information, judges whether the count value is equal to the preset bit number value; if yes, it is determined that the parallel valid data is serialized, and serial data is obtained; the receiving end serial-parallel conversion unit converts the serial data into parallel data, and after detecting a frame header in the parallel data, it is determined that the frame header is in the aligned frame data, and the frame data is written into a receiving data buffer. The application realizes switching of data transmission rate of the serial transceiver in the data transmission process.

The present invention, belonging to the field of memory technology, discloses a circuit structure and method for matching asymmetric read and write currents in STT-MRAM. The circuit comprises a current matching circuit connected in series between a transition line TL and an STT-MRAM source line SL. The circuit comprises: N connected transistors, where N is greater than or equal to 2; three control signals connected to the gates of one or more transistors: a write "1" operation activation signal WR1, a write "0" operation activation signal WR0, and a read operation activation signal RD. When the N transistors are connected in parallel or in series, the matching circuit satisfies the following conditions: when WR1 is activated, the equivalent resistance of the current matching circuit is R1; when WR0 is activated, the equivalent resistance of the current matching circuit is R2; when RD is activated, the equivalent resistance of the current matching circuit is R3; and R3>R2>R1. This invention can match the current magnitudes of different operations while reducing the area overhead of the matching structure.

The invention relates to a quantum device (1) comprising: • a quantum component with Josephson effect (10) having a modular critical current (le), produced on a first face of a substrate (SUB), and comprising: • a first layer (11) made of a first superconducting material; • a second layer (12) made of a second superconducting material; • a junction structure (20) connecting the first layer (11) to the second layer (11) and comprising a ferromagnetic layer with a heterogeneous domain (13) having at least one first magnetic domain (D1) in a first direction and a second magnetic domain (D2) in a second direction opposite to the first direction; and • control means configured to apply a write current through the ferromagnetic layer with the heterogeneous domain (13) in order to modify the volume distribution of the two magnetic domains in the ferromagnetic layer with the heterogeneous domain (13) in order to modulate the critical current (le).

According to one embodiment, a memory device includes: a first memory cell; a second memory cell; a first circuit configured to supply a write current to the first memory cell and the second memory cell; a first wiring coupled to the first circuit; a first electrode configured to electrically couple the first memory cell to the first wiring; and a second electrode configured to electrically couple the second memory cell to the first wiring. A length of the first wiring from the first circuit to the first electrode is smaller than a length of the first wiring from the first circuit to the second electrode. A resistance value of the first electrode is higher than a second resistance value of the second electrode.

The invention provides a capacitive coupling voltage type sense amplifier, a memory and a reading method, the capacitive coupling voltage type sense amplifier comprises a first step-down branch, a coupling capacitor and a first drainage branch; the coupling capacitor comprises a test capacitor; the first voltage reduction branch is connected with one end of the test capacitor and is used for reducing the voltage of one end of the test capacitor to a preset value in a margin development stage; the other end of the test capacitor is respectively connected with the first drainage branch and the magnetic tunnel junction; and the first drainage branch is used for sharing the current on the magnetic tunnel junction in a detection stage. According to the technical scheme provided by the invention, the problems that the critical write-in current cannot be reduced and the read-out reliability cannot be improved at the same time in the prior art and other problems caused by the problems are solved.

A magnetoresistive memory may include a plurality of magnetoresistive memory devices, wherein each magnetoresistive device includes a fixed magnetic region, a free magnetic region, and an intermediate region disposed between the fixed and free magnetic regions. The magnetoresistive memory may include a spin-orbit-torque (SOT) channel, wherein the SOT channel is in contact with the free magnetic regions of the plurality of magnetoresistive memory devices. The magnetoresistive memory may include a write circuit configured to apply a write current through at least one magnetoresistive memory device of the plurality of magnetoresistive memory devices and the SOT channel, wherein the write current is configured to generate a short in at least one magnetoresistive memory device as a one-time programmable read-only memory (ROM) function.

The application relates to a vertical magnetization anti-ferromagnetic magnetic memory without external field assistance and a storage method thereof, which comprises an anti-ferromagnetic layer, an insulating layer and a heavy metal layer from top to bottom, two groups of write currents of the anti-ferromagnetic layer and the heavy metal layer are perpendicular to each other in space, the size and direction of the two groups of write currents of the anti-ferromagnetic layer and the heavy metal layer are controlled, the upward or downward state of a Neel vector in the anti-ferromagnetic layer is controlled, and the Neel vector state represents different information of storage. The Neel vector of an anti-ferromagnetic device is regulated by using direct current to realize data writing, improve the arrangement density of a storage unit array, and save energy consumption. The vertical magnetization anti-ferromagnetic magnetic random storage unit has higher magnetic moment flip speed, better storage stability, simple structure, high speed, anti-stray field disturbance and non-volatility, and the storage unit is especially faster in reading and writing speed.

The invention relates to a distributed hybrid buffer for a memory system. A system may include a memory and a memory controller configured to communicate with the memory through two or more channels. The memory controller may have a buffer with buffer locations distributed across memory channels, and may be configured to receive write commands for writing current data to memory locations within the memory and may be configured to determine whether to buffer data and / or parity, and configured to write the current data or the parity into the buffer when it is determined that the current data or the parity is stored in the buffer. Since the buffer is faster and uses less power, the reduction of back-end access improves performance and reduces power consumption.

This invention discloses a magnetic sensor that integrates full-bridge and dual-axis configurations on a single chip. The magnetic sensor comprises two antiferromagnetic tunnel junction full-bridge structures formed on the same chip with mutually perpendicular magnetic sensing directions. Each arm of the full-bridge structure has an antiferromagnetic tunnel junction unit, comprising, from bottom to top, a heavy metal layer, an antiferromagnetic reference layer, a tunneling barrier layer, an antiferromagnetic free layer, and a ferromagnetic layer. During the initialization phase of the antiferromagnetic tunnel junction unit, the Néel vector direction of the antiferromagnetic reference layer is set by applying an in-plane write current to the heavy metal layer. The Néel vector directions of the antiferromagnetic reference layers in the antiferromagnetic tunnel junction units corresponding to the two pairs of diagonal arms are opposite, and the in-plane write current directions corresponding to the two full-bridge structures are orthogonal. This invention integrates the reverse-direction configuration and the dual-axis orthogonal-direction configuration of the antiferromagnetic tunnel junction full-bridge on the same chip through current initialization.

The invention is suitable for the technical field of display, and provides a compensation method and device of a display panel and a display screen. The display panel comprises a frame buffer. The frame buffer comprises a first storage area used for storing current frame data and a second storage area used for storing previous complete frame data of the current frame data. The compensation method of the display panel comprises the following steps: acquiring a phase difference between an input end synchronizing signal and a display panel synchronizing signal; based on the phase difference, entering a frame compensation mode under the condition of determining that the output frame rate of the graphic processing unit is not synchronous with the fixed refresh rate of the display panel; in the frame compensation mode, stopping writing the current frame data into the first storage area; and circularly outputting the previous complete frame data to the display panel from the second storage area at the first refresh rate, so as to compensate the condition that the front-end input frame rate is different from the refresh rate of the display panel, and improve the problem of picture tearing caused by asynchronization of the input frame rate and the refresh rate of the display panel in a high-frame-rate display process.

The present invention provides a detection and processing method for MRAM write failure, a detection and processing circuit, and an MRAM. The detection and processing method includes: using a write voltage with a voltage value of V1 to write first data to a storage area to be tested of the MRAM; the normal write voltage value of the storage area to be tested during application is V2, and V1 < V2; reading the data stored in the storage area to be tested to obtain second data; comparing the first data and the second data to detect the storage element with write failure in the storage area to be tested. When detecting write failure, the degree of increase in the failure probability of abnormal storage elements with a long tail in the relationship curve between WER and write current is much greater than the degree of increase in the failure probability of normal storage elements with a short tail in the relationship curve between WER and write current, thereby detecting more abnormal storage elements with write failure and improving the overall detection coverage of failed storage elements. The detection and processing method can realize detection through a simple algorithm circuit and can be more efficiently applied to the screening process.

To provide a magnetic recording head, a design method thereof, and a magnetic recording device that provide thermally activated protection against media damage during dynamic events such as operational shocks, load / unload processes, and emergency power-off.SOLUTION: A perpendicular magnetic recording (PMR) read / write transducer head for heat-assisted magnetic recording (HAMR) includes active nano bumper pads formed from thermally activated dynamic flying height (DFH) bulges that protrude closely on either side of the read / write element, and these bumper pads, which can be multiple, are arranged around the perimeter of he transducer head to absorb the heat generated by active heating element, including the write current. When this energy is absorbed, the bulges expand and change shape, protruding closely outward from the slider air bearing surface (ABS), protecting the read / write head from intentional and unintentional touchdowns.SELECTED DRAWING: None

The invention relates to a one-time programmable memory device in monolithic GaN technology. A one time programmable (OTP) memory device includes a semiconductor die and an OTP memory cell integrated into the die. The die includes a channel layer and a barrier layer forming a heterostructure and a plurality of metallization levels over the heterostructure. The OTP memory cell includes a fuse element having a first impedance value in a native unprogrammed state and a second impedance value in a programmed state, where the first impedance value is lower than the second impedance value; and a selector coupled in series to the fuse element and operable to flow a write current to change the fuse element from an unprogrammed state to a programmed state in an irreversible manner. A fuse element is formed in one of the metallization levels of the die. The selector includes a high electron mobility transistor (HEMT) formed at least partially in a heterostructure.

The invention discloses a magnetic random access memory unit and a forming method thereof, and a magnetic random access memory, and the memory unit comprises a spin-orbit torque layer which is used for enabling a write current to flow through when the write operation is carried out on the magnetic random access memory unit; the magnetic tunnel junction is positioned below the spin-orbit torque layer and is in contact with the spin-orbit torque layer; the first conductive structure is located on one side of the magnetic tunnel junction and located below the spin-orbit torque layer, and the first conductive structure is in contact with the spin-orbit torque layer; the second conductive structure is located on the other side of the magnetic tunnel junction and located below the spin-orbit torque layer, the second conductive structure is in contact with the spin-orbit torque layer, and the first conductive structure and the second conductive structure are used for enabling the spin-orbit torque layer to be connected with a write-in current. While the communication delay between the MRAM and the transistor is slowed down, the difficulty that the MRAM needs to stop on a spin-orbit torque layer in the process of forming the magnetic tunnel junction, the first conductive structure and the second conductive structure is also avoided.

The invention discloses a spin-orbit moment magnetic memory and a preparation method thereof, and belongs to the technical field of preparation of spin-electronic devices and semiconductors. The memory includes a first electrode, a spin-orbit moment layer, a magnetic tunnel junction (MTJ), and a conductive interconnect structure underlying the spin-orbit moment layer. A magnetic bias structure is integrated in a conductive interconnection structure and the position of an MTJ is adjusted, so that a compensation field is formed at a free layer of the MTJ, and the compensation field is used for offsetting a bias field caused by a stray field, an interlayer coupling field and a write-in current Oersted field which are generated by a magnetic layer except the free layer in the MTJ. According to the method, an additional layer stack does not need to be introduced into an MTJ film stack, an external magnetic field is not needed, and by adjusting the geometric parameters of the magnetic bias structure and the position of the MTJ, write-in current symmetry and field-free deterministic overturning can be achieved, and the write-in energy efficiency and the data retention performance are improved. The method is compatible with a semiconductor rear-end interconnection process, and excellent performance is still kept under the condition that the size of a device is miniaturized.