73 results about "Write current" patented technology

The invention relates to the technical field of nonvolatile memories, in particular to a 2T1FC ferroelectric memory cell with a memory gate line and a preparation method of the 2T1FC ferroelectric memory cell. The 2T1FC ferroelectric storage unit with the storage gate line comprises a ferroelectric capacitor and a storage transistor which realizes read-write operation of data through polarization modulation of the ferroelectric capacitor; the control transistor is used for enabling a bit line to perform gating access; and the storage gate line is used for controlling the gate of the storage transistor and improving the holding capability of the written data. According to the invention, the special storage gate line is used, so that self-charge dissipation after writing is prevented, and the non-volatility is enhanced; separation of the storage path and the control path minimizes accidental flipping in the read / write cycle; the service life of the device is prolonged by lower write-in current stress and an isolated gate structure; low-voltage writing with high retentivity can be realized, and the method is suitable for energy-limited edge AI equipment.

The present embodiments can generally provide a magnetic write head structure with optimized gap current distribution to maximize the current-assisted areal density capacity (ADC) gain in hard-disk-drive storage devices. In a first example embodiment, a non-dual-write-shield (nDWS) write head can include a main pole (MP), a trailing shield (TS), and a write gap (WG) disposed between the MP and the TS. The write head can also include a side shield (SS), a leading shield (LS), and a write shield (WS). The write head can include a side gap (SG) between the MP and the SS on both sides of the MP tip, and a leading gap (LG) between the MP and the LS. The write head can also include a coil wrapped around the MP through a PP3 shield that is configured to direct a time-dependent write current to saturate magnetization of the MP.

A magnetoresistive effect element includes a reference layer, a barrier layer, a recording layer, and a channel layer that are disposed on top of one another, and a first terminal connected to the reference layer, and a second terminal and a third terminal connected to the channel layer. The channel layer includes a first channel layer and a second channel layer, the first channel layer has electrical resistance larger than electrical resistance of the second channel layer, the second terminal is connected to the first channel layer, and the third terminal is connected to the second channel layer, a write current flows between the second terminal and the third terminal via the first channel layer and the second channel layer, and a read current flows between the first terminal and the third terminal.

The application provides a SOT-MRAM and a manufacturing method thereof, the SOT-MRAM comprising a substrate, a plurality of memory cells arranged on the substrate. Each memory cell comprises a SOT layer deposited on the substrate, a magnetic tunnel junction arranged on the SOT layer. Further comprising an antiferromagnetic insulating layer at least wrapping around the side surface of the free layer in each magnetic tunnel junction, and the magnetic moment direction of the antiferromagnetic insulating layer is parallel to the direction of the write current in the SOT layer. By adding the antiferromagnetic insulating layer at least wrapping around the side surface of the free layer in each magnetic tunnel junction, and further making the magnetic moment direction of the antiferromagnetic insulating layer parallel to the direction of the write current, an in-plane magnetic field can be provided for the free layer, for the field-free switching of the SOT-MRAM, solving the problem that the SOT-MRAM cannot be mass integrated due to the need to apply an external magnetic field during the writing process. And the added antiferromagnetic insulating layer is arranged around the magnetic tunnel junction, thereby also having the effect of protecting the magnetic tunnel junction from the surrounding environment.

A data storage device comprises a magnetic medium and a head configured to be actuated over the magnetic medium. The head comprises a write element and a write driver configured to generate a write current to be applied to the write element. The write driver comprises a data switch section configured to switchably output low-level signals and high-level signals, and a stationary cascode section configured to receive the low-level signals and high-level signals from the data switch section and to generate a cascode pass through current. The data switch section comprises low voltage CMOS devices and the stationary cascode section comprises high voltage CMOS devices.

A magnetic domain wall movement element according to the present embodiment includes a magnetoresistance effect element that has a reference layer, a nonmagnetic layer, and a magnetic domain wall movement layer in order from a side closer to a substrate; and a first magnetization fixed layer and a second magnetization fixed layer which are each in contact with the magnetic domain wall movement layer and are separated from each other, wherein the magnetic domain wall movement layer includes a plurality of ferromagnetic layers and a plurality of insertion layers sandwiched between the plurality of ferromagnetic layers, wherein the ferromagnetic layer contains Co and Fe and has perpendicular magnetic anisotropy, and wherein, when writing is performed, a write current is allowed to flow between the first magnetization fixed layer and the second magnetization fixed layer along the magnetic domain wall movement layer.

The application provides a magnetic tunnel junction free layer and a magnetic tunnel junction structure with the same. The magnetic tunnel junction free layer comprises a first magnetic composite layer, an antiferromagnetic spacer structure and a second magnetic composite layer which are sequentially stacked along a first direction. The first magnetic composite layer and the second magnetic composite layer are in antiferromagnetic coupling under the action of the antiferromagnetic spacer structure, and the magnetization directions thereof are opposite. Since the above structure adopts a plurality of magnetic composite layers, the overall thickness of the magnetic layer is increased while the magnetization direction is controlled to be perpendicular to the film interface, thereby increasing the data retention capability of the device. In addition, in order to reduce the write current, the above structure makes the magnetization directions of different magnetic composite layers opposite, reduces the total magnetic moment of the overall structure, thereby reducing the write current and realizing high device erasing resistance. In addition, the structure can obtain a higher TMR, thereby improving the data reading speed.

A device includes a memristive element; and a write circuit to write the memristive element into a memristive state of a plurality of memristive states by a write operation, wherein the memristive state has a characteristic flux and / or a characteristic charge; wherein the characteristic flux corresponds to a characteristic voltage drop over the memristive element applied for a saturation time and wherein the characteristic charge corresponds to a characteristic current through the memristive element applied for a saturation time; wherein the write operation includes: causing a write voltage drop over the memristive element that is greater than the characteristic voltage drop associated with the memristive state or causing a write current through the memristive element that is higher than the characteristic write current associated with the memristive state, each for a total write time that is shorter than the saturation time.

The application provides a serial transceiver-based data transmission method, a transceiver, a medium and equipment, and the method comprises the following steps: a serial transceiver switches clock frequency in the process of transmitting frame data, sends clock frequency switching information to a sending end parallel-serial conversion unit, and repeatedly writes current frame data into a sending data buffer; the sending end parallel-serial conversion unit reads parallel valid data of a preset bit number in the current frame data, counts the read bit number through a counter, and after receiving the clock frequency switching information, judges whether the count value is equal to the preset bit number value; if yes, it is determined that the parallel valid data is serialized, and serial data is obtained; the receiving end serial-parallel conversion unit converts the serial data into parallel data, and after detecting a frame header in the parallel data, it is determined that the frame header is in the aligned frame data, and the frame data is written into a receiving data buffer. The application realizes switching of data transmission rate of the serial transceiver in the data transmission process.

The application relates to a vertical magnetization anti-ferromagnetic magnetic memory without external field assistance and a storage method thereof, which comprises an anti-ferromagnetic layer, an insulating layer and a heavy metal layer from top to bottom, two groups of write currents of the anti-ferromagnetic layer and the heavy metal layer are perpendicular to each other in space, the size and direction of the two groups of write currents of the anti-ferromagnetic layer and the heavy metal layer are controlled, the upward or downward state of a Neel vector in the anti-ferromagnetic layer is controlled, and the Neel vector state represents different information of storage. The Neel vector of an anti-ferromagnetic device is regulated by using direct current to realize data writing, improve the arrangement density of a storage unit array, and save energy consumption. The vertical magnetization anti-ferromagnetic magnetic random storage unit has higher magnetic moment flip speed, better storage stability, simple structure, high speed, anti-stray field disturbance and non-volatility, and the storage unit is especially faster in reading and writing speed.

The invention relates to a distributed hybrid buffer for a memory system. A system may include a memory and a memory controller configured to communicate with the memory through two or more channels. The memory controller may have a buffer with buffer locations distributed across memory channels, and may be configured to receive write commands for writing current data to memory locations within the memory and may be configured to determine whether to buffer data and / or parity, and configured to write the current data or the parity into the buffer when it is determined that the current data or the parity is stored in the buffer. Since the buffer is faster and uses less power, the reduction of back-end access improves performance and reduces power consumption.

This invention discloses a magnetic sensor that integrates full-bridge and dual-axis configurations on a single chip. The magnetic sensor comprises two antiferromagnetic tunnel junction full-bridge structures formed on the same chip with mutually perpendicular magnetic sensing directions. Each arm of the full-bridge structure has an antiferromagnetic tunnel junction unit, comprising, from bottom to top, a heavy metal layer, an antiferromagnetic reference layer, a tunneling barrier layer, an antiferromagnetic free layer, and a ferromagnetic layer. During the initialization phase of the antiferromagnetic tunnel junction unit, the Néel vector direction of the antiferromagnetic reference layer is set by applying an in-plane write current to the heavy metal layer. The Néel vector directions of the antiferromagnetic reference layers in the antiferromagnetic tunnel junction units corresponding to the two pairs of diagonal arms are opposite, and the in-plane write current directions corresponding to the two full-bridge structures are orthogonal. This invention integrates the reverse-direction configuration and the dual-axis orthogonal-direction configuration of the antiferromagnetic tunnel junction full-bridge on the same chip through current initialization.

The invention is suitable for the technical field of display, and provides a compensation method and device of a display panel and a display screen. The display panel comprises a frame buffer. The frame buffer comprises a first storage area used for storing current frame data and a second storage area used for storing previous complete frame data of the current frame data. The compensation method of the display panel comprises the following steps: acquiring a phase difference between an input end synchronizing signal and a display panel synchronizing signal; based on the phase difference, entering a frame compensation mode under the condition of determining that the output frame rate of the graphic processing unit is not synchronous with the fixed refresh rate of the display panel; in the frame compensation mode, stopping writing the current frame data into the first storage area; and circularly outputting the previous complete frame data to the display panel from the second storage area at the first refresh rate, so as to compensate the condition that the front-end input frame rate is different from the refresh rate of the display panel, and improve the problem of picture tearing caused by asynchronization of the input frame rate and the refresh rate of the display panel in a high-frame-rate display process.

The present invention provides a detection and processing method for MRAM write failure, a detection and processing circuit, and an MRAM. The detection and processing method includes: using a write voltage with a voltage value of V1 to write first data to a storage area to be tested of the MRAM; the normal write voltage value of the storage area to be tested during application is V2, and V1 < V2; reading the data stored in the storage area to be tested to obtain second data; comparing the first data and the second data to detect the storage element with write failure in the storage area to be tested. When detecting write failure, the degree of increase in the failure probability of abnormal storage elements with a long tail in the relationship curve between WER and write current is much greater than the degree of increase in the failure probability of normal storage elements with a short tail in the relationship curve between WER and write current, thereby detecting more abnormal storage elements with write failure and improving the overall detection coverage of failed storage elements. The detection and processing method can realize detection through a simple algorithm circuit and can be more efficiently applied to the screening process.

To provide a magnetic recording head, a design method thereof, and a magnetic recording device that provide thermally activated protection against media damage during dynamic events such as operational shocks, load / unload processes, and emergency power-off.SOLUTION: A perpendicular magnetic recording (PMR) read / write transducer head for heat-assisted magnetic recording (HAMR) includes active nano bumper pads formed from thermally activated dynamic flying height (DFH) bulges that protrude closely on either side of the read / write element, and these bumper pads, which can be multiple, are arranged around the perimeter of he transducer head to absorb the heat generated by active heating element, including the write current. When this energy is absorbed, the bulges expand and change shape, protruding closely outward from the slider air bearing surface (ABS), protecting the read / write head from intentional and unintentional touchdowns.SELECTED DRAWING: None

The invention relates to a one-time programmable memory device in monolithic GaN technology. A one time programmable (OTP) memory device includes a semiconductor die and an OTP memory cell integrated into the die. The die includes a channel layer and a barrier layer forming a heterostructure and a plurality of metallization levels over the heterostructure. The OTP memory cell includes a fuse element having a first impedance value in a native unprogrammed state and a second impedance value in a programmed state, where the first impedance value is lower than the second impedance value; and a selector coupled in series to the fuse element and operable to flow a write current to change the fuse element from an unprogrammed state to a programmed state in an irreversible manner. A fuse element is formed in one of the metallization levels of the die. The selector includes a high electron mobility transistor (HEMT) formed at least partially in a heterostructure.

The invention discloses a magnetic random access memory unit and a forming method thereof, and a magnetic random access memory, and the memory unit comprises a spin-orbit torque layer which is used for enabling a write current to flow through when the write operation is carried out on the magnetic random access memory unit; the magnetic tunnel junction is positioned below the spin-orbit torque layer and is in contact with the spin-orbit torque layer; the first conductive structure is located on one side of the magnetic tunnel junction and located below the spin-orbit torque layer, and the first conductive structure is in contact with the spin-orbit torque layer; the second conductive structure is located on the other side of the magnetic tunnel junction and located below the spin-orbit torque layer, the second conductive structure is in contact with the spin-orbit torque layer, and the first conductive structure and the second conductive structure are used for enabling the spin-orbit torque layer to be connected with a write-in current. While the communication delay between the MRAM and the transistor is slowed down, the difficulty that the MRAM needs to stop on a spin-orbit torque layer in the process of forming the magnetic tunnel junction, the first conductive structure and the second conductive structure is also avoided.

The invention discloses a spin-orbit moment magnetic memory and a preparation method thereof, and belongs to the technical field of preparation of spin-electronic devices and semiconductors. The memory includes a first electrode, a spin-orbit moment layer, a magnetic tunnel junction (MTJ), and a conductive interconnect structure underlying the spin-orbit moment layer. A magnetic bias structure is integrated in a conductive interconnection structure and the position of an MTJ is adjusted, so that a compensation field is formed at a free layer of the MTJ, and the compensation field is used for offsetting a bias field caused by a stray field, an interlayer coupling field and a write-in current Oersted field which are generated by a magnetic layer except the free layer in the MTJ. According to the method, an additional layer stack does not need to be introduced into an MTJ film stack, an external magnetic field is not needed, and by adjusting the geometric parameters of the magnetic bias structure and the position of the MTJ, write-in current symmetry and field-free deterministic overturning can be achieved, and the write-in energy efficiency and the data retention performance are improved. The method is compatible with a semiconductor rear-end interconnection process, and excellent performance is still kept under the condition that the size of a device is miniaturized.

The application discloses a kind of magnetic random memory based on nonlinear spin polarization and its implementation method, belong to magnetic random memory field.The spin orbit layer of the present application adopts magnetic material with perpendicular magnetic anisotropy, when writing, write current is applied in plane by writing electrode, due to nonlinear spin polarization effect, the magnetization vector of spin orbit layer is greatly periodic oscillation, after current is cut off, magnetization vector is determined to relax to the nearest steady state from current phase, information writing is realized;When reading, read circuit shows the voltage state corresponding to the state of magnetization vector, information reading is realized;The present application solves the problem of material symmetry restriction and process sensitivity faced by magnetic memory device when determining flip without external field.The present application widens material selection range, realizes the determining flip without external magnetic field, improves interface efficiency and write energy efficiency, and simplifies device process structure;The present application is applied to MRAM array design and peripheral integrated circuit.

The present disclosure relates to the technical field of semiconductor devices and manufacturing technology thereof, in particular to a magnetic memory and a manufacturing method thereof, the magnetic memory comprising at least: an anti-ferromagnetic layer, a material of the anti-ferromagnetic layer being a non-collinear anti-ferromagnetic material; and a magnetic tunnel junction disposed on the anti-ferromagnetic layer, the magnetic tunnel junction comprising, from bottom to top, a free layer, a tunneling barrier layer and a reference layer; wherein when the anti-ferromagnetic layer is supplied with a current, a spin-orbit torque effect of the anti-ferromagnetic layer is utilized to change a direction of an exchange bias field formed by the anti-ferromagnetic layer and the free layer, and then to flip a magnetic moment direction of the free layer. The magnetic moment flipping can be achieved by means of the spin-orbit torque effect of the anti-ferromagnetic layer of the non-collinear anti-ferromagnetic material, so that the write-in current is greatly reduced, and the power consumption of the magnetic memory is reduced, and the magnetic memory is easier to drive.

A disk drive device is provided that improves the reliability of information recorded on the disk. According to one embodiment, a disk drive device is provided comprising a disk, a head, a preamplifier, and a controller. The head writes information to the disk based on a write current. The preamplifier supplies write current to the head. The controller enables the preamplifier to perform zero-current control. Zero-current control is control that maintains the amplitude of the write current at zero. The controller can vary the time for maintaining the amplitude of the write current at zero according to the pattern of the written data.

This invention provides a domain wall moving element and magnetic array with a high MR ratio and high domain wall controllability. The domain wall moving element of this embodiment includes: a magnetoresistive element having, sequentially from the side closest to the substrate, a reference layer, a non-magnetic layer, and a domain wall moving layer; a first magnetization fixing layer and a second magnetization fixing layer, respectively connected to and separated from the domain wall moving layer; the domain wall moving layer includes a ferromagnetic layer comprising multiple intercalation layers, the ferromagnetic layer containing Co and Fe, and having perpendicular magnetic anisotropy; during writing, a writing current flows along the domain wall moving layer between the first magnetization fixing layer and the second magnetization fixing layer.

According to an embodiment, a system includes a writer circuit of a pre-amplifier coupled between first and second pre-amplifier supply voltages and configured to generate a write current. A ballast circuit couples in parallel with the writer circuit between first and second supply voltages. The ballast circuit generates first and second ballast currents in response to a write enable signal and injects them into the pre-amplifier supply voltages to pre-charge parasitic inductances before the writer circuit generates the write current. The ballast circuit includes a programmable delay circuit that generates a timing pulse matching a propagation delay of the writer circuit, and a configurable current mirror circuit that generates the ballast currents. The ballast currents are de-asserted when the writer circuit begins generating the write current.

This invention belongs to the field of magnetic tunnel junction technology, and particularly relates to a free layer of a magnetic tunnel junction, a magnetic tunnel junction, and a spin-transfer torque magnetic random access memory (STM). The free layer provided by this invention comprises a first ferromagnetic layer, a spacer layer, and a second ferromagnetic layer in sequential contact; the thicknesses of both the first and second ferromagnetic layers are ≤1 nm, and the thickness of the second ferromagnetic layer is less than the thickness of the first ferromagnetic layer; the spacer layer comprises at least two non-magnetic elements. By controlling the thickness of the first and second ferromagnetic layers in the free layer structure to less than 1 nm, this invention effectively improves STT efficiency and reduces write current; simultaneously, the spacer layer in this free layer structure is composed of at least two different non-magnetic elements with strong binding energy, ensuring the stability of the spacer layer structure, suppressing element diffusion caused by the thinning of the magnetic layer, and improving erasure and write resistance.

The invention provides a magnetic random storage unit, a writing method and a storage system, and the magnetic random storage unit comprises a bottom electrode layer which is arranged on a substrate; the at least one magnetic tunnel junction is arranged on the bottom electrode layer and comprises a free layer, an insulating layer arranged on the free layer and a reference layer arranged on the insulating layer; a write-in current is input through a write-in channel, the write-in channel extends from one end of the bottom electrode layer to the top end of the magnetic tunnel junction through the magnetic tunnel junction, and the magnetic moment direction of a free layer of the magnetic tunnel junction is subjected to deterministic overturning based on a track flow effect formed when the write-in current is introduced into the bottom electrode layer. The process difficulty, the device power consumption and the device area can be reduced, and reliable writing of data is realized.

This disclosure provides a computing circuit. The computing circuit includes a first magnetic tunnel junction and a second magnetic tunnel junction. The first magnetic tunnel junction is configured to store a first logic value based on a write current. The second magnetic tunnel junction is configured to store a second logic value based on the write current. The first logic value is different from the second logic value.

A spintronics element (10) comprises: a channel layer (30); a free layer (21) laminated on the channel layer (30); a barrier layer (22) laminated on the free layer (21); and a reference layer (23) laminated on the barrier layer (22). The direction of magnetization in the reference layer (23) is fixed. The direction of magnetization in the free layer (21) changes due to spin-orbit torque, which is generated by a write current that flows through the channel layer (30). The channel layer (30) is formed of a tungsten alloy containing at least one of iron and nickel in an amount of 35at% or less.

A memristor according to an embodiment of the present invention comprises a reference layer, a first nonmagnetic layer, a domain wall displacement layer, a second nonmagnetic layer, a first pin layer, and a second pin layer. The first nonmagnetic layer is between the reference layer and the domain wall displacement layer in the stacking direction. The first pin layer is connected to the domain wall displacement layer with the second nonmagnetic layer interposed therebetween. The second pin layer is connected to the domain wall displacement layer at a position different from that of the first pin layer with the second nonmagnetic layer interposed therebetween. The memristor is configured so that a write current smaller than an initial current can be applied between the first pin layer and the second pin layer. The initial current is applied between the first pin layer and the second pin layer when a magnetic domain wall is introduced into the domain wall displacement layer.

A system may include a memory and memory controller configured to communicate with the memory over two or more channels. The memory controller may have a buffer with buffer locations distributed across memory channels, and may be configured to receive a write command for writing current data to a memory location within the memory and may be configured to determine whether to buffer data and / or parity, and configured to write the current data or the current parity in the buffer when it is determined to be stored in the buffer. As the buffer is faster and uses less power, the reduction in back-end accesses improves performance and reduces power consumption.