47 results about "Write current" patented technology

The present embodiments can generally provide a magnetic write head structure with optimized gap current distribution to maximize the current-assisted areal density capacity (ADC) gain in hard-disk-drive storage devices. In a first example embodiment, a non-dual-write-shield (nDWS) write head can include a main pole (MP), a trailing shield (TS), and a write gap (WG) disposed between the MP and the TS. The write head can also include a side shield (SS), a leading shield (LS), and a write shield (WS). The write head can include a side gap (SG) between the MP and the SS on both sides of the MP tip, and a leading gap (LG) between the MP and the LS. The write head can also include a coil wrapped around the MP through a PP3 shield that is configured to direct a time-dependent write current to saturate magnetization of the MP.

A magnetoresistive effect element includes a reference layer, a barrier layer, a recording layer, and a channel layer that are disposed on top of one another, and a first terminal connected to the reference layer, and a second terminal and a third terminal connected to the channel layer. The channel layer includes a first channel layer and a second channel layer, the first channel layer has electrical resistance larger than electrical resistance of the second channel layer, the second terminal is connected to the first channel layer, and the third terminal is connected to the second channel layer, a write current flows between the second terminal and the third terminal via the first channel layer and the second channel layer, and a read current flows between the first terminal and the third terminal.

The application provides a SOT-MRAM and a manufacturing method thereof, the SOT-MRAM comprising a substrate, a plurality of memory cells arranged on the substrate. Each memory cell comprises a SOT layer deposited on the substrate, a magnetic tunnel junction arranged on the SOT layer. Further comprising an antiferromagnetic insulating layer at least wrapping around the side surface of the free layer in each magnetic tunnel junction, and the magnetic moment direction of the antiferromagnetic insulating layer is parallel to the direction of the write current in the SOT layer. By adding the antiferromagnetic insulating layer at least wrapping around the side surface of the free layer in each magnetic tunnel junction, and further making the magnetic moment direction of the antiferromagnetic insulating layer parallel to the direction of the write current, an in-plane magnetic field can be provided for the free layer, for the field-free switching of the SOT-MRAM, solving the problem that the SOT-MRAM cannot be mass integrated due to the need to apply an external magnetic field during the writing process. And the added antiferromagnetic insulating layer is arranged around the magnetic tunnel junction, thereby also having the effect of protecting the magnetic tunnel junction from the surrounding environment.

A magnetic domain wall movement element according to the present embodiment includes a magnetoresistance effect element that has a reference layer, a nonmagnetic layer, and a magnetic domain wall movement layer in order from a side closer to a substrate; and a first magnetization fixed layer and a second magnetization fixed layer which are each in contact with the magnetic domain wall movement layer and are separated from each other, wherein the magnetic domain wall movement layer includes a plurality of ferromagnetic layers and a plurality of insertion layers sandwiched between the plurality of ferromagnetic layers, wherein the ferromagnetic layer contains Co and Fe and has perpendicular magnetic anisotropy, and wherein, when writing is performed, a write current is allowed to flow between the first magnetization fixed layer and the second magnetization fixed layer along the magnetic domain wall movement layer.

The application provides a serial transceiver-based data transmission method, a transceiver, a medium and equipment, and the method comprises the following steps: a serial transceiver switches clock frequency in the process of transmitting frame data, sends clock frequency switching information to a sending end parallel-serial conversion unit, and repeatedly writes current frame data into a sending data buffer; the sending end parallel-serial conversion unit reads parallel valid data of a preset bit number in the current frame data, counts the read bit number through a counter, and after receiving the clock frequency switching information, judges whether the count value is equal to the preset bit number value; if yes, it is determined that the parallel valid data is serialized, and serial data is obtained; the receiving end serial-parallel conversion unit converts the serial data into parallel data, and after detecting a frame header in the parallel data, it is determined that the frame header is in the aligned frame data, and the frame data is written into a receiving data buffer. The application realizes switching of data transmission rate of the serial transceiver in the data transmission process.

The application relates to a vertical magnetization anti-ferromagnetic magnetic memory without external field assistance and a storage method thereof, which comprises an anti-ferromagnetic layer, an insulating layer and a heavy metal layer from top to bottom, two groups of write currents of the anti-ferromagnetic layer and the heavy metal layer are perpendicular to each other in space, the size and direction of the two groups of write currents of the anti-ferromagnetic layer and the heavy metal layer are controlled, the upward or downward state of a Neel vector in the anti-ferromagnetic layer is controlled, and the Neel vector state represents different information of storage. The Neel vector of an anti-ferromagnetic device is regulated by using direct current to realize data writing, improve the arrangement density of a storage unit array, and save energy consumption. The vertical magnetization anti-ferromagnetic magnetic random storage unit has higher magnetic moment flip speed, better storage stability, simple structure, high speed, anti-stray field disturbance and non-volatility, and the storage unit is especially faster in reading and writing speed.

The invention relates to a distributed hybrid buffer for a memory system. A system may include a memory and a memory controller configured to communicate with the memory through two or more channels. The memory controller may have a buffer with buffer locations distributed across memory channels, and may be configured to receive write commands for writing current data to memory locations within the memory and may be configured to determine whether to buffer data and / or parity, and configured to write the current data or the parity into the buffer when it is determined that the current data or the parity is stored in the buffer. Since the buffer is faster and uses less power, the reduction of back-end access improves performance and reduces power consumption.

This invention discloses a magnetic sensor that integrates full-bridge and dual-axis configurations on a single chip. The magnetic sensor comprises two antiferromagnetic tunnel junction full-bridge structures formed on the same chip with mutually perpendicular magnetic sensing directions. Each arm of the full-bridge structure has an antiferromagnetic tunnel junction unit, comprising, from bottom to top, a heavy metal layer, an antiferromagnetic reference layer, a tunneling barrier layer, an antiferromagnetic free layer, and a ferromagnetic layer. During the initialization phase of the antiferromagnetic tunnel junction unit, the Néel vector direction of the antiferromagnetic reference layer is set by applying an in-plane write current to the heavy metal layer. The Néel vector directions of the antiferromagnetic reference layers in the antiferromagnetic tunnel junction units corresponding to the two pairs of diagonal arms are opposite, and the in-plane write current directions corresponding to the two full-bridge structures are orthogonal. This invention integrates the reverse-direction configuration and the dual-axis orthogonal-direction configuration of the antiferromagnetic tunnel junction full-bridge on the same chip through current initialization.

The invention is suitable for the technical field of display, and provides a compensation method and device of a display panel and a display screen. The display panel comprises a frame buffer. The frame buffer comprises a first storage area used for storing current frame data and a second storage area used for storing previous complete frame data of the current frame data. The compensation method of the display panel comprises the following steps: acquiring a phase difference between an input end synchronizing signal and a display panel synchronizing signal; based on the phase difference, entering a frame compensation mode under the condition of determining that the output frame rate of the graphic processing unit is not synchronous with the fixed refresh rate of the display panel; in the frame compensation mode, stopping writing the current frame data into the first storage area; and circularly outputting the previous complete frame data to the display panel from the second storage area at the first refresh rate, so as to compensate the condition that the front-end input frame rate is different from the refresh rate of the display panel, and improve the problem of picture tearing caused by asynchronization of the input frame rate and the refresh rate of the display panel in a high-frame-rate display process.

The invention discloses a spin-orbit moment magnetic memory and a preparation method thereof, and belongs to the technical field of preparation of spin-electronic devices and semiconductors. The memory includes a first electrode, a spin-orbit moment layer, a magnetic tunnel junction (MTJ), and a conductive interconnect structure underlying the spin-orbit moment layer. A magnetic bias structure is integrated in a conductive interconnection structure and the position of an MTJ is adjusted, so that a compensation field is formed at a free layer of the MTJ, and the compensation field is used for offsetting a bias field caused by a stray field, an interlayer coupling field and a write-in current Oersted field which are generated by a magnetic layer except the free layer in the MTJ. According to the method, an additional layer stack does not need to be introduced into an MTJ film stack, an external magnetic field is not needed, and by adjusting the geometric parameters of the magnetic bias structure and the position of the MTJ, write-in current symmetry and field-free deterministic overturning can be achieved, and the write-in energy efficiency and the data retention performance are improved. The method is compatible with a semiconductor rear-end interconnection process, and excellent performance is still kept under the condition that the size of a device is miniaturized.

The application discloses a kind of magnetic random memory based on nonlinear spin polarization and its implementation method, belong to magnetic random memory field.The spin orbit layer of the present application adopts magnetic material with perpendicular magnetic anisotropy, when writing, write current is applied in plane by writing electrode, due to nonlinear spin polarization effect, the magnetization vector of spin orbit layer is greatly periodic oscillation, after current is cut off, magnetization vector is determined to relax to the nearest steady state from current phase, information writing is realized;When reading, read circuit shows the voltage state corresponding to the state of magnetization vector, information reading is realized;The present application solves the problem of material symmetry restriction and process sensitivity faced by magnetic memory device when determining flip without external field.The present application widens material selection range, realizes the determining flip without external magnetic field, improves interface efficiency and write energy efficiency, and simplifies device process structure;The present application is applied to MRAM array design and peripheral integrated circuit.

A disk drive device is provided that improves the reliability of information recorded on the disk. According to one embodiment, a disk drive device is provided comprising a disk, a head, a preamplifier, and a controller. The head writes information to the disk based on a write current. The preamplifier supplies write current to the head. The controller enables the preamplifier to perform zero-current control. Zero-current control is control that maintains the amplitude of the write current at zero. The controller can vary the time for maintaining the amplitude of the write current at zero according to the pattern of the written data.

This invention provides a domain wall moving element and magnetic array with a high MR ratio and high domain wall controllability. The domain wall moving element of this embodiment includes: a magnetoresistive element having, sequentially from the side closest to the substrate, a reference layer, a non-magnetic layer, and a domain wall moving layer; a first magnetization fixing layer and a second magnetization fixing layer, respectively connected to and separated from the domain wall moving layer; the domain wall moving layer includes a ferromagnetic layer comprising multiple intercalation layers, the ferromagnetic layer containing Co and Fe, and having perpendicular magnetic anisotropy; during writing, a writing current flows along the domain wall moving layer between the first magnetization fixing layer and the second magnetization fixing layer.

According to an embodiment, a system includes a writer circuit of a pre-amplifier coupled between first and second pre-amplifier supply voltages and configured to generate a write current. A ballast circuit couples in parallel with the writer circuit between first and second supply voltages. The ballast circuit generates first and second ballast currents in response to a write enable signal and injects them into the pre-amplifier supply voltages to pre-charge parasitic inductances before the writer circuit generates the write current. The ballast circuit includes a programmable delay circuit that generates a timing pulse matching a propagation delay of the writer circuit, and a configurable current mirror circuit that generates the ballast currents. The ballast currents are de-asserted when the writer circuit begins generating the write current.

This invention belongs to the field of magnetic tunnel junction technology, and particularly relates to a free layer of a magnetic tunnel junction, a magnetic tunnel junction, and a spin-transfer torque magnetic random access memory (STM). The free layer provided by this invention comprises a first ferromagnetic layer, a spacer layer, and a second ferromagnetic layer in sequential contact; the thicknesses of both the first and second ferromagnetic layers are ≤1 nm, and the thickness of the second ferromagnetic layer is less than the thickness of the first ferromagnetic layer; the spacer layer comprises at least two non-magnetic elements. By controlling the thickness of the first and second ferromagnetic layers in the free layer structure to less than 1 nm, this invention effectively improves STT efficiency and reduces write current; simultaneously, the spacer layer in this free layer structure is composed of at least two different non-magnetic elements with strong binding energy, ensuring the stability of the spacer layer structure, suppressing element diffusion caused by the thinning of the magnetic layer, and improving erasure and write resistance.

A memristor according to an embodiment of the present invention comprises a reference layer, a first nonmagnetic layer, a domain wall displacement layer, a second nonmagnetic layer, a first pin layer, and a second pin layer. The first nonmagnetic layer is between the reference layer and the domain wall displacement layer in the stacking direction. The first pin layer is connected to the domain wall displacement layer with the second nonmagnetic layer interposed therebetween. The second pin layer is connected to the domain wall displacement layer at a position different from that of the first pin layer with the second nonmagnetic layer interposed therebetween. The memristor is configured so that a write current smaller than an initial current can be applied between the first pin layer and the second pin layer. The initial current is applied between the first pin layer and the second pin layer when a magnetic domain wall is introduced into the domain wall displacement layer.

A system may include a memory and memory controller configured to communicate with the memory over two or more channels. The memory controller may have a buffer with buffer locations distributed across memory channels, and may be configured to receive a write command for writing current data to a memory location within the memory and may be configured to determine whether to buffer data and / or parity, and configured to write the current data or the current parity in the buffer when it is determined to be stored in the buffer. As the buffer is faster and uses less power, the reduction in back-end accesses improves performance and reduces power consumption.

A magnetic memory device includes: a cell array including: memory cells including first magnetic tunnel junction elements; and a one-time programmable (OTP) cell including a second magnetic tunnel junction element; and a control circuit configured to perform a read operation on the OTP cell by applying a write current to the OTP cell, and determine whether a resistance of the OTP cell changes after the write current is applied to the OTP cell.

A system may include a memory and memory controller configured to communicate with the memory over two or more channels. The memory controller may have a buffer with buffer locations distributed across memory channels, and may be configured to receive a write command for writing current data to a memory location within the memory and may be configured to determine whether to buffer data and / or parity, and configured to write the current data or the current parity in the buffer when it is determined to be stored in the buffer. As the buffer is faster and uses less power, the reduction in back-end accesses improves performance and reduces power consumption.

The disclosed system and method reduce on-chip power IR drop caused by large write current, to increase the write IO number or improve write throughput and to suppress write voltage ripple at the start and end of a write operation. The disclosed systems and methods are described in relation to stabilizing the bit line voltage for MRAMs, however, the disclosed systems and methods can be used to stabilize the bit line voltage of any memory configuration that draws large currents during short write pulses or, more generally, to selectively assist a power supply generator in supplying adequate power to a load at times of large power consumption.

According to various aspects, a device is provided including: a memristive element; and a write circuit to write the memristive element into a memristive state of a plurality of memristive states by a write operation, wherein the memristive state has a characteristic flux and / or a characteristic charge associated therewith, wherein the characteristic flux corresponds to a characteristic voltage drop over the memristive element applied for a saturation time and wherein the characteristic charge corresponds to a characteristic current through the memristive element applied for a saturation time; wherein the write operation includes: causing a write voltage drop over the memristive element that is greater than the characteristic voltage drop associated with the memristive state for a total write time that is shorter than the saturation time, or causing a write current through the memristive element that is higher than the characteristic write current associated with the memristive state for a total write time that is shorter than the saturation time.

A spin-orbit moment magnetic random access memory (MORAM) and method for controlling an artificial antiferromagnetic free layer with ferroelectric metal are disclosed. The MORAM comprises multiple memory cells, with the free magnetic layer being an artificial antiferromagnetic structure comprising a first magnetic layer, a non-magnetically coupled layer formed on the first magnetic layer, and a second magnetic layer formed on the non-magnetically coupled layer. The ferroelectric metal layer simultaneously possesses ferroelectric polarization characteristics and a spin-orbit coupling effect, generating a spin-orbit moment when an in-plane current is applied to drive the magnetic moment reversal of the free magnetic layer. Simultaneously, the magnetic coupling state of the artificial antiferromagnetic structure is controlled by the ferroelectric polarization electric field. The simultaneous presence of ferroelectric polarization and spin-orbit coupling characteristics in the ferroelectric metal layer enables both ferroelectric control and spin-orbit moment writing functions, thereby simplifying the device structure, reducing the write current density required for magnetic moment reversal, and lowering device power consumption.

This invention relates to a magnetic tunnel junction memory cell based on magnetic skyrmions and its operation method. A magnetic tunnel junction memory cell may include: a reference magnetic layer and a free magnetic layer separated by a barrier layer; a skyrmion carrier layer separated from the free magnetic layer by a spacer layer, the spacer layer inducing ferromagnetic coupling or antiferromagnetic coupling between the skyrmion carrier layer and the free magnetic layer; and a cap layer formed on the skyrmion carrier layer, the cap layer applying a bias magnetic field to the skyrmion carrier layer by an exchange bias, such that the skyrmion carrier layer is in the skyrmion phase, wherein the cap layer generates a spin current when an in-plane write current is applied, the spin current being vertically injected into the skyrmion carrier layer to write skyrmions, and the skyrmions being coupled to the free magnetic layer through ferromagnetic coupling or antiferromagnetic coupling induced by the spacer layer.

A resistive memory device includes an array of memory cells including a memory cell connected between a first signal line and a second signal line; a control circuit configured to generate a write control signal for controlling a data write operation performed on the memory cell and a read control signal for controlling a data read operation for reading data stored in the memory cell; a write circuit configured to supply a write current to support the data write operation; a read circuit configured to supply a read current to support the data read operation; a column decoder circuit configured to electrically connect the write circuit to the first signal line based on the write control signal; and a row decoder circuit configured to electrically connect the read circuit to the second signal line based on the read control signal.

A method, system, and storage medium are provided for simulating devices or circuits containing magnetic tunnel junctions. The method includes: applying a write voltage or write current to the device or circuit to be simulated; obtaining the magnitude and direction of the write voltage or the magnitude and direction of the write current; providing the magnitude and direction of the write voltage or the magnitude and direction of the write current to a constructed model for the magnetic tunnel junction; and simulating the device or circuit using the constructed model for the magnetic tunnel junction, wherein the free layer in the model is constructed as a plurality of parallel and independent hysteresis units. This approach allows for a more refined description of the multiple states of the magnetic tunnel junction, its stability, and write accuracy, thereby making the simulation of such devices or circuits more accurate and flexible.

A memory device is provided, including a memory array; a current limit circuit coupled to the memory array; and a write assist unit that generates a first voltage to the current limit circuit and controls, in response to a control signal, a second voltage coupled between the current limit circuit and the memory array. The current limit circuit transmits at least one write current flowing through the memory array in response to the first voltage and the second voltage.

The application relates to a three-dimensional phase change memory high-reliability write circuit, which comprises a bit line data sensing module, a row and column address sensing module and a lookup table module. The bit line data sensing module is used for determining the data state on a selected bit line; the row and column address sensing module is used for determining the block address to which a selected unit belongs according to the row address and the column address of the selected unit; the lookup table module is used for taking the data state on the selected bit line and the block address to which the selected unit belongs as indexes to find the optimal write current amplitude from a write current amplitude configuration table; and the write driving module is used for outputting the write current with the optimal write current amplitude to the selected unit. The application can improve the reliability of the three-dimensional phase change memory.

A memory device including magnetic memory elements is disclosed. The memory device includes an array of memory cells including a first region and a second region, the second region configured to store a value of a write voltage, the write voltage based on a value of a reference resistor used to determine whether a programmed memory cell is in a parallel state or an anti-parallel state; a voltage generator configured to generate a code value based on the value of the write voltage; and a write driver configured to drive a write current based on the code value, the write current being a current used to store data in the first region.

The application provides a read-write method, a read-write circuit and SOT-MRAM based on SOT-MRAM. The read-write method comprises the following steps: inputting a write current into a SOT layer to reverse the magnetization direction of a free layer in a magnetic tunnel junction, so that the magnetization directions of the free layer and a reference layer are in a parallel state or an anti-parallel state; reading the capacitance value of the magnetic tunnel junction; and determining whether the magnetic tunnel junction is in a first state or a second state according to the capacitance value of the magnetic tunnel junction. The capacitance value of the magnetic tunnel junction is read, and whether the magnetic tunnel junction is in the first state or the second state is determined according to the capacitance value of the magnetic tunnel junction, so that the data '0' and '1' in the storage unit are recognized and read. The SOT-MRAM in the magnetic capacitance type has lower requirements for the growth conditions, material selection and sensitivity of the read circuit of the MTJ relative to the SOT-MRAM in the resistance type, so that the growth conditions and material selection of the magnetic tunnel junction of the SOT-MRAM in the magnetic capacitance type are not as harsh as those of the SOT-MRAM in the magnetic resistance type, and the difficulty of manufacturing and reading the SOT-MRAM is reduced.