1910 results about "Low resistance" patented technology

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a semiconductor device with an integrated heat dissipation function for a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The single MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, the profile of the cross section of the grid electrode is in an H shape, and the grid electrode comprises two longitudinal parts and a transverse part used for bridging the two longitudinal parts. According to the invention, the H-shaped gate structure is in bridge connection with the double longitudinal grooves through the transverse part, so that the channel width is increased, and the on-resistance is reduced; a current path is further optimized by combining a metal deposition layer and a heavily doped N + layer in the bottom doping layer; and the metal layer is connected in parallel to conduct electricity, so that the resistance is reduced, and the heavily doped N + layer inhibits the JFET effect, so that the resistance is reduced by more than 10%.

The invention relates to the technical field of crystal material preparation, in particular to a ternary layered selenide Ge3Sb4Se7 semiconductor material and a preparation method thereof. The preparation method of the ternary layered selenide Ge3Sb4Se7 semiconductor material comprises the following steps that S001, germanium powder, antimony powder and selenium powder with the molar ratio being 3: 4: 7 serve as raw materials, the temperature is increased to 900-950 DEG C under the vacuum condition, and heat preservation is conducted for 12-24 h at the temperature; s002, after heat preservation is finished, the temperature is reduced to 475-500 DEG C at the cooling rate of 1-5 DEG C / min, and heat preservation is conducted for 3-5 days at the temperature; and after heat preservation is finished, furnace cooling or quenching cooling is performed to reach the room temperature, and the layered ternary selenide single-phase material with the chemical formula being Ge3Sb4Se7 is obtained. The ternary layered selenide Ge3Sb4Se7 semiconductor material prepared by the invention is a single-phase material and has the characteristics of low thermal conductivity and low resistivity, so that the ternary layered selenide Ge3Sb4Se7 semiconductor material has application potential in the fields of thermoelectric devices, photoelectric detection and the like.

The invention discloses a high-conductivity palladium alloy for a chip test probe and a preparation method of the high-conductivity palladium alloy, and the palladium alloy comprises the following components in percentage by mass: 50-58% of Pd, 35-40% of Cu, 5-10% of Ag, 0.05-1.0% of Cr and 0.1-1.5% of auxiliary elements, the auxiliary element is selected from at least one of Al, Zn, In and Si; the resistivity of the palladium alloy is 8.0 mu omega.cm or below, the Vickers hardness is 450 HV or above, the 90-degree bending frequency is 8 or above, the tensile strength is 1500 MPa or above, and the ductility is 6% or above, the palladium alloy is subjected to pre-smelting and secondary smelting, and at least part of Cu and at least part of Cr in raw materials are mixed and pre-smelted to obtain a copper-chromium intermediate alloy; and the copper-chromium intermediate alloy and the remaining raw materials are mixed and then subjected to secondary smelting. The palladium alloy can meet the urgent requirements of probes in various forms on low resistance, high plasticity and toughness, fatigue resistance, mechanical strength and the like at the same time.

The invention relates to the technical field of conductive copper paste, in particular to conductive copper paste prepared by combining liquid nonferrous metal with graphene and a preparation method of the conductive copper paste. The preparation method comprises the following steps: weighing nano-copper coated graphene composite powder, a liquid nonferrous metal, a binder, trifluoropropyltrimethoxysilane, an auxiliary agent and copper powder, and then preparing trifluoropropyltrimethoxysilane into a dilute solution; copper powder and the nano-copper coated graphene composite powder are mixed to obtain composite powder; the liquid nonferrous metal and the composite powder are stirred to obtain metal paste; and adding a resin solution and an auxiliary agent into the metal paste to form printing paste, and then standing and curing. According to the conductive copper paste, the liquid nonferrous metal serves as a main binding phase, the defect that the welding thrust is low due to a traditional resin system is overcome, the problems of dispersion and interface compatibility are solved through cooperation of the nano-copper-coated graphene and the silane coupling agent, and finally the conductive copper paste with extremely low resistance, high stability and ultrahigh welding thrust is obtained.

Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some embodiments, thin metal oxynitride or metal nitride nucleation layers are deposited followed by deposition of a pure metal conductor. The nucleation layer is amorphous, which templates large pure metal film grain growth and reduced resistivity. Further, certain embodiments of the methods described below convert most or all of the metal oxynitride nucleation layer to a pure metal layer, further lowering the resistivity.

The invention relates to the technical field of lithium ion batteries, in particular to a composite lithium-rich manganese-based positive electrode material and a preparation method and application thereof. The composite lithium-rich manganese-based positive electrode material is of a three-layer structure and sequentially comprises a lithium-rich manganese-based oxide positive electrode material matrix, a first coating layer and a second coating layer from inside to outside, the first coating layer is a mixture of halide solid electrolyte and lithium-containing oxide; and the second coating layer is an oxide solid electrolyte. The conductivity of a contact interface with a positive electrode material can be improved, the resistance is reduced, the moisture absorption degradation of halide is inhibited, the packaging difficulty is reduced, and the cycle performance of the halide-added solid electrolyte after moisture absorption is improved.

The invention discloses a household wall-mounted energy storage power supply, and belongs to the technical field of energy storage equipment, the household wall-mounted energy storage power supply comprises a hanging plate, a power supply body and an equipment box, the top of one side of the power supply body is fixedly provided with a hook, the hook is inserted into the hanging plate, the bottom of the power supply body is provided with a locking mechanism, and the locking mechanism is connected with the hanging plate. An electromagnet, a linkage mechanism, a connection mechanism, a slide rheostat, a monitoring mechanism, a buffer mechanism, a controller and a stop button are arranged in the equipment box, the electromagnet is connected with the power source body in series, the linkage mechanism comprises a sealing box, a piston plate, a sealing cylinder and an iron sheet, the iron sheet is embedded in the piston plate, and the piston plate is connected with the sealing cylinder. And a sealing disc is mounted in the sealing cylinder in a sliding manner. The transverse rod is linked with the slide rheostat to automatically adjust the resistance of the cooling fan, the resistance is reduced when the current is increased to improve the power of the fan, the dynamic matching of the cooling intensity is realized, and in addition, the system is additionally provided with multiple safety protection mechanisms.

The invention discloses multi-solvent synergistically activated low-temperature semi-sintered copper paste and a preparation method and application thereof, and belongs to the technical field of conductive paste. The multi-solvent synergistically activated low-temperature semi-sintered copper slurry comprises the following raw material components in percentage by mass: 82-88% of conductive filler, 2-3% of a resin carrier, 4-7% of an activating solvent, 4-7% of a dispersing solvent and 2-3% of a curing agent. Through cooperation of multiple solvents, full-stage activation of the copper particles is achieved, pre-connection and sintering of the copper particles before resin is completely crosslinked and cured are promoted, densification of the overall structure is improved, the insulation barrier effect of the resin is effectively avoided, the resistivity is reduced, meanwhile, inhibition of the resin on sintering of the copper particles is solved, and the service life of the copper particles is prolonged. And good balance between conductivity and interface adhesion is realized. Through resin curing, chemical bonding between the slurry and the substrate can be enhanced, a metal bond network among copper particles is expanded, and mechanical connection stability and electrical performance are guaranteed.

Provided is a semiconductor device that can be easily manufactured. This semiconductor device has a substrate, a transistor and element isolation layer formed on the substrate, first to fifth conductive layers, a first insulating layer, and first to fifth plugs. The transistor has a first low resistance region, a second low resistance region, and a portion of the first conductive layer. Each of a third conductive layer and a fourth conductive layer is a columnar body extending in a direction perpendicular to the substrate. The first low resistance region and the second conductive layer are connected via the first plug. The second low resistance region and the third conductive layer are connected via the second plug and the second plug. The fourth plug, the fifth plug, and the fourth conductive layer are connected to each other at positions overlapping the element isolation layer. The first insulating layer has a region in contact with a side surface and a top surface of the third conductive layer and the fourth conductive layer, and the fifth conductive layer extends in a direction approximately parallel to the first conductive layer in a planar view and has a region in contact with a side surface and a top surface of the first insulating layer.

A semiconductor device that includes a substrate, a crystalline bottom electrode layer on an upper side of the semiconductor substrate, a conductive crystalline metal layer above the crystalline bottom electrode layer, and a conductive oxide layer above the conductive crystalline metal layer. The conductive oxide layer has a low resistance. The semiconductor device also includes a magnetic tunnel junction (MTJ) above the conductive crystalline metal layer, the MTJ including a tunnel barrier layer, a free layer on a first side of the tunnel barrier layer and a reference layer on a second side of the tunnel barrier layer opposite the first side.

The invention relates to the technical field of crystal material preparation, in particular to a layered selenide Ge3Sb2Se5 semiconductor material and a preparation method thereof. The preparation method of the layered selenide Ge3Sb2Se5 semiconductor material comprises the following steps: grinding a Ge3Sb4Se7 material, putting the ground Ge3Sb4Se7 material into a quartz tube, adding iodine particles, performing vacuum packaging in the quartz tube, putting one end, with raw materials, of the quartz tube into a high-temperature region, and putting one end, without raw materials, of the quartz tube into a low-temperature region; raising the temperature to 400 + / -25 DEG C at the low-temperature region end and 500 + / -25 DEG C at the high-temperature region end, preserving heat for 7 days, and naturally cooling to room temperature to obtain the Ge3Sb2Se5 semiconductor material. The crystal structure of the Ge3Sb2Se5 semiconductor material belongs to an orthorhombic system, and the Ge3Sb2Se5 semiconductor material has the characteristics of low thermal conductivity and low resistivity. According to the preparation method disclosed by the invention, the Ge3Sb2Se5 semiconductor material can be stably prepared, and a material is provided for physical property research of the Ge3Sb2Se5 semiconductor material and preparation of semiconductor photoelectric devices and the like.

Embodiments of the present disclosure provide integrated circuit chips including via towers formed with stacks of conductive layers formed during fabrication of semiconductor devices and interconnect structures of the integrated circuit chips. The via towers may be connected to provide electrical power to subsequently stacked integrated circuit chips. The via towers according to the present disclosure reduce cost of fabrication because the via towers are fabricated without additional processing sequences. The via towers may be integrated in the circuit layout to form a low resistance power rail, therefore, improving performance.

A skip-level through-silicon via structure is provided that enables low resistance via connection for backside power distribution by skipping one or more intermediate backside metal layers. The skip-level through-silicon via structure can enable a greater design flexibility for power grid. The skip-level through-silicon via structure has a large size that provides lower through-silicon via resistance as compared with conventional through-silicon via structures.

The invention provides a dual damascene process method, and relates to the technical field of semiconductors. The dual damascene process method comprises the following steps: sequentially forming a dielectric layer, a patterned first hard mask layer, a first planarization layer and a patterned second hard mask layer on a substrate; performing dry etching by using the second hard mask layer to form a through hole stopped on the surface of the substrate; removing the second hard mask layer and the first planarization layer; performing dry etching by using the first hard mask layer to form a groove; removing the first hard mask layer; and forming a metal layer to fill the through hole and the groove so as to obtain the dual damascene structure. According to the process method, the connectivity of the formed through hole can be ensured, and a low-resistance channel of a metal interconnection structure is subsequently formed in the bottom area of the through hole; meanwhile, the first hard mask layer is removed after the through hole is formed, accurate transmission of the key size of the through hole can be ensured, the accuracy of the key size of the subsequently formed metal interconnection structure is improved, and therefore the yield of a chip product and the performance of a device are improved.

The invention relates to the technical field of metal materials, and discloses a composite metal material based on micro-nano porous copper powder, which is composed of the following components: a matrix is micro-nano porous copper powder with the particle size of 50-500 nanometers, the porosity is 30-80%, and the pore diameter is 20-200 nanometers; the metal additive comprises 5-20 wt% of aluminum powder and 3-15 wt% of nickel powder; the functional additive comprises 1 to 8 weight percent of titanium powder, 0.5 to 5 weight percent of graphene and 0.3 to 3 weight percent of a carbon nano tube; a nickel-titanium alloy coating with the thickness of 50-500 nanometers is formed on the surface of the micro-nano porous copper powder through electrochemical deposition. Through the graded hole design of the micro-nano porous copper powder, a main hole channel provides a rapid electron transmission path, the powder gap stress is eliminated in the low-temperature pre-pressing stage, and atom diffusion and densification are promoted in the high-temperature and high-pressure stage, so that the resistance can be effectively reduced, the loss of energy in the transmission process is reduced, and the energy transmission efficiency of the whole system is improved.

The present invention discloses a plug-in type detachable layered carpet, which comprises an upper carpet body and a lower carpet body, wherein the upper carpet body and the lower carpet body are respectively provided with 2-3 layers of fabric, and the upper carpet body and the lower carpet body are arranged one above the other and the adjacent surfaces can be connected in a plug-in manner, so that on the one hand, the top screen layer and the supporting layer respectively belonging to the upper carpet body and the lower carpet body can be quickly disassembled and adjusted in position with low resistance, on the other hand, the upper carpet body can be cleaned by at home independently, and the pattern is less likely to be scratched after washing.

The invention belongs to the technical field of flexible transparent film electrodes, and particularly relates to a flexible indium tin oxide film electrode, a preparation method and a flexible solar cell. According to the flexible indium tin oxide thin film electrode provided by the invention, after the processes of pre-treating substrates such as PET, covering an acrylic resin hard coating, depositing a SiO2 transition layer and the like, the adhesive force of the indium tin oxide conductive thin film is improved through the indium tin oxide conductive thin film deposited through alternate radio frequency magnetron sputtering and direct current pulse magnetron sputtering; the bottom layer deposited by radio frequency magnetron sputtering is used for providing an interface seed layer for the fluorine-doped indium tin oxide conductive thin film layer deposited by direct current pulse magnetron sputtering and having high carrier concentration and low resistance, and the top layer is used for providing protection, so that the conductivity, environmental stability and other properties of the flexible indium tin oxide thin film electrode are improved; the conductive performance is not easy to attenuate, the long-term use stability is good, and the technical problem that in the prior art, a flexible transparent film electrode is low in performance is solved.

The invention discloses a high-performance conductive adhesive doped with conductive nanoparticles, and belongs to the technical field of conductive adhesives. The high-performance conductive adhesive provided by the invention is prepared from the following raw materials in parts by weight: 50 to 100 parts of vinyl liquid silicone rubber, 100 to 400 parts of modified silver coated copper powder, 1 to 10 parts of nano silver powder I, 1 to 10 parts of epoxy silane modified prepolymer, 3 to 30 parts of hydrogen-containing silicone oil, 0.1 to 5 parts of platinum catalyst and 0.05 to 1 part of inhibitor. The silver-coated copper powder and the epoxy silane are modified, so that the conductivity and the binding power of the conductive adhesive are greatly improved, and the epoxy silane modified prepolymer can form strong covalent bond combination with the surface of an adhered object through a high-density epoxy group of the epoxy silane modified prepolymer; the nano-silver bulges on the surface of the modified silver coated copper powder increase the effective contact area and the number of contact points among the conductive filler particles, so that the conductive adhesive has the characteristics of high conductivity, low resistance, high adhesive strength and strong toughness.

The invention discloses a low-resistance high-efficiency air filter, and relates to the field of air filters, the low-resistance high-efficiency air filter comprises an upper shell, a lower shell, a ventilation end cover, a supporting shell installed in the upper shell and a filter element arranged in the supporting shell, a conical flow collecting barrel is arranged in the lower shell, the bottom of the conical flow collecting barrel is communicated with a water storage barrel, a connecting support is fixed in the water storage barrel, and the connecting support is connected with the ventilation end cover. A threaded connector is arranged at the bottom of the connecting support. The separation structure is connected between the inner wall of the upper shell and the outer wall of the supporting shell and is used for separating rainwater carried in the airflow; a drainage structure capable of preventing air leakage is arranged in the water storage cylinder; rainwater is separated from air through the arranged separation structure, so that the probability that the filter element is wetted by the rainwater can be greatly reduced, the filter element can effectively intercept dust and impurities, meanwhile, dust can be possibly carried in the rainwater, the dust falls down along with the rainwater, and therefore the filtering burden of the filter element can be relieved.

The present invention discloses a memristor based on a GaN / PEDOT:PSS planar heterojunction and a preparation method thereof, including a substrate; a GaN thin film, the GaN thin film is p-type conductive, and the GaN thin film is attached to the surface of the substrate; a PEDOT:PSS organic layer, the PEDOT:PSS organic layer is p-type conductive, and the PEDOT:PSS organic layer is attached to the surface of the GaN thin film; a first electrode, forming an ohmic contact with the GaN thin film; and a second electrode, forming an ohmic contact with the PEDOT:PSS organic layer. Through the combined action of the space charge layer generated by the GaN / PEDOT:PSS heterojunction and the nitrogen vacancies in the GaN thin film, the present invention can realize the switching of the device resistance between the high resistance state and the low resistance state under the control of an external voltage, and realize the non-volatile writing and erasing of data.

The invention relates to the technical field of lithium ion batteries, in particular to a chromium-molybdenum double-doped lithium iron phosphate material as well as a preparation method and application thereof. The preparation method is used for solving the problems of low capacity, low electronic conductivity and poor cycling stability of the existing lithium iron phosphate material. According to the preparation method, chromium-molybdenum is doped into lithium iron phosphate, and the bond energy of a Cr-O bond and a Mo-O bond is stronger than that of a Fe-O bond, so that the dissolution loss of Fe < 2 + > in long-term circulation is reduced, and the battery capacity and the intrinsic electron conductivity of the material are improved; lithium iron phosphate is coated with nitrogen-doped carbon nanotubes, and nitrogen is doped in graphite crystal lattices of the carbon nanotubes, so that additional free electrons are provided, the intrinsic conductivity is improved, the resistance is reduced, the rate capability is improved, and the cycle life is prolonged; the polyaniline coating layer forms a barrier layer on the surface of the lithium iron phosphate particles, so that the cycle performance and the battery capacity are improved; the three components cooperate to improve the capacity, conductivity, rate capability and cycling stability of the material.

The invention discloses a design method of a hollow cup diamond winding, which is characterized in that aiming at the diamond winding of a hollow cup motor, on the basis of ideal power, line load and other parameters of the motor, winding inner and outer diameter parameters are preliminarily calculated, enameled wire specifications are selected, coil layer number, span and other parameters are determined, coil turns, fillet radius and the like are calculated, and then coil resistance and bestrewing rate are obtained. And correcting the parameters according to a calculation result, carrying out comprehensive simulation calculation on the motor, and correcting again until the overall design parameters of the motor are met. Through the implementation of the method, the current situation that domestic hollow cup windings depend on reverse derivation design is broken through, forward design is achieved, various key parameters can be accurately calculated under the limitation of specific space sizes, the design problem is solved, and in addition, the full rate of the windings can be increased and the resistance can be reduced through parameter optimization. The design result can be directly applied to motor simulation and actual production, the research and development period is shortened, and the development of the coreless motor industry is promoted.

A stacked I / O connector for use with a high speed, high density transceiver that generates a large amount of heat. The connector may be formed with a web-like housing into which leadframe assemblies are inserted. The web-like housing may have openings in the front, back, top and / or sides, enabling airflow through the connector with little resistance. Sidewall openings may open into a channel between the housing and a wall of cage, enabling air flowing to cool transceivers inserted into the cage to pass through the connector assembly with low resistance and high cooling efficiency. A cage for the connector may have openings selectively positioned such that air flowing through the cage to cool transceivers mated to the I / O connector may pass through the connector with low resistance, enhancing cooling efficiency. Such a connector may be used with OSFP transceivers to meet signal integrity and thermal requirements at 112 GBps and beyond.

The invention discloses an AlGaInP red light LED chip structure with a polarization-induced tunnel junction and a preparation method thereof. The chip structure sequentially comprises a GaAs substrate, an n-type GaAs buffer layer, an n-type etching barrier layer, an n-type GaAs ohmic contact layer, an n-type limiting layer, a non-doped InGaP / quantum well structure, a p-type spacer layer, a p-type AlGaInP polarization-induced doping layer, an insertion layer and an n-type ohmic contact layer from bottom to top. Wherein the p-type AlGaInP polarization induction doping layer introduces a piezoelectric polarization electric field through an Al component gradual change design, high-density two-dimensional hole gas is formed through induction, and the high-Al component insertion layer and the n-type ohmic contact layer form a tunnel junction; according to the invention, the problems of low p-type doping efficiency and high resistivity of the AlGaInP material with high Al component are fundamentally solved, the epitaxial structure and the chip process are simplified, the series resistance of the chip is reduced, the luminous efficiency is improved, the yield is improved, and the method has remarkable technical and commercial values.

Embodiments of the present invention advantageously provide a method of manufacturing a semiconductor device having multiple threshold voltage capability in a scaled space between nanosheets in an advanced GAA node. One or more embodiments provide an integration scheme to advantageously reduce gate resistance by incorporating n- / p-dipoles with an intermediate bandgap metal with low resistance to achieve a desired work function and low resistance metal gate. In one or more embodiments, the intermediate bandgap metal is used to fill the nanosheets and as a liner for subsequent filling with the low resistance metal. After dipole processing, instead of filling surrounding gate nanosheets with conventional n or p metals, in one or more embodiments, the nanosheets are advantageously filled with a single work function intermediate energy gap metal to achieve n and p work functions. If the work function is shifted in either of the band edges of the P-dipole or the N-dipole after dipole processing, the intermediate bandgap material may also shift the band edges in the opposite manner.

A number of MOSFET architectures provide high-voltage capability (both drain-source breakdown voltage BVDSS and ON-state breakdown voltage BVON), low current leakage, and extended linearity. Embodiments of the invention overcome the limitations of conventional NEDMOS and LDMOS device designs by providing a low-resistance path for hole collection and by purposefully exhibiting multiple voltage thresholds VTH in different segments of the device. Embodiments includes NEDMOS and LDMOS device designs having multiple body contact regions for improved hole collection, sub-gate doped stripes or segments for even better hole collection and linearity, and sub-gate doped edge regions for increased local VTH and thus decreased current leakage. P– hole-collection stripes and P+ body contact regions may be formed of a semiconductor material that includes germanium. The inventive MOSFETs may be arranged as multi-MOSFET array elements, and multiple array elements may be arranged in a larger array.

Methods for depositing a metal contact stack on a substrate are described. The metal stack includes a metal cap layer and a molybdenum conductor layer. The method includes depositing the metal cap layer on the substrate by physical vapor deposition (PVD) and depositing the molybdenum conductor layer by atomic layer deposition (ALD) on the metal cap layer.

The invention relates to the technical field of solar cells, and provides a photovoltaic module, a laminated cell, a back contact cell and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate, wherein a second surface of the substrate comprises a first region and a second region; forming a tunneling layer on the second surface; forming a first polycrystalline silicon layer on the surface of the tunneling layer by adopting a first deposition process; forming a second polycrystalline silicon layer on the surface of the first polycrystalline silicon layer by adopting a second deposition process; the temperature and pressure of the first deposition process are higher than those of the second deposition process; carrying out doping treatment, and converting the first polycrystalline silicon layer and the second polycrystalline silicon layer into a first semiconductor doped layer; forming a second semiconductor doping layer on the second region; a first electrode and a second electrode are formed, the first electrode being in electrical contact with the first semiconductor doped layer and the second electrode being in electrical contact with the second semiconductor doped layer. According to the invention, low-resistance ohmic contact between the first semiconductor doping layer and the first electrode is realized at least while a good surface passivation effect is ensured.

The object of the present invention is to provide a silencer that does not become brittle at low temperatures even with low-temperature gases, does not cause clogging, and has low resistance. [Solution] The silencer (A1, A2) comprises a gas inlet (4) through which low-temperature gas is introduced, a gas outlet (5) through which the low-temperature gas is discharged, and a gas passage (6) through which the low-temperature gas flows, and is provided with a passage-forming member (1) whose wall surface is made of mesh-like metal, a sound-absorbing material (2) that covers the outer periphery of the passage-forming member, and an exterior material (3) that covers the outer periphery of the sound-absorbing material, thereby reducing the sound emitted from the gas outlet.

Provided herein are low resistance metallization stack structures for 3D-NAND applications and related methods of fabrication. In some embodiments, thin metal oxynitride nucleation layers are deposited on dielectric material followed by deposition of a pure metal conductor using process conditions that increase non-molybdenum component element content at the oxynitride-dielectric interface. Certain embodiments of the methods described below convert less than all of the metal oxynitride nucleation layer to a pure metal layer, further lowering the resistivity.