3213 results about "Low resistance" patented technology

The invention discloses a composite positive electrode material and a preparation method thereof, a positive plate and a lithium ion battery. The composite positive electrode material comprises lithium iron phosphate and a carbon coating layer coating the surface of the lithium iron phosphate, wherein the integral intensity ratio ID / IG of a D peak to a G peak of the carbon coating layer in a Raman spectrum is 0.2-0.9, and the resistivity of the composite positive electrode material is 0.1-10 omega.cm. According to the preparation method, the graphitization degree of the carbon coating layer is controlled within a proper range (ID / IG is 0.2-0.9), so that good conductivity is ensured, and structural instability caused by excessive graphitization is avoided. The moderate graphitization degree is beneficial to formation of an ordered carbon layer structure, provides more electron transport channels and reduces the potential barrier of electron migration, so that the conductivity of the composite material is greatly improved, and the resistivity is reduced to an excellent level of 0.1-10 omega.cm.

Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. The methods involve forming bulk conductive films on thin low resistivity transition metal layers that have large grain size. The bulk conductive films follow the grains of the low resistivity transition metal films, resulting in large grain size. Also provided are devices including template layers and bulk films.

The invention belongs to the technical field of crystal growth, and provides a low-resistivity silicon carbide single crystal growth method and system and a single crystal, silicon carbide powder is uniformly paved at the bottom of a graphite crucible, metal carbide material particles are uniformly paved on the surface of the silicon carbide powder, and silicon carbide seed crystals are adhered to the top of the graphite crucible; the graphite crucible is sealed, and the interior of the graphite crucible is vacuumized; heating the graphite crucible subjected to vacuumizing treatment, filling carrier gas into the graphite crucible, then slowly replacing the carrier gas with doped source gas, slowly increasing the growth pressure to a set pressure, and growing a buffer layer; after the growth of the buffer layer is completed, changing the growth condition to grow the heavily doped silicon carbide single crystal; and after the growth of the crystal is completed, cooling the graphite crucible subjected to vacuumizing treatment, so that the crystal is naturally cooled, and the low-resistivity silicon carbide single crystal is obtained. The doping concentration of the silicon carbide single crystal can be improved, and the resistivity of the silicon carbide material can be reduced.

A connector that enables electronic assemblies to be efficiently configured for any of multiple power requirements. The connector may have a mating interface, which may mate with a power supply, a mounting interface for attaching the connector to a PCB and a power tap off interface. The power tap off interface may enable distribution of a portion of the power received through the mating interface to remote locations on the PCB. The connector may be assembled with conductive element subassemblies, enabling efficient configuration of the connector with conductive elements with and without mating contact portion for power tap off. Each subassembly may include a member to which other members with mating contact portions and / or tails for a mounting interface are attached. A projection providing mechanical support for the power tap off interface may be angled relative to the mating interface such that the connector provides lower resistance to airflow, which may lower the cost and / or enable enhanced performance of an assembly using such a connector.

The invention discloses a server power supply system and a server, relates to the field of server power supply, and is used for solving the problem of high energy loss in a traditional alternating current power supply architecture. The power conversion module converts the power supply into high-voltage direct current with the voltage not lower than the preset voltage, the high-voltage direct current is transmitted to the power distribution board of the server through the bus copper bar, and the bus copper bar serves as a transmission medium of the high-voltage direct current and has low resistance and high current-carrying capacity. Extra loss caused by electromagnetic induction and a capacitance effect in alternating current transmission is avoided; high-voltage direct current is directly input to the power distribution board, so that multiple times of conversion in an intermediate link are avoided, and energy loss in the conversion process is reduced; and the power distribution board directly converts the high-voltage direct current into the voltage required by the load, so that the loss of multi-stage conversion in the traditional architecture is reduced. According to the invention, the power transmission efficiency is improved, the energy loss is reduced, and the requirement of a modern high-computing-power and high-energy-consumption server for efficient power supply is met.

Metallization schemes involve atomic layer deposition (ALD) of molybdenum (Mo) and in some embodiments, ALD of Mo in a feature without a barrier layer. In some embodiments, deposition of the ALD Mo film may be followed by chemical vapor deposition (CVD) or physical vapor deposition (PVD) of a Mo film. In some embodiments, the CVD or PVD Mo film is part of the metallization stack. In other embodiments, the CVD or PVD Mo film is deposited as a sacrificial overburden layer. In some embodiments, deposition of the ALD Mo film may be followed by CVD or PVD of another metal such as tungsten (W). In some embodiments, the CVD or PVD W film is part of the metallization stack. In other embodiments, the CVD or PVD W film is deposited as a sacrificial overburden layer.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a semiconductor device with an integrated heat dissipation function for a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The single MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, the profile of the cross section of the grid electrode is in an H shape, and the grid electrode comprises two longitudinal parts and a transverse part used for bridging the two longitudinal parts. According to the invention, the H-shaped gate structure is in bridge connection with the double longitudinal grooves through the transverse part, so that the channel width is increased, and the on-resistance is reduced; a current path is further optimized by combining a metal deposition layer and a heavily doped N + layer in the bottom doping layer; and the metal layer is connected in parallel to conduct electricity, so that the resistance is reduced, and the heavily doped N + layer inhibits the JFET effect, so that the resistance is reduced by more than 10%.

To provide a method for manufacturing an electrode with reduced resistance.SOLUTION: A manufacturing method disclosed herein includes: a first mixing step (S1) of mixing a first electrode active material with a pore-forming agent to obtain a mixture; a second mixing step (S2) of mixing the mixture with a binder to obtain an electrode mixture; an application step (S3) of applying the electrode mixture onto a current collector; and a heat treatment step (S6) of heat-treating the electrode mixture on the current collector to remove the pore-forming agent.SELECTED DRAWING: Figure 5

The invention relates to the technical field of crystal material preparation, in particular to a ternary layered selenide Ge3Sb4Se7 semiconductor material and a preparation method thereof. The preparation method of the ternary layered selenide Ge3Sb4Se7 semiconductor material comprises the following steps that S001, germanium powder, antimony powder and selenium powder with the molar ratio being 3: 4: 7 serve as raw materials, the temperature is increased to 900-950 DEG C under the vacuum condition, and heat preservation is conducted for 12-24 h at the temperature; s002, after heat preservation is finished, the temperature is reduced to 475-500 DEG C at the cooling rate of 1-5 DEG C / min, and heat preservation is conducted for 3-5 days at the temperature; and after heat preservation is finished, furnace cooling or quenching cooling is performed to reach the room temperature, and the layered ternary selenide single-phase material with the chemical formula being Ge3Sb4Se7 is obtained. The ternary layered selenide Ge3Sb4Se7 semiconductor material prepared by the invention is a single-phase material and has the characteristics of low thermal conductivity and low resistivity, so that the ternary layered selenide Ge3Sb4Se7 semiconductor material has application potential in the fields of thermoelectric devices, photoelectric detection and the like.

The invention discloses a high-conductivity palladium alloy for a chip test probe and a preparation method of the high-conductivity palladium alloy, and the palladium alloy comprises the following components in percentage by mass: 50-58% of Pd, 35-40% of Cu, 5-10% of Ag, 0.05-1.0% of Cr and 0.1-1.5% of auxiliary elements, the auxiliary element is selected from at least one of Al, Zn, In and Si; the resistivity of the palladium alloy is 8.0 mu omega.cm or below, the Vickers hardness is 450 HV or above, the 90-degree bending frequency is 8 or above, the tensile strength is 1500 MPa or above, and the ductility is 6% or above, the palladium alloy is subjected to pre-smelting and secondary smelting, and at least part of Cu and at least part of Cr in raw materials are mixed and pre-smelted to obtain a copper-chromium intermediate alloy; and the copper-chromium intermediate alloy and the remaining raw materials are mixed and then subjected to secondary smelting. The palladium alloy can meet the urgent requirements of probes in various forms on low resistance, high plasticity and toughness, fatigue resistance, mechanical strength and the like at the same time.

The invention provides a low-resistance separation trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, performing ion implantation, and forming a P-type source region, a low-resistance region, a P-type well region and an N-type source region; a barrier layer is formed again, and a first insulating medium layer and a second insulating medium layer are formed through etching and deposition; re-forming a barrier layer, etching and depositing metal, and respectively forming a first gate metal layer and a second gate metal layer; forming a barrier layer again, etching and depositing metal, and forming a first source metal layer; and forming a barrier layer again, etching, depositing metal, forming a second source metal layer, and removing the barrier layer to complete preparation. And the driving loss and the body diode loss of the device are reduced.

Package substrate with metallization layer(s) that includes an additional metal pad layer to facilitate reduced via size for reduced bump pitch, and related integrated circuit (IC) packages and fabrication methods. An additional metal pad(s) is provided in an insulating layer of a metallization layer(s) of the package substrate in which a via(s) is formed to reduce vertical connectivity distance between metal interconnects in adjacent metallization layers electrically coupled together by the via. This can reduce the aspect ratio and size of the via thereby allowing metal interconnects that are electrically coupled to the via to also be reduced in size (e.g., width) while still supporting an aligned, low resistance connection between the via(s) and the metal interconnects. Being able to reduce the size (e.g., width) of the metal interconnects can reduce bump pitch of the package substrate, which can facilitate a higher density of die / bump connections to the package substrate.

The embodiment of the utility model provides a resistor calibration circuit, a resistor calibration device and an electronic device. The resistor calibration circuit comprises a current source module used for outputting a reference current; the standard resistor module is connected with the current source module to receive the reference current and generate a reference voltage; in the working process of the resistor calibration circuit, a resistor to be calibrated is connected with the current source module to receive the reference current and generate a voltage to be measured, and the analog-to-digital converter is connected with the standard resistor module to perform analog-to-digital conversion on the voltage to be measured based on the reference voltage. According to the resistance calibration circuit, the analog-to-digital converter in the module to be measured is multiplexed for resistance calibration, an additional high-precision measurement calibration system is not needed, and the resistance can be calibrated only by providing the current source module and the standard resistance module, so that the resistance calibration cost is reduced.

The invention discloses a phosphorus-antimony co-doped monocrystalline silicon rod, a preparation method and application, in the phosphorus-antimony co-doped monocrystalline silicon rod, the antimony element concentration is 2.3 * 10 < 16 > atoms / cm < 3 >-1.17 * 10 < 14 > atoms / cm < 3 >, and the phosphorus element concentration is 7.66 * 10 < 15 > atoms / cm < 3 >-3.9 * 10 < 13 > atoms / cm < 3 >. According to the embodiment of the invention, the silicon single crystal rod is doped with the phosphorus element and the antimony element at the same time, and when only the phosphorus element is doped in the silicon single crystal rod, the resistivity of the obtained silicon single crystal rod is usually high at the head and low at the tail; when only the antimony element is doped in the single crystal silicon rod, due to the fact that antimony is extremely volatile, the controllability of antimony doping in the preparation process is relatively low, and the resistivity is prone to occurrence of the conditions that the head is low and the tail is high, and therefore the difference of the resistivity of the single crystal silicon rod can be reduced through co-doping of phosphorus and antimony in the implementation mode of the application.

The invention relates to the technical field of conductive copper paste, in particular to conductive copper paste prepared by combining liquid nonferrous metal with graphene and a preparation method of the conductive copper paste. The preparation method comprises the following steps: weighing nano-copper coated graphene composite powder, a liquid nonferrous metal, a binder, trifluoropropyltrimethoxysilane, an auxiliary agent and copper powder, and then preparing trifluoropropyltrimethoxysilane into a dilute solution; copper powder and the nano-copper coated graphene composite powder are mixed to obtain composite powder; the liquid nonferrous metal and the composite powder are stirred to obtain metal paste; and adding a resin solution and an auxiliary agent into the metal paste to form printing paste, and then standing and curing. According to the conductive copper paste, the liquid nonferrous metal serves as a main binding phase, the defect that the welding thrust is low due to a traditional resin system is overcome, the problems of dispersion and interface compatibility are solved through cooperation of the nano-copper-coated graphene and the silane coupling agent, and finally the conductive copper paste with extremely low resistance, high stability and ultrahigh welding thrust is obtained.

Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some embodiments, thin metal oxynitride or metal nitride nucleation layers are deposited followed by deposition of a pure metal conductor. The nucleation layer is amorphous, which templates large pure metal film grain growth and reduced resistivity. Further, certain embodiments of the methods described below convert most or all of the metal oxynitride nucleation layer to a pure metal layer, further lowering the resistivity.

The invention relates to the technical field of lithium ion batteries, in particular to a composite lithium-rich manganese-based positive electrode material and a preparation method and application thereof. The composite lithium-rich manganese-based positive electrode material is of a three-layer structure and sequentially comprises a lithium-rich manganese-based oxide positive electrode material matrix, a first coating layer and a second coating layer from inside to outside, the first coating layer is a mixture of halide solid electrolyte and lithium-containing oxide; and the second coating layer is an oxide solid electrolyte. The conductivity of a contact interface with a positive electrode material can be improved, the resistance is reduced, the moisture absorption degradation of halide is inhibited, the packaging difficulty is reduced, and the cycle performance of the halide-added solid electrolyte after moisture absorption is improved.

Provided according to exemplary embodiments is a lithium secondary battery comprising: a positive electrode containing a lithium iron phosphate; and an electrolyte containing a compound represented by chemical formula 1. The lithium secondary battery can have enhanced high-temperature cycle characteristics and low resistance characteristics. The lithium secondary battery can have enhanced high-temperature cycle characteristics and low resistance characteristics.

The invention discloses a household wall-mounted energy storage power supply, and belongs to the technical field of energy storage equipment, the household wall-mounted energy storage power supply comprises a hanging plate, a power supply body and an equipment box, the top of one side of the power supply body is fixedly provided with a hook, the hook is inserted into the hanging plate, the bottom of the power supply body is provided with a locking mechanism, and the locking mechanism is connected with the hanging plate. An electromagnet, a linkage mechanism, a connection mechanism, a slide rheostat, a monitoring mechanism, a buffer mechanism, a controller and a stop button are arranged in the equipment box, the electromagnet is connected with the power source body in series, the linkage mechanism comprises a sealing box, a piston plate, a sealing cylinder and an iron sheet, the iron sheet is embedded in the piston plate, and the piston plate is connected with the sealing cylinder. And a sealing disc is mounted in the sealing cylinder in a sliding manner. The transverse rod is linked with the slide rheostat to automatically adjust the resistance of the cooling fan, the resistance is reduced when the current is increased to improve the power of the fan, the dynamic matching of the cooling intensity is realized, and in addition, the system is additionally provided with multiple safety protection mechanisms.

Circuits and methods for increasing the long-term reliability and performance of phase change material (PCM) switches. To overcome the effects of electromigration damage of the resistive heater(s) of a PCM switch and of the PCM itself, and thus improve long-term performance and reliability, embodiments apply an AC control pulse of equal power to a conventional DC control pulse. An embodiment encompasses a PCM switch, including a PCM region including first and second signal ports configured to be coupled to a signal source; a resistive heater adjacent the PCM region and including first and second heater control signal ports; and a source of AC control pulses coupled to the first and second heater control signal ports, the AC control pulses having a first power profile to transform the PCM region into a low resistance state and a second power profile to transform the PCM region into a high resistance state.

Embodiments of the disclosure are directed to microelectromechanical system (MEMS) switches with a beam contact portion continuously extending between input and output terminal electrodes. In exemplary aspects disclosed herein, the movable beam includes a body and a contact with more conductivity and stiffness than the body. The contact continuously extends between and electrically couples the contact of the movable beam with the input and output terminal electrodes. Differing materials between the body and the contact allow for inclusion of the mechanical properties of the body (e.g., to reduce mechanical fatigue, creep, etc.) while utilizing the electrical properties of the contact (e.g., to reduce on-state electrical resistance). Accordingly, the MEMS switch provides low resistance loss during an on-state while maintaining high levels of isolation during an off-state.

The invention relates to the technical field of precision machinery manufacturing technology, and discloses a high-efficiency wafer test probe station, which comprises a base, the upper surface of the base is fixedly connected with a loading base and a motion control system, the output end of the motion control system is fixedly connected with a microscope, the upper surface of the loading base is fixedly connected with an objective table, and the objective table is fixedly connected with the output end of the motion control system. The interior of the base is in threaded connection with a synchronous adjusting mechanism and a support protection mechanism, the top of the synchronous adjusting mechanism is fixedly connected with a probe angle adjusting mechanism, and the upper surface of the probe angle adjusting mechanism is clamped with a probe seat, so that simultaneous adjustment of a plurality of probes can be realized, the test time is shortened, and the test efficiency is improved. Adjustment is carried out according to different wafer sizes to adapt to different test scenes; the angle of the probe is adjusted by adjusting the angle of the probe seat, so that the influence of resistance on a test signal is reduced in a low-resistance test.

The invention relates to a novel asymmetric groove SiC MOSFET device with low resistance and Miller capacitance, and belongs to the technical field of semiconductor devices. The device comprises a substrate; the drift region is formed on one surface of the substrate; the N-CSL is formed on the surface of the drift region; the low-barrier diode is formed on one side of the surface of the N-CSL; the second P-well is formed on the other side of the surface of the N-CSL; the trench gate and the auxiliary trench gate are formed on the surface of the low-barrier diode and located on the two sides of the low-barrier diode; the P-base is formed on the surface of the N-CSL and is positioned between the second P-well and the trench gate; the source N + region is formed on the surface of the P-base and is positioned between the second P-well and the trench gate; a source electrode formed on the top of the device; and the drain electrode is formed on the other surface of the substrate. The specific on-resistance of the device can be reduced, the Miller capacitance and the gate charge of the device are reduced, and the switching speed of the device is improved.

The invention provides a molybdenum-based oxide sintered body, a sputtering target material containing the sintered body, and an oxide thin film formed by the sputtering target material. In the present invention, a specific dopant is added to a molybdenum oxide and a niobium oxide that are difficult to sinter in a prescribed content range, and it is possible to simultaneously ensure improved sinterability, high density characteristics, and uniformity, low reflection, and low resistance characteristics of a thin film obtained by controlling particle growth even if pressureless sintering is performed.

The invention discloses multi-solvent synergistically activated low-temperature semi-sintered copper paste and a preparation method and application thereof, and belongs to the technical field of conductive paste. The multi-solvent synergistically activated low-temperature semi-sintered copper slurry comprises the following raw material components in percentage by mass: 82-88% of conductive filler, 2-3% of a resin carrier, 4-7% of an activating solvent, 4-7% of a dispersing solvent and 2-3% of a curing agent. Through cooperation of multiple solvents, full-stage activation of the copper particles is achieved, pre-connection and sintering of the copper particles before resin is completely crosslinked and cured are promoted, densification of the overall structure is improved, the insulation barrier effect of the resin is effectively avoided, the resistivity is reduced, meanwhile, inhibition of the resin on sintering of the copper particles is solved, and the service life of the copper particles is prolonged. And good balance between conductivity and interface adhesion is realized. Through resin curing, chemical bonding between the slurry and the substrate can be enhanced, a metal bond network among copper particles is expanded, and mechanical connection stability and electrical performance are guaranteed.

Provided is a semiconductor device that can be easily manufactured. This semiconductor device has a substrate, a transistor and element isolation layer formed on the substrate, first to fifth conductive layers, a first insulating layer, and first to fifth plugs. The transistor has a first low resistance region, a second low resistance region, and a portion of the first conductive layer. Each of a third conductive layer and a fourth conductive layer is a columnar body extending in a direction perpendicular to the substrate. The first low resistance region and the second conductive layer are connected via the first plug. The second low resistance region and the third conductive layer are connected via the second plug and the second plug. The fourth plug, the fifth plug, and the fourth conductive layer are connected to each other at positions overlapping the element isolation layer. The first insulating layer has a region in contact with a side surface and a top surface of the third conductive layer and the fourth conductive layer, and the fifth conductive layer extends in a direction approximately parallel to the first conductive layer in a planar view and has a region in contact with a side surface and a top surface of the first insulating layer.

The utility model relates to a composite heating type silicon carbide crystal growing furnace which comprises a furnace body, a heater assembly and a crucible, the heater assembly and the crucible are arranged in an inner cavity of the furnace body, the crucible is located in the heater assembly, a heat preservation layer is arranged between the furnace body and the heater assembly, and the heater assembly is fixed to the furnace body through an electrode. A crucible is arranged in the furnace body, a seed crystal disc is fixedly mounted on the crucible, seed crystals are adhered to the inner side of the seed crystal disc, raw materials are stored in the crucible, the heater assembly comprises an upper resistance heater and a lower resistance heater, and the upper resistance heater is located on the side, close to a top plate of the furnace body, of the lower resistance heater. The upper resistance heater and the lower resistance heater are used as heat sources, the heating area is increased, the melting speed of silicon materials in the crucible is increased, the axial temperature gradient is more easily formed in the furnace body, and large-size crystals are formed.

A semiconductor device that includes a substrate, a crystalline bottom electrode layer on an upper side of the semiconductor substrate, a conductive crystalline metal layer above the crystalline bottom electrode layer, and a conductive oxide layer above the conductive crystalline metal layer. The conductive oxide layer has a low resistance. The semiconductor device also includes a magnetic tunnel junction (MTJ) above the conductive crystalline metal layer, the MTJ including a tunnel barrier layer, a free layer on a first side of the tunnel barrier layer and a reference layer on a second side of the tunnel barrier layer opposite the first side.

The invention relates to the technical field of crystal material preparation, in particular to a layered selenide Ge3Sb2Se5 semiconductor material and a preparation method thereof. The preparation method of the layered selenide Ge3Sb2Se5 semiconductor material comprises the following steps: grinding a Ge3Sb4Se7 material, putting the ground Ge3Sb4Se7 material into a quartz tube, adding iodine particles, performing vacuum packaging in the quartz tube, putting one end, with raw materials, of the quartz tube into a high-temperature region, and putting one end, without raw materials, of the quartz tube into a low-temperature region; raising the temperature to 400 + / -25 DEG C at the low-temperature region end and 500 + / -25 DEG C at the high-temperature region end, preserving heat for 7 days, and naturally cooling to room temperature to obtain the Ge3Sb2Se5 semiconductor material. The crystal structure of the Ge3Sb2Se5 semiconductor material belongs to an orthorhombic system, and the Ge3Sb2Se5 semiconductor material has the characteristics of low thermal conductivity and low resistivity. According to the preparation method disclosed by the invention, the Ge3Sb2Se5 semiconductor material can be stably prepared, and a material is provided for physical property research of the Ge3Sb2Se5 semiconductor material and preparation of semiconductor photoelectric devices and the like.

Embodiments of the present disclosure provide integrated circuit chips including via towers formed with stacks of conductive layers formed during fabrication of semiconductor devices and interconnect structures of the integrated circuit chips. The via towers may be connected to provide electrical power to subsequently stacked integrated circuit chips. The via towers according to the present disclosure reduce cost of fabrication because the via towers are fabricated without additional processing sequences. The via towers may be integrated in the circuit layout to form a low resistance power rail, therefore, improving performance.