18963 results about "Chip" patented technology

The invention relates to the field of chip verification, and provides a chip verification method, device and equipment, a medium and a chip. The method comprises the following steps: establishing a dynamic simulation verification environment of a to-be-verified design, and generating a plurality of test scenes and corresponding test excitation according to a design specification definition; sending the test excitation to a driver through a sequencer, converting the test excitation into a signal conforming to a to-be-verified design interface protocol by the driver, and transmitting the signal to the to-be-verified design; the monitor collects an input signal and an output signal of a to-be-verified design in real time, converts the input signal and the output signal into transactions, and transmits the transactions to the scoreboard; comparing the reference model with an output signal of the to-be-verified design to generate a dynamic simulation verification result; according to the dynamic simulation result, the state space is reduced, state space traversal is carried out on a design part which is not covered by dynamic simulation in the design to be verified, and a formal verification analysis result is generated; and evaluating the to-be-verified design according to the formal verification analysis result.

The invention relates to a water quality real-time detection system which comprises the following modules: a multi-source sensing module which is based on a multi-parameter sensing array, adopts a self-adaptive sampling strategy, realizes sensor time sequence synchronization through a state estimation algorithm, completes water body multi-dimensional parameter acquisition in combination with a micro-fluidic chip, generates a multi-modal sensing data set, and transmits the multi-modal sensing data set to a data processing module; the multi-source sensing module comprises a multi-source sensing sub-module, a signal conditioning sub-module, a time sequence synchronization sub-module and an anomaly capture sub-module. The method has the advantages that through the synergistic effect of the adaptive sampling strategy and the state estimation algorithm, the multi-sensor time sequence synchronization precision is remarkably improved, the phase deviation problem caused by traditional fixed frequency sampling is effectively eliminated, the sliding window polynomial fitting is combined with the wavelet threshold de-noising technology, and the multi-sensor time sequence synchronization precision is improved. High-frequency noise interference is greatly suppressed on the premise that effective components of the signals are reserved, and meanwhile, the abnormal value detection accuracy is improved through a dynamic threshold mechanism.

The invention provides a power chip packaging detection method and device, and the method comprises the steps: obtaining a structure image, an infrared thermal imaging frame sequence and a working electrical parameter data set of a target power chip after packaging, and carrying out the layering and regional peak analysis, so as to construct a morphology feature parameter set and a thermal anomaly feature set; inputting the morphology feature parameter set, the thermal anomaly feature set and the working electrical parameter data set into a preset defect identification model to obtain a chip packaging anomaly identification map; and performing hierarchical division and node aggregation on the chip packaging abnormity identification map to obtain a packaging defect type result. By constructing a multi-modal packaging detection system taking a structural image, an infrared thermal imaging frame sequence and a working electrical parameter data set as input, accurate identification of the power chip is realized, the accuracy of packaging defect detection is effectively improved, and the problems of low identification precision and information isolation of an existing detection method are improved.

The invention relates to the technical field of artificial intelligence, can be applied to service scenes of pension service, financial science and technology, medical health and the like, and discloses a multi-level heterogeneous integrated chip task processing method, device, equipment and medium, and the method comprises the steps: constructing a multi-level heterogeneous integrated chip composed of a perception processing layer, an intelligent decision-making layer and a driving control layer, the layers are connected through a vertical interconnection structure; receiving multi-modal task data and extracting features to generate feature vectors; inputting the feature vector into a neuromorphic processing unit to determine a task decision result; converting the decision result into a driving signal to control an execution device; adjusting synaptic weights based on the feedback signal; and monitoring chip operation state parameters and dynamically adjusting processing frequency and structure parameters. By integrating multi-modal sensing, neuromorphic decision and a dynamic feedback mechanism, data sensing, decision and execution processing are completed in a chip, and the real-time performance and the calculation efficiency are improved by combining operation state monitoring and adjusting frequency and structure.

The invention discloses a dynamic flow control method for a two-phase cold plate liquid cooling system based on multi-modal sensing, and relates to the technical field of equipment cooling. Comprising the following steps: S1, collecting liquid cooling monitoring data in real time, and performing data preprocessing; s2, judging the state risk of the cold plate, carrying out signal cross validation, and taking an abnormal regulation and control measure; s3, cooling liquid flow regulation and control are carried out, and the matching degree of flow regulation and control and chip thermal load is evaluated, so that flow regulation and control correction is carried out; and S4, constructing a big data modeling and simulation feedback platform, evaluating a flow regulation and control self-healing effect, optimizing each parameter and strategy, and carrying out self-learning evolution. The problems that an existing two-phase cold plate liquid cooling system generally only depends on a single temperature signal, lacks a multi-source redundancy check mechanism, has the problems of response lag, weak local reflection capacity, high risk during failure and the like, consequently, the cooling capacity distribution and adjustment precision is insufficient, and the actual requirement of a high-heat-density data center for heat dissipation is difficult to meet are solved.

The invention relates to a stacking packaging method and system for AI-DSP mixed audio processing chips, and the method comprises the following steps: employing a first bonding machine to carry out the flip-chip bonding of an AI chip and a DSP chip, and obtaining a flip-chip bonding chip; the flip-chip bonding chips are interconnected, and an interconnected chip structure is obtained; vertically stacking the interconnected chip structures to obtain a stacked chip structure; packaging the stacked chip structure by adopting a second bonding machine to obtain a packaging body; according to the AI-DSP mixed audio processing chip and the packaging method thereof, the packaging body is subjected to heat dissipation treatment through the preset heat dissipation substrate, the packaged AI-DSP mixed audio processing chip is obtained, and the technical problems that in a traditional packaging scheme, an AI chip and a DSP chip generally adopt different process nodes and manufacturing processes, and thermal expansion coefficients are not matched and stress distribution is uneven during direct integration are solved.

The invention relates to the technical field of integrated circuits and computer networks, and particularly discloses a transmission control and intelligent scheduling system for an integrated chip, and the system sets a dual-mode decision and dynamic switching mechanism for each routing node. Calculating dynamic characteristic parameters including an instantaneous value, a first-order trend and a second-order acceleration; when the parameter is matched with a pre-stored abnormal feature set and the load exceeds a threshold value, the node is immediately atomized and switched to a predefined security scheduling strategy loaded from a shared storage area, and otherwise, the node generates a scheduling decision according to self-adaptive decision logic continuously optimized based on historical performance feedback; all the nodes carry out data packet forwarding control according to the current execution strategy; and the system also periodically realizes federated global knowledge evolution according to the quality evaluation result of the self-adaptive decision of each node.

The invention discloses a power grid material sampling inspection management method for realizing whole-course tracing based on intelligent sample sealing, and relates to the technical field of electric power material management and intelligent perception, and the method comprises the following steps: S1, an initialization stage: executing a sample sealing coding segmentation pre-configuration process, distributing independent numbered segments to each sample sealing terminal, and the central control module synchronizes the use state of the terminal code to realize distributed isolation of code generation. According to the invention, coding uniqueness is realized through segmented pre-configuration and global duplicate checking, identity information security is guaranteed by adopting chip one-time write protection and tamper-proof technologies, and sample packet switching and data counterfeiting are effectively prevented by combining automatic acquisition and multi-round consistency comparison. Abnormal recognition and closed-loop processing ensure that abnormal events are frozen in time and responsibility is traced, and irregular samples are prevented from flowing into subsequent links. The whole-process auditing and dynamic optimization enable the management process to be self-perfected, and the intelligence, standardization and reliability of sampling inspection of the power grid materials are remarkably improved.

The invention discloses a high-voltage circuit for an electric flame stove. The high-voltage circuit comprises a PFC circuit, a high-frequency conversion circuit, a boosting transformer, an energy coupling circuit and a voltage doubling circuit which are electrically connected in sequence. According to the EMI filter circuit, common-mode interference and differential-mode interference are filtered out, and pure alternating current input is provided for a back-end PFC circuit; two chips are adopted in the PFC circuit, so that the PFC circuit 300 finally realizes the consistency of the current waveform and the voltage phase; in the other embodiment of the invention, double chips are adopted, so that'fault linkage protection 'is realized; stable discharging of multiple groups of positive and negative electrodes is achieved through multiple groups of single energy coupling capacitors and independent voltage doubling rectifier bridges which are connected in parallel.

The invention relates to the technical field of resistor chips, in particular to a method and a system for optimizing a manufacturing process of a thermistor chip. According to the method, multi-scale process entropy analysis is carried out on a process parameter dynamic flow, the coupling strength between key processes is analyzed, and a process parameter cluster with strong non-monotonic correlation and a process system entropy increase path of the process parameter cluster are identified, so that a collaborative stability domain boundary model is constructed; according to transient fluctuation characteristics extracted from a process parameter dynamic flow obtained in real time, in combination with the collaborative stability domain boundary model, determining a parameter subset exceeding a collaborative stability operation interval as a drift parameter cluster, executing an optimization instruction set to perform trial production, synchronously collecting collaborative trajectory data of a process parameter cluster, and performing collaborative trajectory prediction; and the collaborative stability is verified by calculating the entropy change rate of the process system and is fed back to the collaborative stability domain boundary model for boundary toughness strengthening, dynamic collaborative convergence of relevant parameters such as the sintering gradient and the electrode pressure is achieved, and the product consistency and the yield stability are improved.

The invention provides an engineering test method and system for a storage chip and a medium, and belongs to the technical field of semiconductor packaging. The method comprises the following steps: acquiring read-write operation data, temperature data and voltage data of a storage chip in real time through a distributed sensor network, performing dimension reduction and segmentation processing on test data by using a multi-dimensional feature extraction algorithm, extracting statistical features and correlation features, inputting a fault prediction model constructed based on a deep learning algorithm, and performing fault prediction. Fault type and probability prediction is realized; and judging whether the chip has a fault by combining a preset threshold value, if the chip has the fault, accurately positioning a fault area by adopting a dynamic probe test technology, determining a fault time point and a trigger condition through time sequence analysis, and finally generating a fault diagnosis report and providing a repair suggestion. According to the invention, the accuracy and efficiency of fault detection of the storage chip can be effectively improved.

The invention relates to the technical field of Bluetooth communication, and discloses an optimization method for secure communication of Bluetooth chip equipment. The method comprises the following steps: identifying a device type identifier and a protocol version feature, extracting a hardware capability parameter and generating an initial security policy set; collecting channel data, and calculating a stability index and a dynamic noise baseline; then, screening and sorting security policies to generate an execution queue, adjusting an encryption strength threshold according to a noise baseline to perform iterative optimization, and outputting final policy configuration; and when the target Bluetooth chip establishes the communication connection, loading the final security policy configuration and monitoring the channel state in real time, and triggering a policy dynamic switching mechanism when the channel state change exceeds the preset tolerance so as to optimize the security communication effect of the Bluetooth chip equipment. According to the method, the security policy can be accurately matched with the device and the channel state, the policy is dynamically adjusted, and the security and the stability of communication of the Bluetooth chip device are effectively improved.

The embodiment of the invention provides a data tracking circuit, a data tracking processing method, a chip and electronic equipment, the data tracking circuit comprises a selection module and a packaging engine module, tracking source data is received and selected to be output as tracking data through the selection module, the packaging engine module packages the tracking data to generate corresponding data frames, and the corresponding data frames are stored in the storage module. The data frames comprise the identifiers used for identifying the types of the data frames, the larger the number of the data frames of the same type is, the shorter the data bit width of the identifiers of the data frames of the type is, compared with identifiers of fixed lengths, the lengths of most identifiers can be shortened, the data size of the data frames is reduced on the whole, and the data transmission efficiency is improved. And thus, the bandwidth required by the packaged data frame is also reduced.

The embodiment of the invention discloses a chip verification environment generation method and system, electronic equipment and a storage medium, relates to the technical field of integrated circuit verification, can adapt to verification environments with different configurations, and improves verification efficiency. The method comprises the following steps: constructing or calling a verification environment template; analyzing the initial configuration information and the routing topology information, and generating a target configuration file according to an interface protocol and an interconnection rule of a register transfer level and a model; the routing topology information indicates an interconnection link topology structure between the devices, and the target configuration file indicates a component type corresponding to each device required by simulation forming of each interconnection link and a matched verification component type; loading and instantiating the register transfer level component and the model component based on the verification environment template according to the component type; and according to the verification component type, interconnection is carried out between the register transfer level component and the model component through the verification component, and a chip executable verification environment is generated. The method and the device are suitable for a scene for constructing a chip verification environment.

The invention provides a DFT test task management method and device, electronic equipment and a storage medium, and belongs to the technical field of chip design verifier.The DFT test task management method comprises the steps that a data model is constructed on the basis of a design module list and a test step list, the data model is used for indicating testability design DFT test steps of all design modules, and the test steps of all the design modules are stored in the test step list; the data model comprises a plurality of DFT test tasks, attributes of each DFT test task comprise a selection state, and the selection state comprises a selected state and a non-selected state; based on the interactive input, determining at least one DFT test task of which the selection state is selected as an executable DFT regression object; and according to the DFT regression object, driving a DFT test task to be executed. According to the method, the DFT test tasks are normalized through the data model, only the DFT test tasks need to be selected for making the test plan, efficient management of the DFT test tasks is achieved, and the regression test efficiency is improved.

The invention relates to the technical field of chip design, and discloses a chip dynamic power consumption scheduling method and system based on an intelligent algorithm. The method comprises the following steps of: firstly, acquiring instruction stream data operated by a chip in real time, extracting a feature vector comprising an instruction dynamic change vector and context associated data, and determining a power consumption prediction mapping parameter according to the feature vector; and when the parameter exceeds a preset threshold value, an accurate power consumption prediction result is generated by adjusting the weight of the convolutional neural network. Subsequently, a synchronous timing demand is calculated based on the instruction switching frequency and the data dependency, and an initial power supply configuration is determined. By monitoring task load classification signals, the power consumption distribution proportion is adjusted when the signals are lower than a threshold value, the optimized power supply configuration is obtained, and the improvement index of the resource distribution efficiency is calculated according to the optimized power supply configuration. And finally, according to the index, dynamically adjusting a limiting condition of a scheduling period, and forming a self-adaptive optimization framework, thereby realizing accurate prediction and dynamic optimization scheduling of the chip power consumption.

An adaptive modular multimodal communication and computing panel includes a multilayer stack with a protective layer transmissive in selected bands, a reconfigurable communication layer operable in phased array, reflectarray, hybrid phased reflector, free space optical, or quantum modes, and electronics with heterogeneous processors. A multi scale interconnect and input and output fabric couples electrical, radio frequency, guided optical, and free space optical domains through interfaces including electro optic transduction and RF or baseband conversion. The fabric may implement programmable true time delay, resonators, and comb referenced timing. A management system coordinates beamforming, sensing, routing, calibration, workload placement, and security. Panels tessellate and connect by electrical, radio frequency, and fiber optic interfaces, supporting hot swappable modules, blind mate connectors, robotic servicing, and anti tamper features. Power and thermal subsystems harvest, store, regulate, and dissipate energy. The architecture scales from chip level modules to vehicle, airborne, maritime, orbital, and deployable systems.

The invention discloses a clock optimization method, device and equipment and a computer readable storage medium, which are applied to the field of integrated circuits, and comprise the following steps: reading a netlist of each fragment, and traversing each netlist to generate an instance tree corresponding to each fragment; performing reverse tracing and forward tracing on each clock signal based on each instance tree to obtain a clock network path corresponding to each clock signal; determining a redundant clock according to each clock network path, and performing corresponding processing on the redundant clock; the redundant clock comprises an isolated redundant clock and an equivalent redundant clock. According to the method, the instance tree is generated by traversing the netlist, and the complete clock network path is obtained by combining reverse tracing and forward tracing, so that isolated redundant clocks and equivalent redundant clocks can be comprehensively captured, and automatic tracking of the clock network path and accurate identification of the redundant clocks are realized; the redundant clock is correspondingly processed, so that unnecessary clock generation logic and wiring resource occupation can be reduced, the chip power consumption and the area overhead are reduced, and the resource utilization rate is improved.

The invention relates to the technical field of direct current motor servo drive control, and provides a Zynq AXI4 bus-based real-time transmission system and a control method thereof, and the system comprises a Zynq system on chip, a DDR3 common data area, an AXI4 bus interconnection architecture and a dynamic partition manager. By implementing the scheme, firstly, the multi-channel characteristic of the AXI4 bus is utilized, special transmission channels are distributed for different types of data, and parallel data interaction is realized; secondly, a dynamic partition manager is deployed at a PL end, a DDR3 public data area is dynamically divided into a plurality of partitions in real time according to needs, multi-task parallel is achieved, and the real-time performance of the system is improved; thirdly, the read-write operation on the DDR3 in each control period is split into a plurality of state machines through precise scheduling of the state machines, the state machines are combined into a state loop to be mounted to an AXI4 bus, it is ensured that key tasks are completed on time, and the certainty of the system is improved; fourthly, the size and the number of partitions in the DDR3 are dynamically adjusted through a dynamic partition manager, and the storage efficiency is improved.

The invention relates to the technical field of chip test engineering control, in particular to an active temperature control method and system for a chip aging tester, and the method comprises the steps: analyzing a test process according to test task parameters, and evaluating the expected thermal load change rate of a test chip, so as to dynamically generate a chip target junction temperature control curve; based on the chip target junction temperature control curve, the actual chip junction temperature and the current actual furnace temperature, the theoretical furnace temperature is obtained through a junction temperature closed-loop control algorithm, the furnace temperature compensation amount is calculated through a feedforward compensation algorithm in combination with the test state parameters, and the ideal furnace temperature is obtained according to the theoretical furnace temperature and the furnace temperature compensation amount; the actual temperature control quantity is obtained according to the basic temperature adjusting quantity and the temperature control compensation quantity, a preset chip target junction temperature control curve can be tracked more accurately, transient and steady state errors caused by test program switching and environment fluctuation can be more effectively restrained, and control over the chip junction temperature with higher precision and faster response is achieved.

The invention relates to the technical field of embedded data storage, and discloses a method and a system for prolonging the service life of a FLASH simulation EEPROM (Electrically Erasable Programmable Read-Only Memory) in a single chip microcomputer, and the method comprises the following steps: firstly, initializing the FLASH, dividing the FLASH into a main data area, a mapping table area, a backup area and a transaction log area, selecting a physical block through a dynamic wear leveling algorithm when data is written, and writing the data into a database; the method comprises the following steps of: starting a backup area or a transaction log area, safely updating a mapping table by using a transaction mechanism, performing cyclic redundancy check when reading data, if the cyclic redundancy check fails, starting cascade recovery from the backup area or the transaction log area, and finally, updating a transaction log to record operation so as to form a closed-loop management process. According to the invention, through a set of dynamic wear leveling and data classification management mechanism, global and uniform distribution of the write load in the storage array is realized, the physical block with the least erasing times is selected during writing, the access frequency of the data can be identified, and cold data which is not changed frequently can be actively migrated.

The invention discloses an air-sea cross-domain network slice configuration and response method based on a CTC8180 chip, and belongs to the technical field of air-sea cross-domain communication and network slicing, and the method comprises the steps: S1, configuring and parallelly accessing NETCONF and CLI paths, and converting a configuration instruction into a CTC8180 chip call instruction; s2, creating a resource pool, a logic port, a binding interface and a VRF strategy based on a FlexE technology; s3, finishing forwarding and mapping configuration of a slicing strategy by combining SRv6 path programming, service level mapping and gport identification slice identification; s4, performance monitoring, data acquisition and fault detection are carried out through three protocols; s5, closed-loop control is formed through resource dynamic adjustment, path switching, strategy linkage and the like; and S6, multi-chip compatibility and stable adaptive deployment are realized through the steps of integrating S1 to S5. The invention provides a specific implementation method for constructing logic network slicing capability on high-performance forwarding hardware for air-sea cross-domain specific requirements, and provides reliable communication guarantee for high-dynamic heterogeneous services.

The invention discloses a horizontal five-axis turning and milling composite center with a self-adaptive matching system. The horizontal five-axis turning and milling composite center comprises a tool turret, a boring tool mechanism, a tool changing area and a control system. A radio frequency identification reading device is arranged in a tool changing area of the tool turret and the boring tool mechanism, and an RFID chip tag is attached to the outer surface of each tool and used for storing tool serial numbers, specifications and length compensation parameters. And the control system realizes self-adaptive matching and sequential error correction of the cutter and the working procedure through radio frequency identification. The tool changing area is provided with a visual monitoring assembly which comprises a plurality of sets of industrial cameras, an adjustable light source and a structured light stripe illumination module and is used for detecting the clamping posture, the abrasion state and the type of a tool. The system has self-learning and digital twinning simulation functions, and can simulate the motion trail of the cutter and predict the interference risk before the cutter is changed. According to the method, integrated control over automatic tool recognition, posture correction, abrasion detection and path prediction is achieved, and the tool changing precision, the operation stability and the automation level of the horizontal five-axis turning and milling composite center are remarkably improved.

The invention discloses a method and system for testing a direct-current offset compensation circuit of an optical transceiving driving chip and a medium, and relates to the technical field of photoelectric integrated circuit testing, and the method comprises the following steps: carrying out the time alignment of a test waveform and an offset track of the optical transceiving driving chip, extracting the phase dislocation amount and the amplitude kick amount between beats, and carrying out the calculation of the phase offset amount and the amplitude kick amount; a continuous change result is mapped into a time sequence conflict observation band which is used for identifying a beat overlapping region; and on the basis of the phase dislocation trend of the time sequence conflict observation band, determining a beat overlapping point of the direct current offset compensation loop, and generating an overlapping beat index according to the duration of amplitude kick and the polarity direction for identifying an interference node. According to the method, millisecond-level beat observation and microsecond-level overlapping identification are realized in a test stage, interference nodes are accurately extracted, a coupling strength graph is constructed, and by combining beat rearrangement and an energy unloading strategy, nonlinear oscillation is inhibited, oscillation and overload risks are reduced, eye pattern quality and error code stability are improved, and chip test precision and robustness are enhanced.

The invention relates to the technical field of signal analysis, in particular to a GNSS (Global Navigation Satellite System) detection method and system based on machine learning, and the method comprises the steps: receiving a navigation radio-frequency signal containing reality and deception, and carrying out the down-conversion of an RF (Radio Frequency) front end to obtain intermediate-frequency data; gNSS signal capture is completed by searching correlation peaks in frequency and code phases based on intermediate frequency data; in the capturing stage, a motion state, a correlation peak number, a noise value, capturing parameters and peak + / -1 chip sampling features are extracted and input into a machine learning classification model to judge whether cheating exists or not; if so, separating the deception signal from the real signal, and respectively sending the deception signal and the real signal into independent tracking channels; measuring an array element carrier relative phase by an array antenna, establishing a phase center model, and correcting to obtain an effective phase center and a differential baseline; according to the method, a deception azimuth angle and a pitch angle are obtained, a beam weight is calculated, a deception direction is subjected to null setting, a real direction is subjected to main lobe protection, and a weight value is fed back in real time to improve a signal carrier-to-noise ratio and locking stability. According to the invention, the problem that the existing commercial GNSS signal is low in power and easy to be interfered by deception is solved.

The invention relates to the field of chip testing, in particular to a chip signal integrity test analysis method, device and equipment and a storage medium. The method comprises the following steps: extracting a chip performance index based on a chip design requirement document; performing saturation frequency excitation setting based on the chip performance index to generate an excitation test signal; performing a multi-port signal excitation test and parallel signal sampling based on the excitation test signal to generate a high signal-to-noise ratio response data set; obtaining a chip layout design file; performing chip communication link analysis on the chip layout design file, and constructing communication line layout data; performing signal mapping and waveform quality evaluation on the communication line layout data based on the high signal-to-noise ratio response data set to obtain a node signal distortion rate; and performing signal integrity quantization and theoretical signal integrity score comparison based on the node signal distortion rate, and marking a fault node. According to the invention, the chip testing efficiency is improved, and the signal abnormal part of the chip is accurately and efficiently detected.

The invention provides a chip security key protection method and system capable of resisting side channel attack, and relates to the technical field of chips, which comprises the following steps of: obtaining a key operation request, performing address space mapping based on a dynamic mapping rule to obtain encrypted key data, decrypting the encrypted key data, fragmenting key intermediate data, and allocating an independent processing channel to perform decoupling operation; and injecting a time-varying noise signal to cover the association between the key and the physical characteristics, and finally performing recombination and reverse conversion to generate a final key output. According to the method, side channel attacks such as power consumption analysis and electromagnetic analysis are effectively resisted, and the security of key storage and operation processes is improved.

The invention provides a chip test calibration device and method, and relates to the technical field of chip test. The chip test calibration device comprises a base, a cooling air supply device, a control device, a chip and two groups of manipulators. According to the invention, the chip is heated by setting different temperature environments in stages, and the multi-point synchronous temperature measurement of each temperature stage is combined, so that the heat distribution on the surface of the chip can be comprehensively captured, and the calibration error caused by non-uniform temperature or a detection blind area is avoided; the chip is automatically circulated among the heating station, the detection station and the cooling station, synchronous processing and continuous detection of multiple chips are achieved, the single-batch detection period is greatly shortened, the surface of the chip is directly blown by directional airflow, an efficient air return channel is matched, the temperature of the chip can be rapidly reduced after detection is completed, idle waiting for station switching is reduced, and the overall production efficiency is improved.

The invention discloses a rapid exchange chip resetting method and system, and belongs to the technical field of chips. The method comprises the steps of abnormal trigger type identification, reset granularity dynamic determination, operation state freezing, hierarchical reset execution, reset validity verification and redundant reset system reconstruction, rapid abnormal positioning is achieved through hardware monitoring and feature matching, a dynamic reset strategy generation mechanism is combined, the reset granularity is accurately controlled according to the abnormal severity degree, and the system reliability is improved. Excessive reset or insufficient reset is avoided, the system resource utilization rate and the fault processing efficiency are improved, a state freezing technology is operated to maintain the state of a key register, progressive pulse injection and priority control of hierarchical reset execution are matched, it is ensured that a key module is preferentially recovered, the energy consumption is reduced while the reset effect is ensured, and the system performance is improved. Reset effectiveness multi-dimensional verification is combined with redundancy reset and a system reconstruction mechanism, a standby repair scheme is dynamically triggered for different fault types, and the reliability, fault-tolerant capability and maintainability of the system are improved.

The invention provides a chip verification method and device, equipment, a medium and a program product, and the method comprises the steps: receiving a first operation instruction of a to-be-verified module and a second operation instruction of a reference model in parallel, the reference model being a function model used for simulating the expected behavior of the to-be-verified module; searching a first instruction record matched with the first operation instruction from a request queue of the reference model, and searching a second instruction record matched with the second operation instruction from a request queue of the to-be-verified module; and determining a verification result of the to-be-verified module according to a comparison result of the first operation instruction and the first instruction record and / or a comparison result of the second operation instruction and the second instruction record. According to the invention, a structured and reusable universal chip verification method is realized, so that a tedious customized scoreboard design is replaced, and the efficiency and accuracy of verification work are greatly improved.