21813 results about "Chip" patented technology

The present invention relates to an apparatus comprising a substrate having at least one assay station. The at least one assay station has at least a first assay station channel and at least a second assay station channel and the first and second assay station channels each separately being in communication with the at least one assay station. The apparatus has an arrangement of at least first and second multipurpose channels in communication with the first and second assay station channels, respectively. The first multipurpose channel and first assay station channel have internal surface characteristics conducive to conduction of a sample solution therethrough. There is at least one sample fluid inlet in communication with the at least first multipurpose channel, and at least one isolation-medium inlet in communication with the at least first and second multipurpose channels. The at least one second multipurpose channel has an internal surface portion non-conducive to conduction of said sample solution.

A high-speed ring topology. In one embodiment, two base chip types are required: a "drawing" chip, LoopDraw, and an "interface" chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).

A method of producing a reconfigurable circuit device for running a computer program of moderate complexity such as multimedia processing. Code for the application is compiled into Control Flow Graphs representing distinct parts of the application to be run. From those Control Flow Graphs are extracted basic blocks. The basic blocks are converted to Data Flow Graphs by a compiler utility. From two or more Data Flow Graphs, a largest common subgraph is determined. The largest common subgraph is ASAP scheduled and substituted back into the Data Flow Graphs which also have been scheduled. The separate Data Flow Graphs containing the scheduled largest common subgraph are converted to data paths that are then combined to form code for operating the application. The largest common subgraph is effected in hardware that is shared among the parts of the application from which the Data Flow Graphs were developed. Scheduling of the overall code is effected for sequencing, providing fastest run times and the code is implemented in hardware by partitioning and placement of processing elements on a chip and design of the connective fabric for the design elements.

A structure and a method for forming the same. The structure includes a substrate, a first interposer on the substrate, a second interposer on the substrate, and a first bridge. The first and second interposers are electrically connected to the substrate. The first bridge is electrically connected to the first and second interposers.

A radio-frequency integrated circuit chip package has at least one integrated antenna. The package includes at least one generally planar ground plane formed with at least one slot therein. A first substrate structure has an outer surface and an inner surface. The at least one generally planar ground plane is formed on the outer surface of the first substrate structure. At least one feed line is spaced inwardly from the ground plane and parallel thereto. The at least one feed line has an inner surface and an outer surface and is a transmission line formed on the inner surface of the first substrate structure with the outer surface of the at least one feed line adjacent the inner surface of the first substrate structure. At least one radio frequency chip is coupled to the feed line and the ground plane. A second substrate structure, spaced inwardly from the feed line, defines a chip-receiving cavity. The chip is located in the chip-receiving cavity. The inner surface of the at least one feed line borders the chip-receiving cavity. An antenna patch may be provided. Planar phased array embodiments, assemblies with motherboards and heat sinks, and fabrication techniques are also disclosed.

The Field Programmable Instrument Controller (FPIC) is a stand-alone low to high performance, clocked or unclocked multi-processor that operates as a microcontroller with versatile interface and operating options. The FPIC can also be used as a concurrent processor for a microcontroller or other processor. A tightly coupled Multiple Chip Module design incorporates non-volatile memories, a large field programmable gate array (FPGA), field programmable high precision analog to digital converters, field programmable digital to analog signal generators, and multiple ports of external mass data storage and control processors. The FPIC has an inherently open architecture with in-situ reprogrammability and state preservation capability for discontinuous operations. It is designed to operate in multiple roles, including but not limited to, a high speed parallel digital signal processing; co-processor for precision control feedback during analog or hybrid computing; high speed monitoring for condition based maintenance; and distributed real time process control. The FPIC is characterized by low power with small size and weight.

The present invention relates to inter-chip electrostatic discharge (ESD) protection structures for high speed, and high frequency devices that contain one or more direct, inter-chip signal transmission paths. Specifically, the present invention relates to a structure that contains: (1) a first chip including a first circuit, (2) a second chip including a second circuit, (3) an intermediate insulator layer located between the first and second chips, wherein the first and second circuits form a signal transmission path for transmitting signals through the intermediate insulator layer. An electrostatic discharge (ESD) protection path is provided in the structure between the first and the second chip through the intermediate insulator layer, to protect the signal transmission path from ESD damages.

Techniques and instrumentalities to improve ISI and ICI cancellation in reception of modulated symbols by selectively decoding subsymbols of such modulated symbol before they can be completely decided or perceived as well as use of decoded symbol/subsymbol information in the feedback equalization process are disclosed. In particular, a decoder and corresponding method are disclosed which includes a feedback equalizer capable of receiving a modulated signal including a symbol defined by a first number of chips, along with a subsymbol processor to generate a subsymbol waveform upon receipt of a second number, less than the first number, of chips of such symbol and provide the subsymbol waveform to the feedback equalizer in order to equalize the modulated signal using the subsymbol waveform. Other disclosed aspects including techniques and instrumentalities for improving reception performance when symbols encoded by different modulation schemes are encountered, as well as feedback equalization for Barker encoded symbols present in the received signal.

A Dynamic Digital Pre-Distortion (DDPD) system is disclosed to rapidly correct power amplifier (PA) non-linearity and memory effects. To perform pre-distortion, a DDPD engine predistorts an input signal in order to cancel PA nonlinearities as the signal is amplified by the PA. The DDPD engine is implemented as a composite of one linear filter and N-1 high order term linear filters. The bank of linear filters have programmable complex coefficients. To compute the coefficients, samples from the transmit path and a feedback path are captured, and covariance matrices A and B are computed using optimized hardware. After the covariance matrices are computed, Gaussian elimination processing may be employed to compute the coefficients. Mathematical and hardware optimizations may be employed to simplify and reduce the number of multiplication operands and other operations, which can enable the DDPD system to fit within a single chip.

An electronic circuit (200) for use with an accessing circuit (110) that supplies a given address and a partial write data portion and also has dummy cycles. The electronic circuit (200) includes a memory circuit (230) accessible at addresses, an address buffer (410), a data buffer (440) coupled to the memory circuit (230), and a control circuit (246) operable in the dummy cycles to read data from the memory circuit (230) to the data buffer (440) from a next address location in the memory circuit (230) and to store that next address in the address buffer (410). The electronic circuit further includes a multiplexer (430), a comparing circuit (420) responsive to the given address and a stored address in the address buffer (410), to operate the multiplexer (430) to pass data from the data buffer (440) or to pass data from the memory circuit (230) instead; and a mixer circuit (450) operable to put the partial write data portion into the data taken from the selected one of the data buffer (440) or memory circuit (230). Other circuits, devices, systems, processes of operation and processes of manufacture are also disclosed.

A method for determining wagers by applying a chip denomination representation, having at least one angle associated with at least one color transition, against a working chip template. A related system includes, but is not limited to, circuitry and/or programming for effecting the foregoing-referenced method; the circuitry and/or programming can be virtually any combination of hardware, software, and/or firmware configured to effect the foregoing-referenced method embodiments depending upon the design choices of the system designer.

A highly integrated terrestrial and cable tuner for receiving digital and analog television signals is disclosed. It achieves high performances in sensitivity, image rejection, dynamic range, channel selectivity and power consumption. A major-images rejection converter disclosed rejects third- and fifth-order images. Thus it significantly relaxes RF filter design in a tuner of a single-stage or a first-stage zero-IF/low-IF downconversion architecture. Different architectures and frequency planning are disclosed in accordance with specifications of TV standards to improve the overall performance of the tuner with a different or configurable IF output. The tuner is integrated by using standard processes, with minimal off-chip components excluding SAW and LC filters. Small tuner modules cost less than discrete (can) tuners. They can be used in digital/analog TV sets and portable and handheld TV devices and for mobile-phone TV reception.

The invention provides a chip of a consumable container, which comprises a storage module, a control module, an interface module and a data safety module. The storage module is used for storing initial data, printing data, control data and key data; the interface module is used for realizing data communication between the storage module and the control module; the data safety module is respectively connected with the interface module and the control module, and is used for identifying a type and a content of data communicated between a printer and the chip, encrypting matched data in a selected safe mode and decrypting the data; the control module is connected with the storage module and is used for controlling data communication between the chip and the printer and the access operation of the data of the storage module and external data and sending a corresponding control command to the chip according to a safety module processing result so as to realize data communication; and the same keys are stored in the printer and the chip. The invention also provides a data communication method for the chip, the consumable container with the chip structure, and imaging equipment with the consumable container. The safety of the communication data of the chip can be protected.

A system including a device with a first chip and a device with a second chip, to realize contactless communication therebetween. The first chip includes a transmitter circuit converting parallel data into a differential signal and a transmitting antenna transmitting the signal to the second chip. The second chip includes a receiving antenna receiving the differential signal from the transmitting antenna and a receiver circuit converting the differential signal into the parallel data. The transmitting and receiving antenna each include at least two antenna elements, first and second terminals, and first and second junctions. The antenna elements consist of wiring lines on the chips. The terminals are connected with circuits on the chips. At the first junction, first ends of the antenna elements meet to connect to the first terminal. At the second junction, second ends of the antenna elements meet to connect to the second terminal.

A bumped wafer for use in making a chip device. The bumped wafer includes two titanium layers sputtered alternatingly with two copper layers over a non-passivated die. The bumped wafer further includes under bump material under solder bumps contained thereon.

A low-current FN channel scheme for erase, program, program-inhibit and read operations is disclosed for NAND NVM memories. This invention discloses a block array architecture and 3-step half-page program algorithm to achieve less error rate of NAND cell threshold voltage level. Thus, the error correction code capability requirement can be reduced, thus the program yield can be increased to reduce the overall NAND die cost at advanced nodes below 20 nm. As a result, this NAND array can still use the LV, compact PGM buffer for saving in the silicon area and power consumption. In addition, the simpler on-chip state-machine design can be achieved with the superior quality of less program errors.

A management method and device of Ethernet chip output quene is that a single/multi message control separation module outputs queue from the frame control module based on single, multimessage separation way of each interface, the single data frame control module sets single-message queue in mode with multiple priority queue and uses congestion control algorithm to safeguard the single queue, the multiple one organizes in a way of FIFO queue to apply congestion control algorithm to directly discard queue end then carry out single/multi message priority quene matched arrangement. After interface dispatch between interfaces and priority dispatch inside interface in output quene dispatches, if single/multiple in priority.

A preferably CMOS-implementable system measures distance and/or brightness by illuminating a target with emitted optical energy having a modulated periodic waveform whose high frequency component may be idealized as S.sub.1=cos(.omega..multidot.t). A fraction of the emitted optical energy is reflected by a target and detected with at least one in a plurality of semiconductor photodetectors. Photodetector quantum efficiency is modulated to process detected signals to yield data proportional to the distance z separating the target and photodetector. Detection includes measuring phase change between the emitted optical energy and the reflected fraction thereof. Quantum efficiency can be modulated with fixed or variable phase methods and may be enhanced using enhanced photocharge collection, differential modulation, and spatial and temporal multiplexing. System power requirements may be reduced with inductors that resonate with photodetector capacitance at the operating frequency. The system includes on-chip photodetectors, associated electronics, and processing.

Certain embodiments of the invention may be found in a method and system for a vestigial side band (VSB), quadrature amplitude modulation (QAM), NTSC, out-of-band (OOB) receiver that is integrated in a single chip. The single chip integrated digital television (DTV) receiver provides plug and play DTV receiver capability for handling both North American digital cable television and digital terrestrial broadcast television compatible systems. The integrated DTV receiver may receive all standard-definition and high-definition digital formats (SDTV/HDTV) and an on-chip NTSC demodulator handles NTSC video. An output of the NTSC demodulator may be directed to an external broadcast television system committee (BTSC) or Zweiton M decoder, or it may be sent to an on-chip audio BTSC compliant decoder. The single chip integrated DTV receiver may also comprise an integrated out-of-band QPSK receiver, which may be adapted to, for example, handle a CableCard compliant with the CableCard Specification.