39705 results about "Chip" patented technology

A bonded structure is disclosed. The bonded structure can include a carrier. The bonded structure can include a first die having a first communications circuitry to format a communication signal according to a first communication protocol and to transmit the communication signal. The bonded structure can also include a protocol switch die having circuitry to receive the communications signal and to convert the communication signal from the first communication protocol to a second communication protocol, wherein the second communication protocol is different from the first communication protocol. The protocol switch die can transmit the communication signal according to the second communication protocol. The bonded structure can also include a second die having a second communications circuitry to receive the communication signal formatted in the second communication protocol.

The embodiment of the invention provides a cross-chip platform compiling tool chain method which comprises the following steps: scanning a target platform architecture specification file to extract instruction set features, constructing a platform difference matrix based on the instruction set features to record instruction formats and system call differences of different chip platforms, and normalizing a multi-language syntax tree into a unified intermediate representation; constructing a cross-platform compiler to convert the intermediate representation into a target code; designing a unified intermediate language based on a platform difference matrix to support multi-language compilation; creating an instruction mapper to convert the intermediate representation into a target platform instruction; identifying a target architecture type through a platform identification code; designing a test case to verify a compiling result, and deploying the optimized target program to a target platform; according to the method and the device, the expandability and the code quality of the compiling tool chain can be improved by constructing the unified intermediate presentation layer and the optimization framework, and more efficient cross-platform support is realized.

The invention provides an electromagnetic interference suppression method and system for a chip, and relates to the technical field of intelligent chips, and the method comprises the steps: obtaining layout data of a target chip, and based on the layout data, extracting structure parameters and device parameters through an image segmentation algorithm, and constructing a multi-physics field coupling simulation model; the method comprises the following steps: determining an optimal excitation source corresponding to a target chip through a machine learning algorithm, calculating to obtain transient multi-physical field distribution by adopting a time domain finite element method and through an adaptive time step control strategy, extracting time-frequency domain multi-scale distribution characteristics, and constructing a spectrum fingerprint database of electromagnetic interference by utilizing a deep convolutional neural network. Generating an electromagnetic interference identification result; and based on an electromagnetic interference identification result, determining an optimal suppression circuit topology through a suppression topology search algorithm, determining optimal suppression device parameters through a multi-objective optimization algorithm in combination with electromagnetic compatibility index constraints, and generating an electromagnetic interference suppression strategy.

The invention relates to the technical field of probe testing, and discloses a probe testing device and method, and the method comprises the steps: carrying out the synchronous collection of the electric signal response characteristics of a plurality of chip testing probes in a chip contact process, analyzing the signal transmission interference relation between the probes, and obtaining a multi-probe signal coupling feature pattern; identifying a target signal transmission channel to obtain a first test probe configuration scheme; performing test signal input and response acquisition on the chip to obtain electrical characteristic time-frequency data of the chip; and performing multi-probe collaborative analysis and feature extraction on the time-frequency data of the electrical characteristics of the chip to obtain abnormal indication information of the electrical performance of the chip, and adjusting test parameters and contact positions of a plurality of chip test probes to obtain a configuration scheme of a second test probe. Therefore, the test system can intelligently adjust the subsequent test strategy according to the preliminary test result, and the intelligence and automation of the test process are realized.

The invention relates to the technical field of chip design, in particular to a system-on-chip design method and system and a medium. The method comprises the following steps that a chip design target and basic parameters are collected, a constraint condition set is generated through demand constraint analysis, the basic parameters of a system are subjected to parallel recombination, functional prototype data are generated, the functional prototype data are used for chip behavior design, functional unit groups are generated, a network architecture is reconstructed to form a functional module network, and the functional module network is used for chip behavior design. And carrying out clock domain mapping and competition compensation processing based on the network to obtain a function scheduling sequence, carrying out resource matrix remapping on the basic parameters according to the function scheduling sequence, generating hardware abstract data, carrying out chip layout simulation, and finally generating a simulation chip blueprint. According to the system-on-chip design method, the more efficient system-on-chip design method is achieved.

The invention relates to the technical field of chip testing, and provides a chip temperature characteristic testing method, system and equipment, and the method comprises the steps: obtaining transient thermal response data and steady-state thermal distribution data of a chip, carrying out the feature extraction of the transient thermal response data, obtaining a feature thermal mode set, and carrying out the feature extraction of the feature thermal mode set; performing heat transfer analysis on the steady-state heat distribution data by utilizing the characteristic heat mode set to obtain a long-term temperature drift curve; and evaluating the long-term temperature drift curve to obtain a thermal reliability score and a thermal degradation prediction parameter, and generating life prediction data of the chip based on the thermal reliability score and the thermal degradation prediction parameter. By combining the analysis of transient thermal response data and steady-state thermal distribution data, the accuracy and reliability of temperature characteristic test are improved, and the problem that the traditional method is difficult to accurately capture the transient change characteristic of the chip temperature and identify the long-term temperature drift trend under a dynamic working condition or a complex load condition, and the test accuracy is insufficient is solved.

The invention relates to the technical field of integrated circuit test and calibration, and discloses a chip test and calibration method and a chip tester. The chip test calibration method is applied to a chip test module and specifically comprises the following steps that S101, a starting signal sent by a user terminal is received, environment initialization operation is executed, and after initialization is completed, a system automatically enters a standby mode and waits for an external trigger signal or a user instruction; and S102, synchronously capturing input and output signal waveforms of the tested chip at a preset sampling frequency through a high-precision current sensor and a voltage sampling circuit. Through a dynamic parameter acquisition and real-time compensation technology, a voltage reference error is effectively reduced, the temperature control precision is superior to + / -0.3 DEG C, signal distortion caused by environmental interference is effectively inhibited, a multi-dimensional calibration model is combined with time domain, frequency domain and statistical characteristic analysis, nonlinear errors and system drift can be dynamically corrected, and the system performance is improved. And the attenuation error of a test signal transmission path is lower than 0.02 dB.

The invention provides a chip overheating automatic protection control method and system, and relates to the technical field of chip protection, and the method comprises the steps: arranging distributed temperature sensors on a chip, obtaining the real-time temperature data of different regions in the chip, dynamically adjusting the data collection frequency and precision, and generating an optimized temperature data flow; and inputting the optimized temperature data stream into a pre-trained temperature anomaly detection model, detecting the temperature anomaly condition of each region in the chip in real time, outputting the temperature anomaly level of the abnormal region, and triggering thermal emergency processing of different intensities according to the temperature anomaly level. The temperature and power consumption information of the abnormal area is sent to the global manager; the method comprises the following steps: generating an initial chip protection strategy, predicting a future temperature change trend of a chip, identifying a potential high-temperature abnormal region, optimizing the initial chip protection strategy by combining a prediction result, generating an optimal chip protection strategy, and realizing chip overheating automatic protection control according to the optimal chip protection strategy.

The invention relates to the field of chip verification, and provides a chip verification method, device and equipment, a medium and a chip. The method comprises the following steps: establishing a dynamic simulation verification environment of a to-be-verified design, and generating a plurality of test scenes and corresponding test excitation according to a design specification definition; sending the test excitation to a driver through a sequencer, converting the test excitation into a signal conforming to a to-be-verified design interface protocol by the driver, and transmitting the signal to the to-be-verified design; the monitor collects an input signal and an output signal of a to-be-verified design in real time, converts the input signal and the output signal into transactions, and transmits the transactions to the scoreboard; comparing the reference model with an output signal of the to-be-verified design to generate a dynamic simulation verification result; according to the dynamic simulation result, the state space is reduced, state space traversal is carried out on a design part which is not covered by dynamic simulation in the design to be verified, and a formal verification analysis result is generated; and evaluating the to-be-verified design according to the formal verification analysis result.

The invention relates to the technical field of semiconductors, and discloses a full-temperature-zone polynomial digital temperature compensation method and system based on an SOI chip, and the method comprises the steps: obtaining the temperature frequency data of a preset temperature zone of a target SOI chip, fitting a full-temperature-zone curve, extracting a critical point of the temperature zone, dividing a segmented compensation interval according to the critical point, and obtaining the temperature frequency data of the preset temperature zone of the target SOI chip; the method comprises the following steps: calculating frequency drift amounts under different voltages to construct a full-automatic test framework, acquiring an environment temperature parameter and an instantaneous temperature value by using the framework, analyzing a temperature compensation vector of a segmented compensation interval, further monitoring a signal frequency interval output by a chip, extracting a phase noise parameter, calculating a frequency offset error amount with a preset value, and calculating the frequency offset error amount. And analyzing an error source, optimizing a polynomial compensation order, and collecting temperature drift suppression data to generate a full temperature region compensation report. According to the invention, the performance stability of the chip in a complex environment can be improved.

An FPGA-based accelerator for bootstrappable fully homomorphic encryption (FHE) employs (1) acceleration of scalar arithmetic operations using a multi-word approach for efficient utilization of standard-width components (multipliers / adders) on custom-width operands; (2) a performant, shift-based modular reduction technique that avoids the need for expensive multipliers; (3) an improved datapath for an expensive Key Switch operation; and (4) an efficient organization of on-chip memory for storing custom-width operands and supplying them at high bandwidth to computation units.

The invention belongs to the field of switching chips, and relates to a message processing and transmitting device on a CXL switching chip, which comprises a CXL switching interface unit module, an annular topological network on chip and a CXL management unit module, the CXL switching interface unit module is used for receiving and analyzing messages of two sub-protocols, namely. Cache and. Mem, sent by CXL equipment directly connected to a CXL switching chip, then converting and packaging the messages into a message format conforming to the standard of the network on the circular topology chip, and further transmitting the messages through the network on the circular topology chip; and meanwhile, the CXL switching interface unit module also needs to receive the message from the ring topology network-on-chip, converts and packages the message into a corresponding CXL sub-protocol message format, and then distributes the message to other CXL equipment. The method has the characteristics of high bandwidth, low delay and multi-channel concurrency, and provides an efficient transmission channel for a large amount of memory data access scene; and the method has the advantages of high expandability, friendliness to chip back-end physics and the like.

The invention relates to the technical field of chip aging tests, and discloses a chip aging test fixture control method and device and a storage medium, and the method comprises the steps: carrying out the parameter collection of a test fixture, and obtaining original test data; performing control signal analysis and signal fusion, and inputting a fused temperature control instruction into a temperature control unit of the test fixture to obtain steady-state test data; performing multi-dimensional analysis and data screening to obtain effective test data; performing performance feature extraction to obtain performance feature data; grouping is carried out, the weight coefficient of each test channel is calculated, weighting processing is carried out in combination with a failure mode standard, and aging characteristic data is obtained; and inputting the aging characteristic data into the life prediction model to calculate a performance prediction value and a life prediction value to obtain a chip aging test result, the chip performance degradation characteristics can be accurately captured, the performance prediction value and the life prediction value are output at the same time, and a comprehensive aging evaluation result is provided.

The invention relates to the technical field of synchronization in data communication, and provides a PTP protocol-based chip-level hardware timestamp generation method and system, and the method comprises the steps: 1, receiving a synchronization message and a delay request message from a main clock, carrying out the evaluation of a physical layer signal, and recording a first hardware timestamp; 2, responding to the received delay request message, generating and sending a delay response message, acquiring bidirectional transmission delay data by exchanging the delay request and the delay response message, and calculating clock skew in combination with the first hardware timestamp and the bidirectional transmission delay data; 3, adjusting the local clock frequency according to the clock skew; 4, after the synchronization is completed, associating the second hardware timestamp with the corresponding data message, and storing the associated data in a buffer area in the chip; and 5, generating standardized timestamp information, and outputting the standardized timestamp information through a chip interface. And high-precision time synchronization and timestamp generation are realized.

The invention relates to the technical field of streaming media decoding, and discloses a streaming media decoding method and device for a network high-definition player and a storage medium, and the method comprises the steps: carrying out the multi-thread parallel collection and storage of real-time temperature data, network bandwidth jitter data and video code rate fluctuation data of a decoding chip in the network high-definition player; obtaining a streaming media dynamic feature data set; performing classification training to obtain an inter-frame correlation prediction model; constructing a multi-stage streaming media caching system based on the inter-frame correlation prediction model; monitoring a cache state, a network state and a chip state in the multi-stage streaming media cache system in real time to obtain a decoding event sequence; according to the decoding event sequence, the decoding parameter is adjusted in real time, and the streaming media decoding control instruction is obtained.The collaborative optimization of a network layer, a decoding layer and a display layer is achieved, the playing starting delay is reduced, and the overall stability of a network high-definition player is improved.

The invention relates to the technical field of chip heat dissipation, and discloses a photoelectric co-packaging heterogeneous chip heat dissipation integration method, device and equipment, and the method comprises the steps: carrying out the finite element modeling analysis of a photoelectric co-packaging heterogeneous chip, and obtaining a three-dimensional thermal characteristic model; performing signal acquisition and frequency domain characteristic analysis on each functional module of the photoelectric co-packaged heterogeneous chip to generate power consumption prediction data; performing temperature field distribution calculation on the photoelectric co-packaging heterogeneous chip according to the power consumption prediction data and the three-dimensional thermal characteristic model, and constructing a temperature outer ring control model and a heat flow inner ring control model; and performing heat dissipation structure layout optimization calculation based on the temperature outer ring control model and the heat flow inner ring control model, and generating a hybrid heat dissipation layout scheme. Dynamic distribution of heat dissipation power and automatic threshold adjustment are realized, frequent mode switching is avoided, and the thermal characteristic stability of a chip is improved.

The invention relates to an ultrahigh-voltage silicon carbide start control chip protection method and system, and the method comprises the steps: obtaining the operation parameters and composite structure characteristic data of an ultrahigh-voltage silicon carbide start control chip, and carrying out the TVS-MOSFET hierarchical characteristic analysis, and obtaining the real-time state information of the chip; acquiring a grid charging curve of the ultrahigh-voltage silicon carbide starting control chip, and performing correlation analysis on the grid charging curve and the real-time state information of the chip to obtain a multi-threshold protection parameter; acquiring current change data of the ultrahigh-voltage silicon carbide starting control chip, and performing Miller platform feature analysis on the real-time state information of the chip to obtain a current abnormal trend; performing temperature control construction on a multi-threshold protection parameter and the current abnormal trend to obtain an initial control scheme; and carrying out clamping turn-off strategy construction on the initial control scheme and the potential fault area to obtain a chip start protection strategy. Optimized starting protection of the chip can be achieved through the comprehensive adjustment strategy, and therefore the service life of the chip is effectively prolonged.

The invention provides a chip production logistics optimization method and system based on a multi-target genetic algorithm, and relates to the technical field of chip production scheduling, and the method comprises the steps: collecting the real-time operation data of a production line, extracting task execution features and equipment layout features through a dual-channel deep neural network, and carrying out the feature fusion through a recurrent neural network, generating a production state vector containing a multi-dimensional scheduling index predicted value; constructing a multi-dimensional optimization target set based on the production state vector, and generating an initial population by adopting a double-layer gene coding structure; executing non-dominated sorting and crowding degree distance calculation based on the fitness value, and selecting high-quality individuals to form a parent population; and performing adaptive crossover, tabu search optimization and adaptive mutation operation on the parent population, iteratively selecting a new generation of population until convergence, and outputting an optimal scheduling scheme.

The invention relates to the technical field of automatic debugging, in particular to a digital twinning-based chip fixture debugging system, which comprises a state sensing fusion module, a positioning correction judgment module, a contact adjustment execution module, a closed-loop feedback correction module and a data linkage optimization module. According to the method, through time axis synchronous matching of multiple types of sensing data, extraction of position offset and pressure sudden change intersection features, enhancement of direction identification and dynamic precision, angle direction trend quantification through included angle interval analysis, improvement of spatial positioning continuity, and guarantee of effective response of an adjustment window through driving rate difference comparison, the accuracy of the adjustment window is improved, and the accuracy of the adjustment window is improved. Stretching and deformation data backtracking are introduced to improve the path correction capability, a virtual and real link is constructed in combination with a node log and a delay identifier, the consistency of simulation and actual behaviors is constrained, the overall debugging process is optimized through data linkage and time sequence control collaboratively, and higher response timeliness, posture recognition precision and data fusion stability are achieved.

The invention discloses a container tracking management system and method. The method comprises the following steps: S1, carrying out dynamic encryption binding and multi-dimensional data acquisition on an RFID chip; s2, realizing real-time position data acquisition of the container under different environmental conditions through a multi-source signal fusion and error correction algorithm; s3, various sensor modules are installed inside and outside the container, and data processing is carried out through distributed edge nodes; s4, performing on-chain storage on total data generated in the transportation process through a Hash encryption algorithm, and realizing automatic data verification, state tracking and abnormity alarm in combination with an intelligent contract; s5, carrying out real-time dynamic modeling analysis on the transportation path and resource allocation, and dynamically adjusting the transportation plan by using a distributed scheduling strategy; and S6, integrating the real-time state data, the path optimization model and the transportation scheduling decision, and providing a report for a user. The method has the advantages of high positioning precision, high data security, high transportation efficiency and good real-time performance.

Aspects relate to an expanded data link width for a chip connection. In one example a sideband transmitter of a module of a first die is configured to send an expanded data link width enable request to a module partner through a sideband of a die-to-die connection to set an expanded data link width of a main band of the die-to-die connection. The expanded data link width includes data lines of the main band and redundant data lines of the main band reconfigured as data lines. A sideband receiver of the module is configured to receive an expanded data link width enable response from the module partner through the sideband to set the expanded data link width of the main band. A main band transmitter is configured to communicate data with the module partner through the main band using the expanded data link width.

The invention relates to the technical field of chip testing, in particular to a chip aging test and analysis method, which comprises the following steps of: constructing an aging parameter matrix containing process deviation, electrical parameters and thermodynamic parameters on the basis of fusion of wafer level and packaged test data, multi-stress cooperative loading is realized through a programmable power supply and a multi-zone temperature control array, transient electric signals, thermal imaging data and leakage current frequency spectrums are acquired in real time, an electrical-thermal coupling coefficient and a process deviation sensitivity factor are extracted in a cross-dimension manner, a non-linear recession model is established, differential aging paths of chip functional blocks are evaluated, and the reliability of the chip functional blocks is improved. And based on the dynamic life prediction model and a fault early warning mechanism, generating and executing an adaptive test optimization strategy to realize early prediction and stress adjustment of multiple failure modes. According to the invention, the efficiency and accuracy of the aging test can be obviously improved, and technical support is provided for high-reliability evaluation of deep submicron and post-mole times of chips.

The invention relates to the technical field of chip heat management, and discloses a chip heat distribution prediction modeling method and device, and the method comprises the steps: obtaining chip design information, carrying out the three-dimensional grid division through a pre-training transfer learning neural network, and constructing an electricity-heat-force multi-physics field coupling model; the method comprises the following steps: monitoring operation load data in real time, carrying out thermal simulation and generating a temperature distribution characteristic matrix, collecting data through a temperature sensor array, simulating thermal diffusion by using particle filtering and Bayesian inference, compressing and reconstructing the temperature distribution characteristic matrix by using a variational auto-encoder, generating a digital twinborn body, and optimizing a heat dissipation strategy by using deep reinforcement learning. The temperature control strategy is generated, the chip heat management precision is improved, the heat dissipation strategy is optimized, the performance and stability are improved, and the problem of insufficient prediction of temperature distribution in a traditional heat management scheme in the prior art is solved.

The invention relates to a water quality real-time detection system which comprises the following modules: a multi-source sensing module which is based on a multi-parameter sensing array, adopts a self-adaptive sampling strategy, realizes sensor time sequence synchronization through a state estimation algorithm, completes water body multi-dimensional parameter acquisition in combination with a micro-fluidic chip, generates a multi-modal sensing data set, and transmits the multi-modal sensing data set to a data processing module; the multi-source sensing module comprises a multi-source sensing sub-module, a signal conditioning sub-module, a time sequence synchronization sub-module and an anomaly capture sub-module. The method has the advantages that through the synergistic effect of the adaptive sampling strategy and the state estimation algorithm, the multi-sensor time sequence synchronization precision is remarkably improved, the phase deviation problem caused by traditional fixed frequency sampling is effectively eliminated, the sliding window polynomial fitting is combined with the wavelet threshold de-noising technology, and the multi-sensor time sequence synchronization precision is improved. High-frequency noise interference is greatly suppressed on the premise that effective components of the signals are reserved, and meanwhile, the abnormal value detection accuracy is improved through a dynamic threshold mechanism.

Provided is a method for wireless communication. The method includes: transmitting, by an access point device, a first signal, wherein the first signal comprises a first signal portion and a second signal portion, wherein the first signal portion is transmitted over a conventional 802.11 radio interface, and the second signal portion is transmitted over a zero-power radio interface, the first signal portion comprising a first preamble signal.

The invention relates to the technical field of chip development, and discloses a chip post-simulation verification acceleration method, system and device and a storage medium, and the method comprises the steps: collecting multi-dimensional data of a large-scale chip; collecting all module names of a given chip; establishing a mapping relation between a redundant module RTL and a corresponding gate-level netlist, ensuring that interfaces before and after replacement are completely consistent, and designing an automatic script identification and processing parameterization module; establishing a post-simulation verification environment, verifying the consistency of output responses before and after replacement, analyzing the time delay change of a key path, calculating the dynamic power consumption and static power consumption of each functional module before and after replacement, and generating a simulation verification result. According to the method, the hybrid simulation model is constructed, and part of the gate-level netlist irrelevant to the current simulation function is replaced with the RTL, so that the actual simulation scale of a chip is reduced, the problem of overlong simulation time after a large-scale integrated circuit is remarkably solved, and the simulation efficiency is effectively improved.

The embodiment of the invention provides a data processing method, end side equipment, a storage medium, a chip system and a computer program product, and relates to the technical field of terminals. Due to the fact that the second expert modules in the first storage are formed in the mode that the second thread executes the preloading process based on the expert preference strategy of the first request under the condition that the first thread executes the prefilling stage process through the first model, parallel execution of the preloading process and the prefilling stage process is achieved, I / O delay is reduced, and the processing efficiency is improved. And the reasoning efficiency of the first model is improved. And because the first request has expert preference, and the plurality of second expert modules stored in the first memory are determined according to the first request, the first thread performs the decoding stage flow by using the first model, and the second thread performs the decoding stage flow by using the second model. The first thread can directly obtain the second expert module corresponding to the first expert module from the first storage, so that the cache hit rate is improved, and the reasoning efficiency of the first model is improved.

The invention relates to the technical field of data packet transmission, and discloses a data packet transmission control method and device for a low-power-consumption dual-mode Bluetooth chip, and the method comprises the steps: obtaining a signal strength parameter, a power consumption parameter, a transmission rate parameter and an environment parameter of the dual-mode Bluetooth chip, inputting the parameters into a deep time convolution network, and carrying out the time sequence feature extraction, obtaining a transmission mode switching judgment result; calculating transmission state evaluation data; the chip transmitting power is adjusted in a grading mode, standby power consumption is controlled through a nanoamp LDO circuit, and a dynamic power control parameter is obtained; performing compression coding on the data packet to obtain a dual-mode transmission protocol configuration parameter; executing time sequence sampling, and constructing a dual-mode state feature sequence; the data packet delivery success rate, the end-to-end transmission time delay and the total power consumption of the system are calculated, transmission control parameter optimization is carried out through double-layer deep reinforcement learning, target transmission control parameters are obtained, and the optimal balance of the transmission performance and the power consumption of the dual-mode Bluetooth chip is achieved.

The invention discloses a clock tree synthesis method and related equipment, and the method comprises the steps: dividing a plurality of time sequence units which need to receive clock signals from a clock source into clustering clusters of different levels, and enabling the load capacitance of each clustering cluster of the same level to be balanced; according to a hierarchical sequence of clusters starting from the clock source, taking each cluster as a node of a clock tree, recursively constructing the clock tree, and inserting a target buffer at the position of each node for driving the corresponding node; analyzing the delay and offset of the constructed clock tree to obtain an analysis result; and if the analysis result indicates that the delay and offset of the clock tree do not meet the preset constraint condition, adjusting the clock tree until the adjusted delay and offset of the clock tree meet the preset constraint condition. According to the technical scheme, power consumption and offset can be effectively reduced, calculation efficiency and design reliability are improved, and the method is suitable for high-performance chip design under the advanced technology.

The invention relates to the technical field of chip testing, and discloses a chip power supply noise influence testing method and device. The method comprises the following steps: carrying out multi-dimensional data acquisition on a chip power supply by utilizing a multi-mode sensing array to obtain original sensing data, and carrying out time synchronization calibration and signal preprocessing to obtain high-quality multi-dimensional data; carrying out time-frequency domain decomposition and correlation calculation on the processed data, and carrying out time delay and position calculation to determine noise source distribution; noise source distribution is mapped to a chip layout, multi-physical field calculation is carried out, a coupling propagation matrix is generated, and a noise propagation characteristic spectrum is obtained through characteristic value decomposition and path calculation; and designing a test condition based on the propagation characteristic spectrum, performing a chip function module performance test, establishing a response relationship between noise and function performance, determining a function failure noise critical value and a tolerance boundary, and forming a complete power supply noise influence test result. According to the method, the accurate positioning of the chip power supply noise is realized, and the evaluation accuracy of the power supply noise influence is improved.